Thomas Gleixner | a61127c | 2019-05-29 16:57:49 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright © 2006, Intel Corporation. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 4 | */ |
| 5 | #ifndef _ASYNC_TX_H_ |
| 6 | #define _ASYNC_TX_H_ |
| 7 | #include <linux/dmaengine.h> |
| 8 | #include <linux/spinlock.h> |
| 9 | #include <linux/interrupt.h> |
| 10 | |
Dan Williams | 06164f3 | 2009-03-25 09:13:25 -0700 | [diff] [blame] | 11 | /* on architectures without dma-mapping capabilities we need to ensure |
| 12 | * that the asynchronous path compiles away |
| 13 | */ |
| 14 | #ifdef CONFIG_HAS_DMA |
| 15 | #define __async_inline |
| 16 | #else |
| 17 | #define __async_inline __always_inline |
| 18 | #endif |
| 19 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 20 | /** |
| 21 | * dma_chan_ref - object used to manage dma channels received from the |
| 22 | * dmaengine core. |
| 23 | * @chan - the channel being tracked |
| 24 | * @node - node for the channel to be placed on async_tx_master_list |
| 25 | * @rcu - for list_del_rcu |
| 26 | * @count - number of times this channel is listed in the pool |
| 27 | * (for channels with multiple capabiities) |
| 28 | */ |
| 29 | struct dma_chan_ref { |
| 30 | struct dma_chan *chan; |
| 31 | struct list_head node; |
| 32 | struct rcu_head rcu; |
| 33 | atomic_t count; |
| 34 | }; |
| 35 | |
| 36 | /** |
| 37 | * async_tx_flags - modifiers for the async_* calls |
| 38 | * @ASYNC_TX_XOR_ZERO_DST: this flag must be used for xor operations where the |
Randy Dunlap | 121ae8d | 2020-08-11 18:34:04 -0700 | [diff] [blame] | 39 | * destination address is not a source. The asynchronous case handles this |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 40 | * implicitly, the synchronous case needs to zero the destination block. |
| 41 | * @ASYNC_TX_XOR_DROP_DST: this flag must be used if the destination address is |
| 42 | * also one of the source addresses. In the synchronous case the destination |
| 43 | * address is an implied source, whereas the asynchronous case it must be listed |
| 44 | * as a source. The destination address must be the first address in the source |
| 45 | * array. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 46 | * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a |
| 47 | * dependency chain |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 48 | * @ASYNC_TX_FENCE: specify that the next operation in the dependency |
| 49 | * chain uses this operation's result as an input |
Markus Stockhausen | 584acdd | 2014-12-15 12:57:05 +1100 | [diff] [blame] | 50 | * @ASYNC_TX_PQ_XOR_DST: do not overwrite the syndrome but XOR it with the |
| 51 | * input data. Required for rmw case. |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 52 | */ |
| 53 | enum async_tx_flags { |
| 54 | ASYNC_TX_XOR_ZERO_DST = (1 << 0), |
| 55 | ASYNC_TX_XOR_DROP_DST = (1 << 1), |
Dan Williams | 88ba2aa | 2009-04-09 16:16:18 -0700 | [diff] [blame] | 56 | ASYNC_TX_ACK = (1 << 2), |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 57 | ASYNC_TX_FENCE = (1 << 3), |
Markus Stockhausen | 584acdd | 2014-12-15 12:57:05 +1100 | [diff] [blame] | 58 | ASYNC_TX_PQ_XOR_DST = (1 << 4), |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 61 | /** |
| 62 | * struct async_submit_ctl - async_tx submission/completion modifiers |
| 63 | * @flags: submission modifiers |
| 64 | * @depend_tx: parent dependency of the current operation being submitted |
| 65 | * @cb_fn: callback routine to run at operation completion |
| 66 | * @cb_param: parameter for the callback routine |
| 67 | * @scribble: caller provided space for dma/page address conversions |
| 68 | */ |
| 69 | struct async_submit_ctl { |
| 70 | enum async_tx_flags flags; |
| 71 | struct dma_async_tx_descriptor *depend_tx; |
| 72 | dma_async_tx_callback cb_fn; |
| 73 | void *cb_param; |
| 74 | void *scribble; |
| 75 | }; |
| 76 | |
Dan Williams | b802c84 | 2017-02-15 18:42:09 -0800 | [diff] [blame] | 77 | #if defined(CONFIG_DMA_ENGINE) && !defined(CONFIG_ASYNC_TX_CHANNEL_SWITCH) |
Dan Williams | 2ba0562 | 2009-01-06 11:38:14 -0700 | [diff] [blame] | 78 | #define async_tx_issue_pending_all dma_issue_pending_all |
Dan Williams | 95475e5 | 2009-07-14 12:19:02 -0700 | [diff] [blame] | 79 | |
| 80 | /** |
| 81 | * async_tx_issue_pending - send pending descriptor to the hardware channel |
| 82 | * @tx: descriptor handle to retrieve hardware context |
| 83 | * |
| 84 | * Note: any dependent operations will have already been issued by |
| 85 | * async_tx_channel_switch, or (in the case of no channel switch) will |
| 86 | * be already pending on this channel. |
| 87 | */ |
| 88 | static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx) |
| 89 | { |
| 90 | if (likely(tx)) { |
| 91 | struct dma_chan *chan = tx->chan; |
| 92 | struct dma_device *dma = chan->device; |
| 93 | |
| 94 | dma->device_issue_pending(chan); |
| 95 | } |
| 96 | } |
Dan Williams | 47437b2 | 2008-02-02 19:49:59 -0700 | [diff] [blame] | 97 | #ifdef CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL |
| 98 | #include <asm/async_tx.h> |
| 99 | #else |
| 100 | #define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \ |
| 101 | __async_tx_find_channel(dep, type) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 102 | struct dma_chan * |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 103 | __async_tx_find_channel(struct async_submit_ctl *submit, |
| 104 | enum dma_transaction_type tx_type); |
Dan Williams | 47437b2 | 2008-02-02 19:49:59 -0700 | [diff] [blame] | 105 | #endif /* CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL */ |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 106 | #else |
| 107 | static inline void async_tx_issue_pending_all(void) |
| 108 | { |
| 109 | do { } while (0); |
| 110 | } |
| 111 | |
Dan Williams | 95475e5 | 2009-07-14 12:19:02 -0700 | [diff] [blame] | 112 | static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx) |
| 113 | { |
| 114 | do { } while (0); |
| 115 | } |
| 116 | |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 117 | static inline struct dma_chan * |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 118 | async_tx_find_channel(struct async_submit_ctl *submit, |
| 119 | enum dma_transaction_type tx_type, struct page **dst, |
| 120 | int dst_count, struct page **src, int src_count, |
| 121 | size_t len) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 122 | { |
| 123 | return NULL; |
| 124 | } |
| 125 | #endif |
| 126 | |
| 127 | /** |
| 128 | * async_tx_sync_epilog - actions to take if an operation is run synchronously |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 129 | * @cb_fn: function to call when the transaction completes |
| 130 | * @cb_fn_param: parameter to pass to the callback routine |
| 131 | */ |
| 132 | static inline void |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 133 | async_tx_sync_epilog(struct async_submit_ctl *submit) |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 134 | { |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 135 | if (submit->cb_fn) |
| 136 | submit->cb_fn(submit->cb_param); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 137 | } |
| 138 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 139 | typedef union { |
| 140 | unsigned long addr; |
| 141 | struct page *page; |
| 142 | dma_addr_t dma; |
| 143 | } addr_conv_t; |
| 144 | |
| 145 | static inline void |
| 146 | init_async_submit(struct async_submit_ctl *args, enum async_tx_flags flags, |
| 147 | struct dma_async_tx_descriptor *tx, |
| 148 | dma_async_tx_callback cb_fn, void *cb_param, |
| 149 | addr_conv_t *scribble) |
| 150 | { |
| 151 | args->flags = flags; |
| 152 | args->depend_tx = tx; |
| 153 | args->cb_fn = cb_fn; |
| 154 | args->cb_param = cb_param; |
| 155 | args->scribble = scribble; |
| 156 | } |
| 157 | |
| 158 | void async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, |
| 159 | struct async_submit_ctl *submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 160 | |
| 161 | struct dma_async_tx_descriptor * |
| 162 | async_xor(struct page *dest, struct page **src_list, unsigned int offset, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 163 | int src_cnt, size_t len, struct async_submit_ctl *submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 164 | |
| 165 | struct dma_async_tx_descriptor * |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 166 | async_xor_offs(struct page *dest, unsigned int offset, |
| 167 | struct page **src_list, unsigned int *src_offset, |
| 168 | int src_cnt, size_t len, struct async_submit_ctl *submit); |
| 169 | |
| 170 | struct dma_async_tx_descriptor * |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 171 | async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, |
Dan Williams | ad283ea | 2009-08-29 19:09:26 -0700 | [diff] [blame] | 172 | int src_cnt, size_t len, enum sum_check_flags *result, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 173 | struct async_submit_ctl *submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 174 | |
| 175 | struct dma_async_tx_descriptor * |
Yufen Yu | 29bcff7 | 2020-08-20 09:22:08 -0400 | [diff] [blame] | 176 | async_xor_val_offs(struct page *dest, unsigned int offset, |
| 177 | struct page **src_list, unsigned int *src_offset, |
| 178 | int src_cnt, size_t len, enum sum_check_flags *result, |
| 179 | struct async_submit_ctl *submit); |
| 180 | |
| 181 | struct dma_async_tx_descriptor * |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 182 | async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 183 | unsigned int src_offset, size_t len, |
| 184 | struct async_submit_ctl *submit); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 185 | |
Dan Williams | a08abd8 | 2009-06-03 11:43:59 -0700 | [diff] [blame] | 186 | struct dma_async_tx_descriptor *async_trigger_callback(struct async_submit_ctl *submit); |
Dan Williams | d2c52b7 | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 187 | |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 188 | struct dma_async_tx_descriptor * |
Yufen Yu | d69454b | 2020-08-20 09:22:10 -0400 | [diff] [blame] | 189 | async_gen_syndrome(struct page **blocks, unsigned int *offsets, int src_cnt, |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 190 | size_t len, struct async_submit_ctl *submit); |
| 191 | |
| 192 | struct dma_async_tx_descriptor * |
Yufen Yu | d69454b | 2020-08-20 09:22:10 -0400 | [diff] [blame] | 193 | async_syndrome_val(struct page **blocks, unsigned int *offsets, int src_cnt, |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 194 | size_t len, enum sum_check_flags *pqres, struct page *spare, |
Yufen Yu | d69454b | 2020-08-20 09:22:10 -0400 | [diff] [blame] | 195 | unsigned int s_off, struct async_submit_ctl *submit); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 196 | |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 197 | struct dma_async_tx_descriptor * |
| 198 | async_raid6_2data_recov(int src_num, size_t bytes, int faila, int failb, |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 199 | struct page **ptrs, unsigned int *offs, |
| 200 | struct async_submit_ctl *submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 201 | |
| 202 | struct dma_async_tx_descriptor * |
| 203 | async_raid6_datap_recov(int src_num, size_t bytes, int faila, |
Yufen Yu | 4f86ff5 | 2020-08-20 09:22:11 -0400 | [diff] [blame] | 204 | struct page **ptrs, unsigned int *offs, |
| 205 | struct async_submit_ctl *submit); |
Dan Williams | 0a82a62 | 2009-07-14 12:20:37 -0700 | [diff] [blame] | 206 | |
Dan Williams | d2c52b7 | 2008-07-17 17:59:55 -0700 | [diff] [blame] | 207 | void async_tx_quiesce(struct dma_async_tx_descriptor **tx); |
Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 208 | #endif /* _ASYNC_TX_H_ */ |