blob: 25222497f82854a9edbe213c144d3a9f4daa9634 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Felipe Balbi4a457872014-06-23 13:20:59 -05002/*
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
Felipe Balbi4a457872014-06-23 13:20:59 -05004 */
5
6/* AM437x SK EVM */
7
8/dts-v1/;
9
10#include "am4372.dtsi"
11#include <dt-bindings/pinctrl/am43xx.h>
12#include <dt-bindings/pwm/pwm.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
Eyal Reizer443ef122018-05-06 10:58:06 +030015#include <dt-bindings/interrupt-controller/irq.h>
Felipe Balbi4a457872014-06-23 13:20:59 -050016
17/ {
18 model = "TI AM437x SK EVM";
19 compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43";
20
21 aliases {
22 display0 = &lcd0;
23 };
24
Lokesh Vutla24a1eb42017-01-18 09:33:24 +053025 chosen {
26 stdout-path = &uart0;
27 };
28
Keerthyfff51e72015-08-18 15:11:14 +053029 /* fixed 32k external oscillator clock */
30 clk_32k_rtc: clk_32k_rtc {
31 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-frequency = <32768>;
34 };
35
Peter Ujfalusidc5eedd2017-12-15 14:09:41 +020036 lcd_bl: backlight {
Felipe Balbi4a457872014-06-23 13:20:59 -050037 compatible = "pwm-backlight";
38 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
39 brightness-levels = <0 51 53 56 62 75 101 152 255>;
40 default-brightness-level = <8>;
41 };
42
43 sound {
Peter Ujfalusi20746c52015-07-02 17:06:18 +030044 compatible = "simple-audio-card";
45 simple-audio-card,name = "AM437x-SK-EVM";
46 simple-audio-card,widgets =
47 "Headphone", "Headphone Jack",
48 "Line", "Line In";
49 simple-audio-card,routing =
50 "Headphone Jack", "HPLOUT",
51 "Headphone Jack", "HPROUT",
52 "LINE1L", "Line In",
53 "LINE1R", "Line In";
54 simple-audio-card,format = "dsp_b";
55 simple-audio-card,bitclock-master = <&sound_master>;
56 simple-audio-card,frame-master = <&sound_master>;
57 simple-audio-card,bitclock-inversion;
58
59 simple-audio-card,cpu {
60 sound-dai = <&mcasp1>;
61 };
62
63 sound_master: simple-audio-card,codec {
64 sound-dai = <&tlv320aic3106>;
65 system-clock-frequency = <24000000>;
66 };
Felipe Balbi4a457872014-06-23 13:20:59 -050067 };
68
Javier Martinez Canillas18ad99d2016-08-01 12:46:57 -040069 matrix_keypad: matrix_keypad0 {
Felipe Balbi4a457872014-06-23 13:20:59 -050070 compatible = "gpio-matrix-keypad";
71
72 pinctrl-names = "default";
73 pinctrl-0 = <&matrix_keypad_pins>;
74
75 debounce-delay-ms = <5>;
Felipe Balbif6b957f2015-04-09 10:59:27 -050076 col-scan-delay-us = <5>;
Felipe Balbi4a457872014-06-23 13:20:59 -050077
78 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
79 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
80
81 col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */
82 &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */
83
84 linux,keymap = <
85 MATRIX_KEY(0, 0, KEY_DOWN)
86 MATRIX_KEY(0, 1, KEY_RIGHT)
87 MATRIX_KEY(1, 0, KEY_LEFT)
88 MATRIX_KEY(1, 1, KEY_UP)
89 >;
90 };
91
92 leds {
93 compatible = "gpio-leds";
94
95 pinctrl-names = "default";
96 pinctrl-0 = <&leds_pins>;
97
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040098 led0 {
Felipe Balbi4a457872014-06-23 13:20:59 -050099 label = "am437x-sk:red:heartbeat";
100 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
101 linux,default-trigger = "heartbeat";
102 default-state = "off";
103 };
104
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -0400105 led1 {
Felipe Balbi4a457872014-06-23 13:20:59 -0500106 label = "am437x-sk:green:mmc1";
107 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
108 linux,default-trigger = "mmc0";
109 default-state = "off";
110 };
111
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -0400112 led2 {
Felipe Balbi4a457872014-06-23 13:20:59 -0500113 label = "am437x-sk:blue:cpu0";
114 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
115 linux,default-trigger = "cpu0";
116 default-state = "off";
117 };
118
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -0400119 led3 {
Felipe Balbi4a457872014-06-23 13:20:59 -0500120 label = "am437x-sk:blue:usr3";
121 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
122 default-state = "off";
123 };
124 };
125
126 lcd0: display {
Tomi Valkeinend73f8252014-12-05 09:39:31 +0200127 compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi";
Felipe Balbi4a457872014-06-23 13:20:59 -0500128 label = "lcd";
129
130 pinctrl-names = "default";
131 pinctrl-0 = <&lcd_pins>;
132
Peter Ujfalusidc5eedd2017-12-15 14:09:41 +0200133 backlight = <&lcd_bl>;
134
Felipe Balbi4a457872014-06-23 13:20:59 -0500135 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
136
137 panel-timing {
138 clock-frequency = <9000000>;
139 hactive = <480>;
140 vactive = <272>;
Tomi Valkeinend73f8252014-12-05 09:39:31 +0200141 hfront-porch = <2>;
142 hback-porch = <2>;
143 hsync-len = <41>;
144 vfront-porch = <2>;
145 vback-porch = <2>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500146 vsync-len = <10>;
147 hsync-active = <0>;
148 vsync-active = <0>;
149 de-active = <1>;
150 pixelclk-active = <1>;
151 };
152
153 port {
154 lcd_in: endpoint {
155 remote-endpoint = <&dpi_out>;
156 };
157 };
158 };
Eyal Reizer443ef122018-05-06 10:58:06 +0300159
160 vmmcwl_fixed: fixedregulator-mmcwl {
161 /*
162 * WL_EN is not SDIO standard compliant. It is an out of band
163 * signal and hard to be dealt with in a standard way by the
164 * SDIO core driver.
165 * So modelling the WL_EN line as a regulator was a natural
166 * choice as the MMC core already deals with MMC supplies.
167 */
168 compatible = "regulator-fixed";
169 regulator-name = "vmmcwl_fixed";
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <1800000>;
172 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
173 enable-active-high;
174 };
Felipe Balbi4a457872014-06-23 13:20:59 -0500175};
176
177&am43xx_pinmux {
178 matrix_keypad_pins: matrix_keypad_pins {
179 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300180 AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
181 AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
182 AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
183 AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500184 >;
185 };
186
187 leds_pins: leds_pins {
188 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300189 AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
190 AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
191 AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
192 AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500193 >;
194 };
195
196 i2c0_pins: i2c0_pins {
197 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300198 AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
199 AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
Felipe Balbi4a457872014-06-23 13:20:59 -0500200 >;
201 };
202
203 i2c1_pins: i2c1_pins {
204 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300205 AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
206 AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
Felipe Balbi4a457872014-06-23 13:20:59 -0500207 >;
208 };
209
210 mmc1_pins: pinmux_mmc1_pins {
211 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300212 AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
213 AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
214 AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
215 AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
216 AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
217 AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
218 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500219 >;
220 };
221
222 ecap0_pins: backlight_pins {
223 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300224 AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
Felipe Balbi4a457872014-06-23 13:20:59 -0500225 >;
226 };
227
228 edt_ft5306_ts_pins: edt_ft5306_ts_pins {
229 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300230 AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
231 AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500232 >;
233 };
234
Darren Etheridge5ccaa6e2014-12-18 21:54:13 +0530235 vpfe0_pins_default: vpfe0_pins_default {
236 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300237 AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
238 AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
239 AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
240 AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
241 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
242 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
243 AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
244 AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
245 AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
246 AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
247 AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
248 AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
249 AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
250 AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
251 AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
Darren Etheridge5ccaa6e2014-12-18 21:54:13 +0530252 >;
253 };
254
255 vpfe0_pins_sleep: vpfe0_pins_sleep {
256 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300257 AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
258 AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
259 AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
260 AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
261 AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
262 AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
263 AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
264 AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
265 AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
266 AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
267 AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
268 AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
269 AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
270 AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
271 AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
Darren Etheridge5ccaa6e2014-12-18 21:54:13 +0530272 >;
273 };
274
Benoit Parrotf8404f12019-12-11 08:07:19 -0600275 clkout1_pin: pinmux_clkout1_pin {
276 pinctrl-single,pins = <
277 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
278 >;
279 };
280
Felipe Balbi4a457872014-06-23 13:20:59 -0500281 cpsw_default: cpsw_default {
282 pinctrl-single,pins = <
283 /* Slave 1 */
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300284 AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
285 AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
286 AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
287 AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
288 AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
289 AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
290 AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
291 AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
292 AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
293 AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
294 AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
295 AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500296
297 /* Slave 2 */
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300298 AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
299 AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
300 AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
301 AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
302 AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
303 AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
304 AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
305 AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
306 AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
307 AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
308 AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
309 AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500310 >;
311 };
312
313 cpsw_sleep: cpsw_sleep {
314 pinctrl-single,pins = <
315 /* Slave 1 reset value */
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300316 AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
317 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
318 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
319 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
320 AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
321 AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
322 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
323 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
324 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
325 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
326 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
327 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
Felipe Balbi4a457872014-06-23 13:20:59 -0500328
329 /* Slave 2 reset value */
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300330 AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
331 AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
332 AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
333 AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
334 AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
335 AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
336 AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
337 AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
338 AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
339 AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
340 AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
341 AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
Felipe Balbi4a457872014-06-23 13:20:59 -0500342 >;
343 };
344
345 davinci_mdio_default: davinci_mdio_default {
346 pinctrl-single,pins = <
347 /* MDIO */
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300348 AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
349 AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
Felipe Balbi4a457872014-06-23 13:20:59 -0500350 >;
351 };
352
353 davinci_mdio_sleep: davinci_mdio_sleep {
354 pinctrl-single,pins = <
355 /* MDIO reset value */
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300356 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
357 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
Felipe Balbi4a457872014-06-23 13:20:59 -0500358 >;
359 };
360
361 dss_pins: dss_pins {
362 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300363 AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
364 AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)
365 AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)
366 AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)
367 AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)
368 AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)
369 AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)
370 AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
371 AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
372 AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)
373 AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)
374 AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)
375 AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)
376 AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)
377 AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)
378 AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)
379 AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)
380 AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)
381 AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)
382 AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)
383 AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)
384 AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)
385 AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)
386 AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
387 AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
388 AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
389 AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
390 AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
Felipe Balbi4a457872014-06-23 13:20:59 -0500391
392 >;
393 };
394
395 qspi_pins: qspi_pins {
396 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300397 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
398 AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
399 AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
400 AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
401 AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
402 AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500403 >;
404 };
405
406 mcasp1_pins: mcasp1_pins {
407 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300408 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
409 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
410 AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
411 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500412 >;
413 };
414
Peter Ujfalusi7155ace2015-07-02 17:06:17 +0300415 mcasp1_pins_sleep: mcasp1_pins_sleep {
416 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300417 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
418 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
419 AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
420 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
Peter Ujfalusi7155ace2015-07-02 17:06:17 +0300421 >;
422 };
423
Felipe Balbi4a457872014-06-23 13:20:59 -0500424 lcd_pins: lcd_pins {
425 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300426 AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
Felipe Balbi4a457872014-06-23 13:20:59 -0500427 >;
428 };
Felipe Balbi221fed32014-12-04 11:01:57 -0600429
430 usb1_pins: usb1_pins {
431 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300432 AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
Felipe Balbi221fed32014-12-04 11:01:57 -0600433 >;
434 };
435
436 usb2_pins: usb2_pins {
437 pinctrl-single,pins = <
Javier Martinez Canillase98ceb22015-11-13 01:53:56 -0300438 AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
Felipe Balbi221fed32014-12-04 11:01:57 -0600439 >;
440 };
Eyal Reizer443ef122018-05-06 10:58:06 +0300441
442 mmc3_pins_default: pinmux_mmc3_pins_default {
443 pinctrl-single,pins = <
444 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */
445 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */
446 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD22) cam1_data4.mmc2_dat0 */
447 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE23) cam1_data5.mmc2_dat1 */
448 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD23) cam1_data6.mmc2_dat2 */
449 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 */
450 >;
451 };
452
453 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
454 pinctrl-single,pins = <
455 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */
456 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */
457 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD22) cam1_data4.mmc2_dat0 */
458 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE23) cam1_data5.mmc2_dat1 */
459 AM4372_IOPAD(0xa00, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD23) cam1_data6.mmc2_dat2 */
460 AM4372_IOPAD(0xa04, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE24) cam1_data7.mmc2_dat3 */
461 >;
462 };
463
464 wlan_pins_default: pinmux_wlan_pins_default {
465 pinctrl-single,pins = <
466 AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */
467 AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */
468 >;
469 };
470
471 wlan_pins_sleep: pinmux_wlan_pins_sleep {
472 pinctrl-single,pins = <
473 AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */
474 AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */
475 >;
476 };
477
478 uart1_bt_pins_default: pinmux_uart1_bt_pins_default {
479 pinctrl-single,pins = <
480 AM4372_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */
481 AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
482 AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
483 AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
484 AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */
485 >;
486 };
487
488 uart1_bt_pins_sleep: pinmux_uart1_bt_pins_sleep {
489 pinctrl-single,pins = <
490 AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */
491 AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */
492 AM4372_IOPAD(0x978, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
493 AM4372_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
494 AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */
495 >;
496 };
Felipe Balbi4a457872014-06-23 13:20:59 -0500497};
498
499&i2c0 {
500 status = "okay";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c0_pins>;
Dave Gerlachd279f7a2016-06-15 11:45:28 +0530503 clock-frequency = <100000>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500504
505 tps@24 {
506 compatible = "ti,tps65218";
507 reg = <0x24>;
Peter Ujfalusi21135b62018-05-08 16:20:53 +0300508 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500509 interrupt-controller;
510 #interrupt-cells = <2>;
511
512 dcdc1: regulator-dcdc1 {
Felipe Balbi4a457872014-06-23 13:20:59 -0500513 /* VDD_CORE limits min of OPP50 and max of OPP100 */
514 regulator-name = "vdd_core";
515 regulator-min-microvolt = <912000>;
516 regulator-max-microvolt = <1144000>;
517 regulator-boot-on;
518 regulator-always-on;
519 };
520
521 dcdc2: regulator-dcdc2 {
Felipe Balbi4a457872014-06-23 13:20:59 -0500522 /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
523 regulator-name = "vdd_mpu";
524 regulator-min-microvolt = <912000>;
525 regulator-max-microvolt = <1378000>;
526 regulator-boot-on;
527 regulator-always-on;
528 };
529
530 dcdc3: regulator-dcdc3 {
Felipe Balbi4a457872014-06-23 13:20:59 -0500531 regulator-name = "vdds_ddr";
Felipe Balbi4a457872014-06-23 13:20:59 -0500532 regulator-boot-on;
533 regulator-always-on;
Keerthy1bc5e132016-08-11 10:57:48 +0530534 regulator-state-mem {
535 regulator-on-in-suspend;
536 };
Tero Kristo5a9009f2016-08-11 10:57:50 +0530537 regulator-state-disk {
538 regulator-off-in-suspend;
539 };
Felipe Balbi4a457872014-06-23 13:20:59 -0500540 };
541
542 dcdc4: regulator-dcdc4 {
Felipe Balbi4a457872014-06-23 13:20:59 -0500543 regulator-name = "v3_3d";
544 regulator-min-microvolt = <3300000>;
545 regulator-max-microvolt = <3300000>;
546 regulator-boot-on;
547 regulator-always-on;
548 };
549
Keerthy1bc5e132016-08-11 10:57:48 +0530550 dcdc5: regulator-dcdc5 {
551 compatible = "ti,tps65218-dcdc5";
552 regulator-name = "v1_0bat";
553 regulator-min-microvolt = <1000000>;
554 regulator-max-microvolt = <1000000>;
555 regulator-boot-on;
556 regulator-always-on;
557 regulator-state-mem {
558 regulator-on-in-suspend;
559 };
560 };
561
562 dcdc6: regulator-dcdc6 {
563 compatible = "ti,tps65218-dcdc6";
564 regulator-name = "v1_8bat";
565 regulator-min-microvolt = <1800000>;
566 regulator-max-microvolt = <1800000>;
567 regulator-boot-on;
568 regulator-always-on;
569 regulator-state-mem {
570 regulator-on-in-suspend;
571 };
572 };
573
Felipe Balbi4a457872014-06-23 13:20:59 -0500574 ldo1: regulator-ldo1 {
Felipe Balbi4a457872014-06-23 13:20:59 -0500575 regulator-name = "v1_8d";
576 regulator-min-microvolt = <1800000>;
577 regulator-max-microvolt = <1800000>;
578 regulator-boot-on;
579 regulator-always-on;
580 };
581
Felipe Balbibb1c5fe2014-12-26 13:28:23 -0600582 power-button {
583 compatible = "ti,tps65218-pwrbutton";
584 status = "okay";
585 interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
586 };
Felipe Balbi4a457872014-06-23 13:20:59 -0500587 };
588
589 at24@50 {
Javier Martinez Canillas05e7d622017-05-23 15:34:31 +0200590 compatible = "atmel,24c256";
Felipe Balbi4a457872014-06-23 13:20:59 -0500591 pagesize = <64>;
592 reg = <0x50>;
593 };
594};
595
596&i2c1 {
597 status = "okay";
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c1_pins>;
600 clock-frequency = <400000>;
601
Benoit Parrotf8404f12019-12-11 08:07:19 -0600602 ov2659@30 {
603 compatible = "ovti,ov2659";
604 reg = <0x30>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&clkout1_pin>;
607
608 clocks = <&clkout1_mux_ck>;
609 clock-names = "xvclk";
610 assigned-clocks = <&clkout1_mux_ck>;
611 assigned-clock-parents = <&clkout1_osc_div_ck>;
612
613 port {
614 ov2659_1: endpoint {
615 remote-endpoint = <&vpfe0_ep>;
616 link-frequencies = /bits/ 64 <70000000>;
617 };
618 };
619 };
620
Felipe Balbi4a457872014-06-23 13:20:59 -0500621 edt-ft5306@38 {
622 status = "okay";
623 compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
624 pinctrl-names = "default";
625 pinctrl-0 = <&edt_ft5306_ts_pins>;
626
627 reg = <0x38>;
628 interrupt-parent = <&gpio0>;
Dmitry Torokhov09bb4312015-09-12 10:22:55 -0700629 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500630
Felipe Balbifaa4ec12015-04-09 10:59:26 -0500631 reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500632
633 touchscreen-size-x = <480>;
634 touchscreen-size-y = <272>;
Daniel Mack49a6ec52018-06-17 13:53:09 +0200635
636 wakeup-source;
Felipe Balbi4a457872014-06-23 13:20:59 -0500637 };
638
639 tlv320aic3106: tlv320aic3106@1b {
Peter Ujfalusi20746c52015-07-02 17:06:18 +0300640 #sound-dai-cells = <0>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500641 compatible = "ti,tlv320aic3106";
642 reg = <0x1b>;
643 status = "okay";
644
645 /* Regulators */
646 AVDD-supply = <&dcdc4>;
647 IOVDD-supply = <&dcdc4>;
648 DRVDD-supply = <&dcdc4>;
649 DVDD-supply = <&ldo1>;
650 };
651
652 lis331dlh@18 {
653 compatible = "st,lis331dlh";
654 reg = <0x18>;
655 status = "okay";
656
657 Vdd-supply = <&dcdc4>;
658 Vdd_IO-supply = <&dcdc4>;
659 interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
660 };
661};
662
663&epwmss0 {
664 status = "okay";
665};
666
667&ecap0 {
668 status = "okay";
669 pinctrl-names = "default";
670 pinctrl-0 = <&ecap0_pins>;
671};
672
673&gpio0 {
674 status = "okay";
675};
676
677&gpio1 {
678 status = "okay";
679};
680
Eyal Reizer443ef122018-05-06 10:58:06 +0300681&gpio4 {
682 status = "okay";
683};
684
Felipe Balbi4a457872014-06-23 13:20:59 -0500685&gpio5 {
686 status = "okay";
687};
688
689&mmc1 {
690 status = "okay";
691 pinctrl-names = "default";
692 pinctrl-0 = <&mmc1_pins>;
693
694 vmmc-supply = <&dcdc4>;
695 bus-width = <4>;
Mugunthan V N0731cbd2015-10-12 14:37:11 +0530696 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500697};
698
Eyal Reizer443ef122018-05-06 10:58:06 +0300699&uart1 {
700 status = "okay";
701 pinctrl-names = "default", "sleep";
702 pinctrl-0 = <&uart1_bt_pins_default>;
703 pinctrl-1 = <&uart1_bt_pins_sleep>;
704};
705
706&mmc3 {
707 status = "okay";
708 /*
709 * these are on the crossbar and are outlined in the
710 * xbar-event-map element
711 */
712 dmas = <&edma_xbar 30 0 1>,
713 <&edma_xbar 31 0 2>;
714 dma-names = "tx", "rx";
715 vmmc-supply = <&vmmcwl_fixed>;
716 bus-width = <4>;
717 pinctrl-names = "default", "sleep";
718 pinctrl-0 = <&mmc3_pins_default>;
719 pinctrl-1 = <&mmc3_pins_sleep>;
720 cap-power-off-card;
721 keep-power-in-suspend;
722 ti,non-removable;
723
724 #address-cells = <1>;
725 #size-cells = <0>;
726 wlcore: wlcore@2 {
727 compatible = "ti,wl1835";
728 pinctrl-names = "default", "sleep";
729 pinctrl-0 = <&wlan_pins_default>;
730 pinctrl-1 = <&wlan_pins_sleep>;
731 reg = <2>;
732 interrupt-parent = <&gpio4>;
733 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
734 };
735};
736
Felipe Balbi4a457872014-06-23 13:20:59 -0500737&usb2_phy1 {
738 status = "okay";
739};
740
741&usb1 {
Roger Quadros54cab612018-03-16 13:11:43 +0200742 dr_mode = "otg";
Felipe Balbi4a457872014-06-23 13:20:59 -0500743 status = "okay";
Felipe Balbi221fed32014-12-04 11:01:57 -0600744 pinctrl-names = "default";
745 pinctrl-0 = <&usb1_pins>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500746};
747
748&usb2_phy2 {
749 status = "okay";
750};
751
752&usb2 {
753 dr_mode = "host";
754 status = "okay";
Felipe Balbi221fed32014-12-04 11:01:57 -0600755 pinctrl-names = "default";
756 pinctrl-0 = <&usb2_pins>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500757};
758
759&qspi {
760 status = "okay";
761 pinctrl-names = "default";
762 pinctrl-0 = <&qspi_pins>;
763
764 spi-max-frequency = <48000000>;
765 m25p80@0 {
766 compatible = "mx66l51235l";
767 spi-max-frequency = <48000000>;
768 reg = <0>;
769 spi-cpol;
770 spi-cpha;
771 spi-tx-bus-width = <1>;
772 spi-rx-bus-width = <4>;
773 #address-cells = <1>;
774 #size-cells = <1>;
775
776 /* MTD partition table.
777 * The ROM checks the first 512KiB
778 * for a valid file to boot(XIP).
779 */
780 partition@0 {
781 label = "QSPI.U_BOOT";
782 reg = <0x00000000 0x000080000>;
783 };
784 partition@1 {
785 label = "QSPI.U_BOOT.backup";
786 reg = <0x00080000 0x00080000>;
787 };
788 partition@2 {
789 label = "QSPI.U-BOOT-SPL_OS";
790 reg = <0x00100000 0x00010000>;
791 };
792 partition@3 {
793 label = "QSPI.U_BOOT_ENV";
794 reg = <0x00110000 0x00010000>;
795 };
796 partition@4 {
797 label = "QSPI.U-BOOT-ENV.backup";
798 reg = <0x00120000 0x00010000>;
799 };
800 partition@5 {
801 label = "QSPI.KERNEL";
802 reg = <0x00130000 0x0800000>;
803 };
804 partition@6 {
805 label = "QSPI.FILESYSTEM";
806 reg = <0x00930000 0x36D0000>;
807 };
808 };
809};
810
811&mac {
812 pinctrl-names = "default", "sleep";
813 pinctrl-0 = <&cpsw_default>;
814 pinctrl-1 = <&cpsw_sleep>;
815 dual_emac = <1>;
816 status = "okay";
817};
818
819&davinci_mdio {
820 pinctrl-names = "default", "sleep";
821 pinctrl-0 = <&davinci_mdio_default>;
822 pinctrl-1 = <&davinci_mdio_sleep>;
823 status = "okay";
Grygorii Strashko7c0373b2018-09-10 17:57:42 -0500824
825 ethphy0: ethernet-phy@4 {
826 reg = <4>;
827 };
828
829 ethphy1: ethernet-phy@5 {
830 reg = <5>;
831 };
Felipe Balbi4a457872014-06-23 13:20:59 -0500832};
833
834&cpsw_emac0 {
Grygorii Strashko7c0373b2018-09-10 17:57:42 -0500835 phy-handle = <&ethphy0>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500836 phy-mode = "rgmii";
837 dual_emac_res_vlan = <1>;
838};
839
840&cpsw_emac1 {
Grygorii Strashko7c0373b2018-09-10 17:57:42 -0500841 phy-handle = <&ethphy1>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500842 phy-mode = "rgmii";
843 dual_emac_res_vlan = <2>;
844};
845
846&elm {
847 status = "okay";
848};
849
850&mcasp1 {
Peter Ujfalusi20746c52015-07-02 17:06:18 +0300851 #sound-dai-cells = <0>;
Peter Ujfalusi7155ace2015-07-02 17:06:17 +0300852 pinctrl-names = "default", "sleep";
Felipe Balbi4a457872014-06-23 13:20:59 -0500853 pinctrl-0 = <&mcasp1_pins>;
Peter Ujfalusi7155ace2015-07-02 17:06:17 +0300854 pinctrl-1 = <&mcasp1_pins_sleep>;
Felipe Balbi4a457872014-06-23 13:20:59 -0500855
856 status = "okay";
857
858 op-mode = <0>;
859 tdm-slots = <2>;
860 serial-dir = <
861 0 0 1 2
862 >;
863
864 tx-num-evt = <1>;
865 rx-num-evt = <1>;
866};
867
868&dss {
869 status = "okay";
870
871 pinctrl-names = "default";
872 pinctrl-0 = <&dss_pins>;
873
874 port {
875 dpi_out: endpoint@0 {
876 remote-endpoint = <&lcd_in>;
877 data-lines = <24>;
878 };
879 };
880};
881
882&rtc {
Keerthyfff51e72015-08-18 15:11:14 +0530883 clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
884 clock-names = "ext-clk", "int-clk";
Felipe Balbi4a457872014-06-23 13:20:59 -0500885 status = "okay";
886};
887
888&wdt {
889 status = "okay";
890};
Dave Gerlach3e1fe452014-12-04 09:24:39 -0600891
892&cpu {
893 cpu0-supply = <&dcdc2>;
894};
Darren Etheridge5ccaa6e2014-12-18 21:54:13 +0530895
896&vpfe0 {
897 status = "okay";
898 pinctrl-names = "default", "sleep";
899 pinctrl-0 = <&vpfe0_pins_default>;
900 pinctrl-1 = <&vpfe0_pins_sleep>;
901
902 /* Camera port */
903 port {
904 vpfe0_ep: endpoint {
Benoit Parrotf8404f12019-12-11 08:07:19 -0600905 remote-endpoint = <&ov2659_1>;
Darren Etheridge5ccaa6e2014-12-18 21:54:13 +0530906 ti,am437x-vpfe-interface = <0>;
907 bus-width = <8>;
908 hsync-active = <0>;
909 vsync-active = <0>;
910 };
911 };
912};