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Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -03001==============================
Linus Torvalds1da177e2005-04-16 15:20:36 -07002IRQ affinity on IA64 platforms
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -03003==============================
4
507.01.2002, Erich Focht <efocht@ess.nec.de>
Linus Torvalds1da177e2005-04-16 15:20:36 -07006
7
8By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
9controlled. The behavior on IA64 platforms is slightly different from
Mauro Carvalho Chehabe00b0ab2020-05-01 17:37:51 +020010that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems.
Linus Torvalds1da177e2005-04-16 15:20:36 -070011
12Because of the usage of SAPIC mode and physical destination mode the
13IRQ target is one particular CPU and cannot be a mask of several
14CPUs. Only the first non-zero bit is taken into account.
15
16
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030017Usage examples
18==============
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
20The target CPU has to be specified as a hexadecimal CPU mask. The
21first non-zero bit is the selected CPU. This format has been kept for
22compatibility reasons with i386.
23
24Set the delivery mode of interrupt 41 to fixed and route the
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030025interrupts to CPU #3 (logical CPU number) (2^3=0x08)::
26
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 echo "8" >/proc/irq/41/smp_affinity
28
29Set the default route for IRQ number 41 to CPU 6 in lowest priority
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030030delivery mode (redirectable)::
31
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 echo "r 40" >/proc/irq/41/smp_affinity
33
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030034The output of the command::
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036 cat /proc/irq/IRQ#/smp_affinity
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030037
Linus Torvalds1da177e2005-04-16 15:20:36 -070038gives the target CPU mask for the specified interrupt vector. If the CPU
39mask is preceded by the character "r", the interrupt is redirectable
40(i.e. lowest priority mode routing is used), otherwise its route is
41fixed.
42
43
44
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030045Initialization and default behavior
46===================================
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48If the platform features IRQ redirection (info provided by SAL) all
49IO-SAPIC interrupts are initialized with CPU#0 as their default target
50and the routing is the so called "lowest priority mode" (actually
51fixed SAPIC mode with hint). The XTP chipset registers are used as hints
52for the IRQ routing. Currently in Linux XTP registers can have three
53values:
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030054
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 - minimal for an idle task,
56 - normal if any other task runs,
57 - maximal if the CPU is going to be switched off.
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030058
Linus Torvalds1da177e2005-04-16 15:20:36 -070059The IRQ is routed to the CPU with lowest XTP register value, the
60search begins at the default CPU. Therefore most of the interrupts
61will be handled by CPU #0.
62
63If the platform doesn't feature interrupt redirection IOSAPIC fixed
64routing is used. The target CPUs are distributed in a round robin
65manner. IRQs will be routed only to the selected target CPUs. Check
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030066with::
67
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 cat /proc/interrupts
69
70
71
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -030072Comments
73========
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75On large (multi-node) systems it is recommended to route the IRQs to
76the node to which the corresponding device is connected.
77For systems like the NEC AzusA we get IRQ node-affinity for free. This
78is because usually the chipsets on each node redirect the interrupts
79only to their own CPUs (as they cannot see the XTP registers on the
80other nodes).