Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2 | #if !defined(_I915_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) |
| 3 | #define _I915_TRACE_H_ |
| 4 | |
| 5 | #include <linux/stringify.h> |
| 6 | #include <linux/types.h> |
| 7 | #include <linux/tracepoint.h> |
| 8 | |
| 9 | #include <drm/drmP.h> |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 10 | #include "i915_drv.h" |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 11 | #include "intel_drv.h" |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 12 | #include "intel_ringbuffer.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 13 | |
| 14 | #undef TRACE_SYSTEM |
| 15 | #define TRACE_SYSTEM i915 |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 16 | #define TRACE_INCLUDE_FILE i915_trace |
| 17 | |
Ville Syrjälä | c137d66 | 2017-03-02 19:15:06 +0200 | [diff] [blame] | 18 | /* watermark/fifo updates */ |
| 19 | |
Ville Syrjälä | 53a7915 | 2017-03-02 19:15:08 +0200 | [diff] [blame] | 20 | TRACE_EVENT(intel_cpu_fifo_underrun, |
| 21 | TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pipe), |
| 22 | TP_ARGS(dev_priv, pipe), |
| 23 | |
| 24 | TP_STRUCT__entry( |
| 25 | __field(enum pipe, pipe) |
| 26 | __field(u32, frame) |
| 27 | __field(u32, scanline) |
| 28 | ), |
| 29 | |
| 30 | TP_fast_assign( |
| 31 | __entry->pipe = pipe; |
| 32 | __entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe); |
| 33 | __entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe)); |
| 34 | ), |
| 35 | |
| 36 | TP_printk("pipe %c, frame=%u, scanline=%u", |
| 37 | pipe_name(__entry->pipe), |
| 38 | __entry->frame, __entry->scanline) |
| 39 | ); |
| 40 | |
| 41 | TRACE_EVENT(intel_pch_fifo_underrun, |
Ville Syrjälä | 034263a | 2017-09-01 17:31:23 +0300 | [diff] [blame] | 42 | TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pch_transcoder), |
Ville Syrjälä | 53a7915 | 2017-03-02 19:15:08 +0200 | [diff] [blame] | 43 | TP_ARGS(dev_priv, pch_transcoder), |
| 44 | |
| 45 | TP_STRUCT__entry( |
| 46 | __field(enum pipe, pipe) |
| 47 | __field(u32, frame) |
| 48 | __field(u32, scanline) |
| 49 | ), |
| 50 | |
| 51 | TP_fast_assign( |
Ville Syrjälä | 034263a | 2017-09-01 17:31:23 +0300 | [diff] [blame] | 52 | enum pipe pipe = pch_transcoder; |
Ville Syrjälä | 53a7915 | 2017-03-02 19:15:08 +0200 | [diff] [blame] | 53 | __entry->pipe = pipe; |
| 54 | __entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe); |
| 55 | __entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe)); |
| 56 | ), |
| 57 | |
| 58 | TP_printk("pch transcoder %c, frame=%u, scanline=%u", |
| 59 | pipe_name(__entry->pipe), |
| 60 | __entry->frame, __entry->scanline) |
| 61 | ); |
| 62 | |
Ville Syrjälä | 1489bba | 2017-03-02 19:15:07 +0200 | [diff] [blame] | 63 | TRACE_EVENT(intel_memory_cxsr, |
| 64 | TP_PROTO(struct drm_i915_private *dev_priv, bool old, bool new), |
| 65 | TP_ARGS(dev_priv, old, new), |
| 66 | |
| 67 | TP_STRUCT__entry( |
| 68 | __array(u32, frame, 3) |
| 69 | __array(u32, scanline, 3) |
| 70 | __field(bool, old) |
| 71 | __field(bool, new) |
| 72 | ), |
| 73 | |
| 74 | TP_fast_assign( |
| 75 | enum pipe pipe; |
| 76 | for_each_pipe(dev_priv, pipe) { |
| 77 | __entry->frame[pipe] = |
| 78 | dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe); |
| 79 | __entry->scanline[pipe] = |
| 80 | intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe)); |
| 81 | } |
| 82 | __entry->old = old; |
| 83 | __entry->new = new; |
| 84 | ), |
| 85 | |
| 86 | TP_printk("%s->%s, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u", |
| 87 | onoff(__entry->old), onoff(__entry->new), |
| 88 | __entry->frame[PIPE_A], __entry->scanline[PIPE_A], |
| 89 | __entry->frame[PIPE_B], __entry->scanline[PIPE_B], |
| 90 | __entry->frame[PIPE_C], __entry->scanline[PIPE_C]) |
| 91 | ); |
| 92 | |
Ville Syrjälä | e93329a | 2017-04-21 21:14:31 +0300 | [diff] [blame] | 93 | TRACE_EVENT(g4x_wm, |
| 94 | TP_PROTO(struct intel_crtc *crtc, const struct g4x_wm_values *wm), |
| 95 | TP_ARGS(crtc, wm), |
| 96 | |
| 97 | TP_STRUCT__entry( |
| 98 | __field(enum pipe, pipe) |
| 99 | __field(u32, frame) |
| 100 | __field(u32, scanline) |
| 101 | __field(u16, primary) |
| 102 | __field(u16, sprite) |
| 103 | __field(u16, cursor) |
| 104 | __field(u16, sr_plane) |
| 105 | __field(u16, sr_cursor) |
| 106 | __field(u16, sr_fbc) |
| 107 | __field(u16, hpll_plane) |
| 108 | __field(u16, hpll_cursor) |
| 109 | __field(u16, hpll_fbc) |
| 110 | __field(bool, cxsr) |
| 111 | __field(bool, hpll) |
| 112 | __field(bool, fbc) |
| 113 | ), |
| 114 | |
| 115 | TP_fast_assign( |
| 116 | __entry->pipe = crtc->pipe; |
| 117 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, |
| 118 | crtc->pipe); |
| 119 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 120 | __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; |
| 121 | __entry->sprite = wm->pipe[crtc->pipe].plane[PLANE_SPRITE0]; |
| 122 | __entry->cursor = wm->pipe[crtc->pipe].plane[PLANE_CURSOR]; |
| 123 | __entry->sr_plane = wm->sr.plane; |
| 124 | __entry->sr_cursor = wm->sr.cursor; |
| 125 | __entry->sr_fbc = wm->sr.fbc; |
| 126 | __entry->hpll_plane = wm->hpll.plane; |
| 127 | __entry->hpll_cursor = wm->hpll.cursor; |
| 128 | __entry->hpll_fbc = wm->hpll.fbc; |
| 129 | __entry->cxsr = wm->cxsr; |
| 130 | __entry->hpll = wm->hpll_en; |
| 131 | __entry->fbc = wm->fbc_en; |
| 132 | ), |
| 133 | |
| 134 | TP_printk("pipe %c, frame=%u, scanline=%u, wm %d/%d/%d, sr %s/%d/%d/%d, hpll %s/%d/%d/%d, fbc %s", |
| 135 | pipe_name(__entry->pipe), __entry->frame, __entry->scanline, |
| 136 | __entry->primary, __entry->sprite, __entry->cursor, |
| 137 | yesno(__entry->cxsr), __entry->sr_plane, __entry->sr_cursor, __entry->sr_fbc, |
| 138 | yesno(__entry->hpll), __entry->hpll_plane, __entry->hpll_cursor, __entry->hpll_fbc, |
| 139 | yesno(__entry->fbc)) |
| 140 | ); |
| 141 | |
Ville Syrjälä | c137d66 | 2017-03-02 19:15:06 +0200 | [diff] [blame] | 142 | TRACE_EVENT(vlv_wm, |
| 143 | TP_PROTO(struct intel_crtc *crtc, const struct vlv_wm_values *wm), |
| 144 | TP_ARGS(crtc, wm), |
| 145 | |
| 146 | TP_STRUCT__entry( |
| 147 | __field(enum pipe, pipe) |
| 148 | __field(u32, frame) |
| 149 | __field(u32, scanline) |
| 150 | __field(u32, level) |
| 151 | __field(u32, cxsr) |
| 152 | __field(u32, primary) |
| 153 | __field(u32, sprite0) |
| 154 | __field(u32, sprite1) |
| 155 | __field(u32, cursor) |
| 156 | __field(u32, sr_plane) |
| 157 | __field(u32, sr_cursor) |
| 158 | ), |
| 159 | |
| 160 | TP_fast_assign( |
| 161 | __entry->pipe = crtc->pipe; |
| 162 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, |
| 163 | crtc->pipe); |
| 164 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 165 | __entry->level = wm->level; |
| 166 | __entry->cxsr = wm->cxsr; |
| 167 | __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; |
| 168 | __entry->sprite0 = wm->pipe[crtc->pipe].plane[PLANE_SPRITE0]; |
| 169 | __entry->sprite1 = wm->pipe[crtc->pipe].plane[PLANE_SPRITE1]; |
| 170 | __entry->cursor = wm->pipe[crtc->pipe].plane[PLANE_CURSOR]; |
| 171 | __entry->sr_plane = wm->sr.plane; |
| 172 | __entry->sr_cursor = wm->sr.cursor; |
| 173 | ), |
| 174 | |
| 175 | TP_printk("pipe %c, frame=%u, scanline=%u, level=%d, cxsr=%d, wm %d/%d/%d/%d, sr %d/%d", |
| 176 | pipe_name(__entry->pipe), __entry->frame, |
| 177 | __entry->scanline, __entry->level, __entry->cxsr, |
| 178 | __entry->primary, __entry->sprite0, __entry->sprite1, __entry->cursor, |
| 179 | __entry->sr_plane, __entry->sr_cursor) |
| 180 | ); |
| 181 | |
| 182 | TRACE_EVENT(vlv_fifo_size, |
| 183 | TP_PROTO(struct intel_crtc *crtc, u32 sprite0_start, u32 sprite1_start, u32 fifo_size), |
| 184 | TP_ARGS(crtc, sprite0_start, sprite1_start, fifo_size), |
| 185 | |
| 186 | TP_STRUCT__entry( |
| 187 | __field(enum pipe, pipe) |
| 188 | __field(u32, frame) |
| 189 | __field(u32, scanline) |
| 190 | __field(u32, sprite0_start) |
| 191 | __field(u32, sprite1_start) |
| 192 | __field(u32, fifo_size) |
| 193 | ), |
| 194 | |
| 195 | TP_fast_assign( |
| 196 | __entry->pipe = crtc->pipe; |
| 197 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, |
| 198 | crtc->pipe); |
| 199 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 200 | __entry->sprite0_start = sprite0_start; |
| 201 | __entry->sprite1_start = sprite1_start; |
| 202 | __entry->fifo_size = fifo_size; |
| 203 | ), |
| 204 | |
| 205 | TP_printk("pipe %c, frame=%u, scanline=%u, %d/%d/%d", |
| 206 | pipe_name(__entry->pipe), __entry->frame, |
| 207 | __entry->scanline, __entry->sprite0_start, |
| 208 | __entry->sprite1_start, __entry->fifo_size) |
| 209 | ); |
| 210 | |
Ville Syrjälä | 7225953 | 2017-03-02 19:15:05 +0200 | [diff] [blame] | 211 | /* plane updates */ |
| 212 | |
| 213 | TRACE_EVENT(intel_update_plane, |
| 214 | TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc), |
| 215 | TP_ARGS(plane, crtc), |
| 216 | |
| 217 | TP_STRUCT__entry( |
| 218 | __field(enum pipe, pipe) |
| 219 | __field(const char *, name) |
| 220 | __field(u32, frame) |
| 221 | __field(u32, scanline) |
| 222 | __array(int, src, 4) |
| 223 | __array(int, dst, 4) |
| 224 | ), |
| 225 | |
| 226 | TP_fast_assign( |
| 227 | __entry->pipe = crtc->pipe; |
| 228 | __entry->name = plane->name; |
| 229 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, |
| 230 | crtc->pipe); |
| 231 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 232 | memcpy(__entry->src, &plane->state->src, sizeof(__entry->src)); |
| 233 | memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst)); |
| 234 | ), |
| 235 | |
| 236 | TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT, |
| 237 | pipe_name(__entry->pipe), __entry->name, |
| 238 | __entry->frame, __entry->scanline, |
| 239 | DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src), |
| 240 | DRM_RECT_ARG((const struct drm_rect *)__entry->dst)) |
| 241 | ); |
| 242 | |
| 243 | TRACE_EVENT(intel_disable_plane, |
| 244 | TP_PROTO(struct drm_plane *plane, struct intel_crtc *crtc), |
| 245 | TP_ARGS(plane, crtc), |
| 246 | |
| 247 | TP_STRUCT__entry( |
| 248 | __field(enum pipe, pipe) |
| 249 | __field(const char *, name) |
| 250 | __field(u32, frame) |
| 251 | __field(u32, scanline) |
| 252 | ), |
| 253 | |
| 254 | TP_fast_assign( |
| 255 | __entry->pipe = crtc->pipe; |
| 256 | __entry->name = plane->name; |
| 257 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, |
| 258 | crtc->pipe); |
| 259 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 260 | ), |
| 261 | |
| 262 | TP_printk("pipe %c, plane %s, frame=%u, scanline=%u", |
| 263 | pipe_name(__entry->pipe), __entry->name, |
| 264 | __entry->frame, __entry->scanline) |
| 265 | ); |
| 266 | |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 267 | /* pipe updates */ |
| 268 | |
| 269 | TRACE_EVENT(i915_pipe_update_start, |
Jesse Barnes | d637ce3 | 2015-09-17 08:08:32 -0700 | [diff] [blame] | 270 | TP_PROTO(struct intel_crtc *crtc), |
| 271 | TP_ARGS(crtc), |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 272 | |
| 273 | TP_STRUCT__entry( |
| 274 | __field(enum pipe, pipe) |
| 275 | __field(u32, frame) |
| 276 | __field(u32, scanline) |
| 277 | __field(u32, min) |
| 278 | __field(u32, max) |
| 279 | ), |
| 280 | |
| 281 | TP_fast_assign( |
| 282 | __entry->pipe = crtc->pipe; |
| 283 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, |
| 284 | crtc->pipe); |
| 285 | __entry->scanline = intel_get_crtc_scanline(crtc); |
Jesse Barnes | d637ce3 | 2015-09-17 08:08:32 -0700 | [diff] [blame] | 286 | __entry->min = crtc->debug.min_vbl; |
| 287 | __entry->max = crtc->debug.max_vbl; |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 288 | ), |
| 289 | |
| 290 | TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u", |
| 291 | pipe_name(__entry->pipe), __entry->frame, |
| 292 | __entry->scanline, __entry->min, __entry->max) |
| 293 | ); |
| 294 | |
| 295 | TRACE_EVENT(i915_pipe_update_vblank_evaded, |
Jesse Barnes | d637ce3 | 2015-09-17 08:08:32 -0700 | [diff] [blame] | 296 | TP_PROTO(struct intel_crtc *crtc), |
| 297 | TP_ARGS(crtc), |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 298 | |
| 299 | TP_STRUCT__entry( |
| 300 | __field(enum pipe, pipe) |
| 301 | __field(u32, frame) |
| 302 | __field(u32, scanline) |
| 303 | __field(u32, min) |
| 304 | __field(u32, max) |
| 305 | ), |
| 306 | |
| 307 | TP_fast_assign( |
| 308 | __entry->pipe = crtc->pipe; |
Jesse Barnes | d637ce3 | 2015-09-17 08:08:32 -0700 | [diff] [blame] | 309 | __entry->frame = crtc->debug.start_vbl_count; |
| 310 | __entry->scanline = crtc->debug.scanline_start; |
| 311 | __entry->min = crtc->debug.min_vbl; |
| 312 | __entry->max = crtc->debug.max_vbl; |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 313 | ), |
| 314 | |
| 315 | TP_printk("pipe %c, frame=%u, scanline=%u, min=%u, max=%u", |
| 316 | pipe_name(__entry->pipe), __entry->frame, |
| 317 | __entry->scanline, __entry->min, __entry->max) |
| 318 | ); |
| 319 | |
| 320 | TRACE_EVENT(i915_pipe_update_end, |
Jesse Barnes | d637ce3 | 2015-09-17 08:08:32 -0700 | [diff] [blame] | 321 | TP_PROTO(struct intel_crtc *crtc, u32 frame, int scanline_end), |
| 322 | TP_ARGS(crtc, frame, scanline_end), |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 323 | |
| 324 | TP_STRUCT__entry( |
| 325 | __field(enum pipe, pipe) |
| 326 | __field(u32, frame) |
| 327 | __field(u32, scanline) |
| 328 | ), |
| 329 | |
| 330 | TP_fast_assign( |
| 331 | __entry->pipe = crtc->pipe; |
| 332 | __entry->frame = frame; |
Jesse Barnes | d637ce3 | 2015-09-17 08:08:32 -0700 | [diff] [blame] | 333 | __entry->scanline = scanline_end; |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 334 | ), |
| 335 | |
| 336 | TP_printk("pipe %c, frame=%u, scanline=%u", |
| 337 | pipe_name(__entry->pipe), __entry->frame, |
| 338 | __entry->scanline) |
| 339 | ); |
| 340 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 341 | /* object tracking */ |
| 342 | |
| 343 | TRACE_EVENT(i915_gem_object_create, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 344 | TP_PROTO(struct drm_i915_gem_object *obj), |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 345 | TP_ARGS(obj), |
| 346 | |
| 347 | TP_STRUCT__entry( |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 348 | __field(struct drm_i915_gem_object *, obj) |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 349 | __field(u64, size) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 350 | ), |
| 351 | |
| 352 | TP_fast_assign( |
| 353 | __entry->obj = obj; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 354 | __entry->size = obj->base.size; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 355 | ), |
| 356 | |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 357 | TP_printk("obj=%p, size=0x%llx", __entry->obj, __entry->size) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 358 | ); |
| 359 | |
Chris Wilson | 3abafa5 | 2015-10-01 12:18:26 +0100 | [diff] [blame] | 360 | TRACE_EVENT(i915_gem_shrink, |
| 361 | TP_PROTO(struct drm_i915_private *i915, unsigned long target, unsigned flags), |
| 362 | TP_ARGS(i915, target, flags), |
| 363 | |
| 364 | TP_STRUCT__entry( |
| 365 | __field(int, dev) |
| 366 | __field(unsigned long, target) |
| 367 | __field(unsigned, flags) |
| 368 | ), |
| 369 | |
| 370 | TP_fast_assign( |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 371 | __entry->dev = i915->drm.primary->index; |
Chris Wilson | 3abafa5 | 2015-10-01 12:18:26 +0100 | [diff] [blame] | 372 | __entry->target = target; |
| 373 | __entry->flags = flags; |
| 374 | ), |
| 375 | |
| 376 | TP_printk("dev=%d, target=%lu, flags=%x", |
| 377 | __entry->dev, __entry->target, __entry->flags) |
| 378 | ); |
| 379 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 380 | TRACE_EVENT(i915_vma_bind, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 381 | TP_PROTO(struct i915_vma *vma, unsigned flags), |
| 382 | TP_ARGS(vma, flags), |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 383 | |
| 384 | TP_STRUCT__entry( |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 385 | __field(struct drm_i915_gem_object *, obj) |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 386 | __field(struct i915_address_space *, vm) |
Ben Widawsky | 3393871 | 2015-01-22 17:01:23 +0000 | [diff] [blame] | 387 | __field(u64, offset) |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 388 | __field(u64, size) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 389 | __field(unsigned, flags) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 390 | ), |
| 391 | |
| 392 | TP_fast_assign( |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 393 | __entry->obj = vma->obj; |
| 394 | __entry->vm = vma->vm; |
| 395 | __entry->offset = vma->node.start; |
| 396 | __entry->size = vma->node.size; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 397 | __entry->flags = flags; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 398 | ), |
| 399 | |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 400 | TP_printk("obj=%p, offset=0x%016llx size=0x%llx%s vm=%p", |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 401 | __entry->obj, __entry->offset, __entry->size, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 402 | __entry->flags & PIN_MAPPABLE ? ", mappable" : "", |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 403 | __entry->vm) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 404 | ); |
| 405 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 406 | TRACE_EVENT(i915_vma_unbind, |
| 407 | TP_PROTO(struct i915_vma *vma), |
| 408 | TP_ARGS(vma), |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 409 | |
| 410 | TP_STRUCT__entry( |
| 411 | __field(struct drm_i915_gem_object *, obj) |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 412 | __field(struct i915_address_space *, vm) |
Ben Widawsky | 3393871 | 2015-01-22 17:01:23 +0000 | [diff] [blame] | 413 | __field(u64, offset) |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 414 | __field(u64, size) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 415 | ), |
| 416 | |
| 417 | TP_fast_assign( |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 418 | __entry->obj = vma->obj; |
| 419 | __entry->vm = vma->vm; |
| 420 | __entry->offset = vma->node.start; |
| 421 | __entry->size = vma->node.size; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 422 | ), |
| 423 | |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 424 | TP_printk("obj=%p, offset=0x%016llx size=0x%llx vm=%p", |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 425 | __entry->obj, __entry->offset, __entry->size, __entry->vm) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 426 | ); |
| 427 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 428 | TRACE_EVENT(i915_gem_object_pwrite, |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 429 | TP_PROTO(struct drm_i915_gem_object *obj, u64 offset, u64 len), |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 430 | TP_ARGS(obj, offset, len), |
| 431 | |
| 432 | TP_STRUCT__entry( |
| 433 | __field(struct drm_i915_gem_object *, obj) |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 434 | __field(u64, offset) |
| 435 | __field(u64, len) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 436 | ), |
| 437 | |
| 438 | TP_fast_assign( |
| 439 | __entry->obj = obj; |
| 440 | __entry->offset = offset; |
| 441 | __entry->len = len; |
| 442 | ), |
| 443 | |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 444 | TP_printk("obj=%p, offset=0x%llx, len=0x%llx", |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 445 | __entry->obj, __entry->offset, __entry->len) |
| 446 | ); |
| 447 | |
| 448 | TRACE_EVENT(i915_gem_object_pread, |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 449 | TP_PROTO(struct drm_i915_gem_object *obj, u64 offset, u64 len), |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 450 | TP_ARGS(obj, offset, len), |
| 451 | |
| 452 | TP_STRUCT__entry( |
| 453 | __field(struct drm_i915_gem_object *, obj) |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 454 | __field(u64, offset) |
| 455 | __field(u64, len) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 456 | ), |
| 457 | |
| 458 | TP_fast_assign( |
| 459 | __entry->obj = obj; |
| 460 | __entry->offset = offset; |
| 461 | __entry->len = len; |
| 462 | ), |
| 463 | |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 464 | TP_printk("obj=%p, offset=0x%llx, len=0x%llx", |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 465 | __entry->obj, __entry->offset, __entry->len) |
| 466 | ); |
| 467 | |
| 468 | TRACE_EVENT(i915_gem_object_fault, |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 469 | TP_PROTO(struct drm_i915_gem_object *obj, u64 index, bool gtt, bool write), |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 470 | TP_ARGS(obj, index, gtt, write), |
| 471 | |
| 472 | TP_STRUCT__entry( |
| 473 | __field(struct drm_i915_gem_object *, obj) |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 474 | __field(u64, index) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 475 | __field(bool, gtt) |
| 476 | __field(bool, write) |
| 477 | ), |
| 478 | |
| 479 | TP_fast_assign( |
| 480 | __entry->obj = obj; |
| 481 | __entry->index = index; |
| 482 | __entry->gtt = gtt; |
| 483 | __entry->write = write; |
| 484 | ), |
| 485 | |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 486 | TP_printk("obj=%p, %s index=%llu %s", |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 487 | __entry->obj, |
| 488 | __entry->gtt ? "GTT" : "CPU", |
| 489 | __entry->index, |
| 490 | __entry->write ? ", writable" : "") |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 491 | ); |
| 492 | |
Li Zefan | 903cf20 | 2010-03-11 16:41:45 +0800 | [diff] [blame] | 493 | DECLARE_EVENT_CLASS(i915_gem_object, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 494 | TP_PROTO(struct drm_i915_gem_object *obj), |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 495 | TP_ARGS(obj), |
| 496 | |
| 497 | TP_STRUCT__entry( |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 498 | __field(struct drm_i915_gem_object *, obj) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 499 | ), |
| 500 | |
| 501 | TP_fast_assign( |
| 502 | __entry->obj = obj; |
| 503 | ), |
| 504 | |
| 505 | TP_printk("obj=%p", __entry->obj) |
| 506 | ); |
| 507 | |
Li Zefan | f41275e | 2010-05-24 16:25:44 +0800 | [diff] [blame] | 508 | DEFINE_EVENT(i915_gem_object, i915_gem_object_clflush, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 509 | TP_PROTO(struct drm_i915_gem_object *obj), |
| 510 | TP_ARGS(obj) |
Li Zefan | 903cf20 | 2010-03-11 16:41:45 +0800 | [diff] [blame] | 511 | ); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 512 | |
Li Zefan | 903cf20 | 2010-03-11 16:41:45 +0800 | [diff] [blame] | 513 | DEFINE_EVENT(i915_gem_object, i915_gem_object_destroy, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 514 | TP_PROTO(struct drm_i915_gem_object *obj), |
Li Zefan | 903cf20 | 2010-03-11 16:41:45 +0800 | [diff] [blame] | 515 | TP_ARGS(obj) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 516 | ); |
| 517 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 518 | TRACE_EVENT(i915_gem_evict, |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 519 | TP_PROTO(struct i915_address_space *vm, u64 size, u64 align, unsigned int flags), |
Chris Wilson | e522ac23 | 2016-08-04 16:32:18 +0100 | [diff] [blame] | 520 | TP_ARGS(vm, size, align, flags), |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 521 | |
| 522 | TP_STRUCT__entry( |
Chris Wilson | 4f49be5 | 2009-09-24 00:23:33 +0100 | [diff] [blame] | 523 | __field(u32, dev) |
Chris Wilson | e522ac23 | 2016-08-04 16:32:18 +0100 | [diff] [blame] | 524 | __field(struct i915_address_space *, vm) |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 525 | __field(u64, size) |
| 526 | __field(u64, align) |
Chris Wilson | e522ac23 | 2016-08-04 16:32:18 +0100 | [diff] [blame] | 527 | __field(unsigned int, flags) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 528 | ), |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 529 | |
| 530 | TP_fast_assign( |
Chris Wilson | c6385c9 | 2016-11-29 12:42:05 +0000 | [diff] [blame] | 531 | __entry->dev = vm->i915->drm.primary->index; |
Chris Wilson | e522ac23 | 2016-08-04 16:32:18 +0100 | [diff] [blame] | 532 | __entry->vm = vm; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 533 | __entry->size = size; |
| 534 | __entry->align = align; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 535 | __entry->flags = flags; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 536 | ), |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 537 | |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 538 | TP_printk("dev=%d, vm=%p, size=0x%llx, align=0x%llx %s", |
Chris Wilson | e522ac23 | 2016-08-04 16:32:18 +0100 | [diff] [blame] | 539 | __entry->dev, __entry->vm, __entry->size, __entry->align, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 540 | __entry->flags & PIN_MAPPABLE ? ", mappable" : "") |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 541 | ); |
| 542 | |
Chris Wilson | 625d988 | 2017-01-11 11:23:11 +0000 | [diff] [blame] | 543 | TRACE_EVENT(i915_gem_evict_node, |
| 544 | TP_PROTO(struct i915_address_space *vm, struct drm_mm_node *node, unsigned int flags), |
| 545 | TP_ARGS(vm, node, flags), |
Chris Wilson | 172ae5b | 2016-12-05 14:29:37 +0000 | [diff] [blame] | 546 | |
| 547 | TP_STRUCT__entry( |
| 548 | __field(u32, dev) |
| 549 | __field(struct i915_address_space *, vm) |
| 550 | __field(u64, start) |
| 551 | __field(u64, size) |
| 552 | __field(unsigned long, color) |
| 553 | __field(unsigned int, flags) |
| 554 | ), |
| 555 | |
| 556 | TP_fast_assign( |
Chris Wilson | 625d988 | 2017-01-11 11:23:11 +0000 | [diff] [blame] | 557 | __entry->dev = vm->i915->drm.primary->index; |
| 558 | __entry->vm = vm; |
| 559 | __entry->start = node->start; |
| 560 | __entry->size = node->size; |
| 561 | __entry->color = node->color; |
Chris Wilson | 172ae5b | 2016-12-05 14:29:37 +0000 | [diff] [blame] | 562 | __entry->flags = flags; |
| 563 | ), |
| 564 | |
Chris Wilson | 6c1fa34 | 2017-10-03 13:50:54 +0100 | [diff] [blame] | 565 | TP_printk("dev=%d, vm=%p, start=0x%llx size=0x%llx, color=0x%lx, flags=%x", |
Chris Wilson | 172ae5b | 2016-12-05 14:29:37 +0000 | [diff] [blame] | 566 | __entry->dev, __entry->vm, |
| 567 | __entry->start, __entry->size, |
| 568 | __entry->color, __entry->flags) |
| 569 | ); |
| 570 | |
Chris Wilson | 65921223 | 2017-10-03 13:50:55 +0100 | [diff] [blame] | 571 | TRACE_EVENT(i915_gem_evict_vm, |
| 572 | TP_PROTO(struct i915_address_space *vm), |
| 573 | TP_ARGS(vm), |
| 574 | |
| 575 | TP_STRUCT__entry( |
| 576 | __field(u32, dev) |
| 577 | __field(struct i915_address_space *, vm) |
| 578 | ), |
| 579 | |
| 580 | TP_fast_assign( |
| 581 | __entry->dev = vm->i915->drm.primary->index; |
| 582 | __entry->vm = vm; |
| 583 | ), |
| 584 | |
| 585 | TP_printk("dev=%d, vm=%p", __entry->dev, __entry->vm) |
| 586 | ); |
| 587 | |
Chris Wilson | b52b89d | 2013-09-25 11:43:28 +0100 | [diff] [blame] | 588 | TRACE_EVENT(i915_gem_ring_sync_to, |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 589 | TP_PROTO(struct i915_request *to, struct i915_request *from), |
Chris Wilson | 8e63717 | 2016-08-02 22:50:26 +0100 | [diff] [blame] | 590 | TP_ARGS(to, from), |
Chris Wilson | b52b89d | 2013-09-25 11:43:28 +0100 | [diff] [blame] | 591 | |
| 592 | TP_STRUCT__entry( |
| 593 | __field(u32, dev) |
| 594 | __field(u32, sync_from) |
| 595 | __field(u32, sync_to) |
| 596 | __field(u32, seqno) |
| 597 | ), |
| 598 | |
| 599 | TP_fast_assign( |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 600 | __entry->dev = from->i915->drm.primary->index; |
Chris Wilson | 8e63717 | 2016-08-02 22:50:26 +0100 | [diff] [blame] | 601 | __entry->sync_from = from->engine->id; |
| 602 | __entry->sync_to = to->engine->id; |
Chris Wilson | 65e4760 | 2016-10-28 13:58:49 +0100 | [diff] [blame] | 603 | __entry->seqno = from->global_seqno; |
Chris Wilson | b52b89d | 2013-09-25 11:43:28 +0100 | [diff] [blame] | 604 | ), |
| 605 | |
| 606 | TP_printk("dev=%u, sync-from=%u, sync-to=%u, seqno=%u", |
| 607 | __entry->dev, |
| 608 | __entry->sync_from, __entry->sync_to, |
| 609 | __entry->seqno) |
| 610 | ); |
| 611 | |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 612 | TRACE_EVENT(i915_request_queue, |
| 613 | TP_PROTO(struct i915_request *rq, u32 flags), |
| 614 | TP_ARGS(rq, flags), |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 615 | |
| 616 | TP_STRUCT__entry( |
| 617 | __field(u32, dev) |
Lionel Landwerlin | 151a99e | 2017-12-18 15:19:59 +0000 | [diff] [blame] | 618 | __field(u32, hw_id) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 619 | __field(u32, ring) |
Tvrtko Ursulin | 1cce892 | 2017-02-21 09:13:44 +0000 | [diff] [blame] | 620 | __field(u32, ctx) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 621 | __field(u32, seqno) |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 622 | __field(u32, flags) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 623 | ), |
| 624 | |
| 625 | TP_fast_assign( |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 626 | __entry->dev = rq->i915->drm.primary->index; |
| 627 | __entry->hw_id = rq->ctx->hw_id; |
| 628 | __entry->ring = rq->engine->id; |
| 629 | __entry->ctx = rq->fence.context; |
| 630 | __entry->seqno = rq->fence.seqno; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 631 | __entry->flags = flags; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 632 | ), |
| 633 | |
Lionel Landwerlin | 151a99e | 2017-12-18 15:19:59 +0000 | [diff] [blame] | 634 | TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, flags=0x%x", |
| 635 | __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx, |
| 636 | __entry->seqno, __entry->flags) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 637 | ); |
| 638 | |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 639 | DECLARE_EVENT_CLASS(i915_request, |
| 640 | TP_PROTO(struct i915_request *rq), |
| 641 | TP_ARGS(rq), |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 642 | |
| 643 | TP_STRUCT__entry( |
Chris Wilson | 4f49be5 | 2009-09-24 00:23:33 +0100 | [diff] [blame] | 644 | __field(u32, dev) |
Lionel Landwerlin | 151a99e | 2017-12-18 15:19:59 +0000 | [diff] [blame] | 645 | __field(u32, hw_id) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 646 | __field(u32, ring) |
Lionel Landwerlin | 3c2d067 | 2017-12-18 15:19:58 +0000 | [diff] [blame] | 647 | __field(u32, ctx) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 648 | __field(u32, seqno) |
Tvrtko Ursulin | e235b53 | 2017-02-21 09:13:43 +0000 | [diff] [blame] | 649 | __field(u32, global) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 650 | ), |
| 651 | |
| 652 | TP_fast_assign( |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 653 | __entry->dev = rq->i915->drm.primary->index; |
| 654 | __entry->hw_id = rq->ctx->hw_id; |
| 655 | __entry->ring = rq->engine->id; |
| 656 | __entry->ctx = rq->fence.context; |
| 657 | __entry->seqno = rq->fence.seqno; |
| 658 | __entry->global = rq->global_seqno; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 659 | ), |
| 660 | |
Lionel Landwerlin | 151a99e | 2017-12-18 15:19:59 +0000 | [diff] [blame] | 661 | TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u", |
| 662 | __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx, |
| 663 | __entry->seqno, __entry->global) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 664 | ); |
| 665 | |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 666 | DEFINE_EVENT(i915_request, i915_request_add, |
| 667 | TP_PROTO(struct i915_request *rq), |
| 668 | TP_ARGS(rq) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 669 | ); |
| 670 | |
Tvrtko Ursulin | 354d036 | 2017-02-21 11:01:42 +0000 | [diff] [blame] | 671 | #if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS) |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 672 | DEFINE_EVENT(i915_request, i915_request_submit, |
| 673 | TP_PROTO(struct i915_request *rq), |
| 674 | TP_ARGS(rq) |
Tvrtko Ursulin | 354d036 | 2017-02-21 11:01:42 +0000 | [diff] [blame] | 675 | ); |
| 676 | |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 677 | DEFINE_EVENT(i915_request, i915_request_execute, |
| 678 | TP_PROTO(struct i915_request *rq), |
| 679 | TP_ARGS(rq) |
Tvrtko Ursulin | 354d036 | 2017-02-21 11:01:42 +0000 | [diff] [blame] | 680 | ); |
Tvrtko Ursulin | d7d9683 | 2017-02-21 11:03:00 +0000 | [diff] [blame] | 681 | |
Tvrtko Ursulin | f2742e4 | 2018-05-04 12:56:43 +0100 | [diff] [blame] | 682 | TRACE_EVENT(i915_request_in, |
| 683 | TP_PROTO(struct i915_request *rq, unsigned int port), |
| 684 | TP_ARGS(rq, port), |
Tvrtko Ursulin | d7d9683 | 2017-02-21 11:03:00 +0000 | [diff] [blame] | 685 | |
Tvrtko Ursulin | f2742e4 | 2018-05-04 12:56:43 +0100 | [diff] [blame] | 686 | TP_STRUCT__entry( |
| 687 | __field(u32, dev) |
| 688 | __field(u32, hw_id) |
| 689 | __field(u32, ring) |
| 690 | __field(u32, ctx) |
| 691 | __field(u32, seqno) |
| 692 | __field(u32, global_seqno) |
| 693 | __field(u32, port) |
| 694 | __field(u32, prio) |
| 695 | ), |
Tvrtko Ursulin | d7d9683 | 2017-02-21 11:03:00 +0000 | [diff] [blame] | 696 | |
Tvrtko Ursulin | f2742e4 | 2018-05-04 12:56:43 +0100 | [diff] [blame] | 697 | TP_fast_assign( |
| 698 | __entry->dev = rq->i915->drm.primary->index; |
| 699 | __entry->hw_id = rq->ctx->hw_id; |
| 700 | __entry->ring = rq->engine->id; |
| 701 | __entry->ctx = rq->fence.context; |
| 702 | __entry->seqno = rq->fence.seqno; |
| 703 | __entry->global_seqno = rq->global_seqno; |
| 704 | __entry->prio = rq->sched.attr.priority; |
| 705 | __entry->port = port; |
| 706 | ), |
Tvrtko Ursulin | d7d9683 | 2017-02-21 11:03:00 +0000 | [diff] [blame] | 707 | |
Tvrtko Ursulin | f2742e4 | 2018-05-04 12:56:43 +0100 | [diff] [blame] | 708 | TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, prio=%u, global=%u, port=%u", |
| 709 | __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx, |
| 710 | __entry->seqno, __entry->prio, __entry->global_seqno, |
| 711 | __entry->port) |
| 712 | ); |
| 713 | |
| 714 | TRACE_EVENT(i915_request_out, |
| 715 | TP_PROTO(struct i915_request *rq), |
| 716 | TP_ARGS(rq), |
| 717 | |
| 718 | TP_STRUCT__entry( |
| 719 | __field(u32, dev) |
| 720 | __field(u32, hw_id) |
| 721 | __field(u32, ring) |
| 722 | __field(u32, ctx) |
| 723 | __field(u32, seqno) |
| 724 | __field(u32, global_seqno) |
| 725 | __field(u32, completed) |
| 726 | ), |
| 727 | |
| 728 | TP_fast_assign( |
| 729 | __entry->dev = rq->i915->drm.primary->index; |
| 730 | __entry->hw_id = rq->ctx->hw_id; |
| 731 | __entry->ring = rq->engine->id; |
| 732 | __entry->ctx = rq->fence.context; |
| 733 | __entry->seqno = rq->fence.seqno; |
| 734 | __entry->global_seqno = rq->global_seqno; |
| 735 | __entry->completed = i915_request_completed(rq); |
| 736 | ), |
| 737 | |
| 738 | TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u, completed?=%u", |
Lionel Landwerlin | 151a99e | 2017-12-18 15:19:59 +0000 | [diff] [blame] | 739 | __entry->dev, __entry->hw_id, __entry->ring, |
| 740 | __entry->ctx, __entry->seqno, |
Tvrtko Ursulin | f2742e4 | 2018-05-04 12:56:43 +0100 | [diff] [blame] | 741 | __entry->global_seqno, __entry->completed) |
Tvrtko Ursulin | d7d9683 | 2017-02-21 11:03:00 +0000 | [diff] [blame] | 742 | ); |
| 743 | |
Tvrtko Ursulin | 354d036 | 2017-02-21 11:01:42 +0000 | [diff] [blame] | 744 | #else |
| 745 | #if !defined(TRACE_HEADER_MULTI_READ) |
| 746 | static inline void |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 747 | trace_i915_request_submit(struct i915_request *rq) |
Tvrtko Ursulin | 354d036 | 2017-02-21 11:01:42 +0000 | [diff] [blame] | 748 | { |
| 749 | } |
| 750 | |
| 751 | static inline void |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 752 | trace_i915_request_execute(struct i915_request *rq) |
Tvrtko Ursulin | 354d036 | 2017-02-21 11:01:42 +0000 | [diff] [blame] | 753 | { |
| 754 | } |
Tvrtko Ursulin | d7d9683 | 2017-02-21 11:03:00 +0000 | [diff] [blame] | 755 | |
| 756 | static inline void |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 757 | trace_i915_request_in(struct i915_request *rq, unsigned int port) |
Tvrtko Ursulin | d7d9683 | 2017-02-21 11:03:00 +0000 | [diff] [blame] | 758 | { |
| 759 | } |
| 760 | |
| 761 | static inline void |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 762 | trace_i915_request_out(struct i915_request *rq) |
Tvrtko Ursulin | d7d9683 | 2017-02-21 11:03:00 +0000 | [diff] [blame] | 763 | { |
| 764 | } |
Tvrtko Ursulin | 354d036 | 2017-02-21 11:01:42 +0000 | [diff] [blame] | 765 | #endif |
| 766 | #endif |
| 767 | |
Tvrtko Ursulin | dffabc8 | 2017-02-21 09:13:48 +0000 | [diff] [blame] | 768 | TRACE_EVENT(intel_engine_notify, |
| 769 | TP_PROTO(struct intel_engine_cs *engine, bool waiters), |
| 770 | TP_ARGS(engine, waiters), |
Chris Wilson | 814e9b5 | 2013-09-23 17:33:19 -0300 | [diff] [blame] | 771 | |
| 772 | TP_STRUCT__entry( |
| 773 | __field(u32, dev) |
| 774 | __field(u32, ring) |
| 775 | __field(u32, seqno) |
Tvrtko Ursulin | dffabc8 | 2017-02-21 09:13:48 +0000 | [diff] [blame] | 776 | __field(bool, waiters) |
Chris Wilson | 814e9b5 | 2013-09-23 17:33:19 -0300 | [diff] [blame] | 777 | ), |
| 778 | |
| 779 | TP_fast_assign( |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 780 | __entry->dev = engine->i915->drm.primary->index; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 781 | __entry->ring = engine->id; |
Chris Wilson | 1b7744e | 2016-07-01 17:23:17 +0100 | [diff] [blame] | 782 | __entry->seqno = intel_engine_get_seqno(engine); |
Tvrtko Ursulin | dffabc8 | 2017-02-21 09:13:48 +0000 | [diff] [blame] | 783 | __entry->waiters = waiters; |
Chris Wilson | 814e9b5 | 2013-09-23 17:33:19 -0300 | [diff] [blame] | 784 | ), |
| 785 | |
Tvrtko Ursulin | dffabc8 | 2017-02-21 09:13:48 +0000 | [diff] [blame] | 786 | TP_printk("dev=%u, ring=%u, seqno=%u, waiters=%u", |
| 787 | __entry->dev, __entry->ring, __entry->seqno, |
| 788 | __entry->waiters) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 789 | ); |
| 790 | |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 791 | DEFINE_EVENT(i915_request, i915_request_retire, |
| 792 | TP_PROTO(struct i915_request *rq), |
| 793 | TP_ARGS(rq) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 794 | ); |
| 795 | |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 796 | TRACE_EVENT(i915_request_wait_begin, |
| 797 | TP_PROTO(struct i915_request *rq, unsigned int flags), |
| 798 | TP_ARGS(rq, flags), |
Ben Widawsky | f3fd376 | 2012-05-24 15:03:09 -0700 | [diff] [blame] | 799 | |
| 800 | TP_STRUCT__entry( |
| 801 | __field(u32, dev) |
Lionel Landwerlin | 151a99e | 2017-12-18 15:19:59 +0000 | [diff] [blame] | 802 | __field(u32, hw_id) |
Ben Widawsky | f3fd376 | 2012-05-24 15:03:09 -0700 | [diff] [blame] | 803 | __field(u32, ring) |
Tvrtko Ursulin | 9369250 | 2017-02-21 11:00:24 +0000 | [diff] [blame] | 804 | __field(u32, ctx) |
Ben Widawsky | f3fd376 | 2012-05-24 15:03:09 -0700 | [diff] [blame] | 805 | __field(u32, seqno) |
Tvrtko Ursulin | 9369250 | 2017-02-21 11:00:24 +0000 | [diff] [blame] | 806 | __field(u32, global) |
| 807 | __field(unsigned int, flags) |
Ben Widawsky | f3fd376 | 2012-05-24 15:03:09 -0700 | [diff] [blame] | 808 | ), |
| 809 | |
| 810 | /* NB: the blocking information is racy since mutex_is_locked |
| 811 | * doesn't check that the current thread holds the lock. The only |
| 812 | * other option would be to pass the boolean information of whether |
| 813 | * or not the class was blocking down through the stack which is |
| 814 | * less desirable. |
| 815 | */ |
| 816 | TP_fast_assign( |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 817 | __entry->dev = rq->i915->drm.primary->index; |
| 818 | __entry->hw_id = rq->ctx->hw_id; |
| 819 | __entry->ring = rq->engine->id; |
| 820 | __entry->ctx = rq->fence.context; |
| 821 | __entry->seqno = rq->fence.seqno; |
| 822 | __entry->global = rq->global_seqno; |
Tvrtko Ursulin | 9369250 | 2017-02-21 11:00:24 +0000 | [diff] [blame] | 823 | __entry->flags = flags; |
Ben Widawsky | f3fd376 | 2012-05-24 15:03:09 -0700 | [diff] [blame] | 824 | ), |
| 825 | |
Lionel Landwerlin | 151a99e | 2017-12-18 15:19:59 +0000 | [diff] [blame] | 826 | TP_printk("dev=%u, hw_id=%u, ring=%u, ctx=%u, seqno=%u, global=%u, blocking=%u, flags=0x%x", |
| 827 | __entry->dev, __entry->hw_id, __entry->ring, __entry->ctx, |
| 828 | __entry->seqno, __entry->global, |
| 829 | !!(__entry->flags & I915_WAIT_LOCKED), __entry->flags) |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 830 | ); |
| 831 | |
Chris Wilson | e61e0f5 | 2018-02-21 09:56:36 +0000 | [diff] [blame] | 832 | DEFINE_EVENT(i915_request, i915_request_wait_end, |
| 833 | TP_PROTO(struct i915_request *rq), |
| 834 | TP_ARGS(rq) |
Li Zefan | 903cf20 | 2010-03-11 16:41:45 +0800 | [diff] [blame] | 835 | ); |
| 836 | |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 837 | TRACE_EVENT_CONDITION(i915_reg_rw, |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 838 | TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace), |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 839 | |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 840 | TP_ARGS(write, reg, val, len, trace), |
| 841 | |
| 842 | TP_CONDITION(trace), |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 843 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 844 | TP_STRUCT__entry( |
| 845 | __field(u64, val) |
| 846 | __field(u32, reg) |
| 847 | __field(u16, write) |
| 848 | __field(u16, len) |
| 849 | ), |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 850 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 851 | TP_fast_assign( |
| 852 | __entry->val = (u64)val; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 853 | __entry->reg = i915_mmio_reg_offset(reg); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 854 | __entry->write = write; |
| 855 | __entry->len = len; |
| 856 | ), |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 857 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 858 | TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)", |
| 859 | __entry->write ? "write" : "read", |
| 860 | __entry->reg, __entry->len, |
| 861 | (u32)(__entry->val & 0xffffffff), |
| 862 | (u32)(__entry->val >> 32)) |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 863 | ); |
| 864 | |
Daniel Vetter | be2cde9 | 2012-08-30 13:26:48 +0200 | [diff] [blame] | 865 | TRACE_EVENT(intel_gpu_freq_change, |
| 866 | TP_PROTO(u32 freq), |
| 867 | TP_ARGS(freq), |
| 868 | |
| 869 | TP_STRUCT__entry( |
| 870 | __field(u32, freq) |
| 871 | ), |
| 872 | |
| 873 | TP_fast_assign( |
| 874 | __entry->freq = freq; |
| 875 | ), |
| 876 | |
| 877 | TP_printk("new_freq=%u", __entry->freq) |
| 878 | ); |
| 879 | |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 880 | /** |
| 881 | * DOC: i915_ppgtt_create and i915_ppgtt_release tracepoints |
| 882 | * |
| 883 | * With full ppgtt enabled each process using drm will allocate at least one |
| 884 | * translation table. With these traces it is possible to keep track of the |
| 885 | * allocation and of the lifetime of the tables; this can be used during |
| 886 | * testing/debug to verify that we are not leaking ppgtts. |
| 887 | * These traces identify the ppgtt through the vm pointer, which is also printed |
| 888 | * by the i915_vma_bind and i915_vma_unbind tracepoints. |
| 889 | */ |
| 890 | DECLARE_EVENT_CLASS(i915_ppgtt, |
| 891 | TP_PROTO(struct i915_address_space *vm), |
| 892 | TP_ARGS(vm), |
| 893 | |
| 894 | TP_STRUCT__entry( |
| 895 | __field(struct i915_address_space *, vm) |
| 896 | __field(u32, dev) |
| 897 | ), |
| 898 | |
| 899 | TP_fast_assign( |
| 900 | __entry->vm = vm; |
Chris Wilson | c6385c9 | 2016-11-29 12:42:05 +0000 | [diff] [blame] | 901 | __entry->dev = vm->i915->drm.primary->index; |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 902 | ), |
| 903 | |
| 904 | TP_printk("dev=%u, vm=%p", __entry->dev, __entry->vm) |
| 905 | ) |
| 906 | |
| 907 | DEFINE_EVENT(i915_ppgtt, i915_ppgtt_create, |
| 908 | TP_PROTO(struct i915_address_space *vm), |
| 909 | TP_ARGS(vm) |
| 910 | ); |
| 911 | |
| 912 | DEFINE_EVENT(i915_ppgtt, i915_ppgtt_release, |
| 913 | TP_PROTO(struct i915_address_space *vm), |
| 914 | TP_ARGS(vm) |
| 915 | ); |
| 916 | |
| 917 | /** |
| 918 | * DOC: i915_context_create and i915_context_free tracepoints |
| 919 | * |
| 920 | * These tracepoints are used to track creation and deletion of contexts. |
| 921 | * If full ppgtt is enabled, they also print the address of the vm assigned to |
| 922 | * the context. |
| 923 | */ |
| 924 | DECLARE_EVENT_CLASS(i915_context, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 925 | TP_PROTO(struct i915_gem_context *ctx), |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 926 | TP_ARGS(ctx), |
| 927 | |
| 928 | TP_STRUCT__entry( |
| 929 | __field(u32, dev) |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 930 | __field(struct i915_gem_context *, ctx) |
Tvrtko Ursulin | 99c181a | 2017-02-21 09:13:50 +0000 | [diff] [blame] | 931 | __field(u32, hw_id) |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 932 | __field(struct i915_address_space *, vm) |
| 933 | ), |
| 934 | |
| 935 | TP_fast_assign( |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 936 | __entry->dev = ctx->i915->drm.primary->index; |
Tvrtko Ursulin | 99c181a | 2017-02-21 09:13:50 +0000 | [diff] [blame] | 937 | __entry->ctx = ctx; |
| 938 | __entry->hw_id = ctx->hw_id; |
| 939 | __entry->vm = ctx->ppgtt ? &ctx->ppgtt->base : NULL; |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 940 | ), |
| 941 | |
Tvrtko Ursulin | 99c181a | 2017-02-21 09:13:50 +0000 | [diff] [blame] | 942 | TP_printk("dev=%u, ctx=%p, ctx_vm=%p, hw_id=%u", |
| 943 | __entry->dev, __entry->ctx, __entry->vm, __entry->hw_id) |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 944 | ) |
| 945 | |
| 946 | DEFINE_EVENT(i915_context, i915_context_create, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 947 | TP_PROTO(struct i915_gem_context *ctx), |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 948 | TP_ARGS(ctx) |
| 949 | ); |
| 950 | |
| 951 | DEFINE_EVENT(i915_context, i915_context_free, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 952 | TP_PROTO(struct i915_gem_context *ctx), |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 953 | TP_ARGS(ctx) |
| 954 | ); |
| 955 | |
| 956 | /** |
| 957 | * DOC: switch_mm tracepoint |
| 958 | * |
| 959 | * This tracepoint allows tracking of the mm switch, which is an important point |
| 960 | * in the lifetime of the vm in the legacy submission path. This tracepoint is |
| 961 | * called only if full ppgtt is enabled. |
| 962 | */ |
| 963 | TRACE_EVENT(switch_mm, |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 964 | TP_PROTO(struct intel_engine_cs *engine, struct i915_gem_context *to), |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 965 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 966 | TP_ARGS(engine, to), |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 967 | |
| 968 | TP_STRUCT__entry( |
| 969 | __field(u32, ring) |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 970 | __field(struct i915_gem_context *, to) |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 971 | __field(struct i915_address_space *, vm) |
| 972 | __field(u32, dev) |
| 973 | ), |
| 974 | |
| 975 | TP_fast_assign( |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 976 | __entry->ring = engine->id; |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 977 | __entry->to = to; |
| 978 | __entry->vm = to->ppgtt? &to->ppgtt->base : NULL; |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 979 | __entry->dev = engine->i915->drm.primary->index; |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 980 | ), |
| 981 | |
| 982 | TP_printk("dev=%u, ring=%u, ctx=%p, ctx_vm=%p", |
| 983 | __entry->dev, __entry->ring, __entry->to, __entry->vm) |
| 984 | ); |
| 985 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 986 | #endif /* _I915_TRACE_H_ */ |
| 987 | |
| 988 | /* This part must be outside protection */ |
| 989 | #undef TRACE_INCLUDE_PATH |
Thierry Reding | 4e6d771 | 2017-09-01 16:49:52 +0200 | [diff] [blame] | 990 | #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915 |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 991 | #include <trace/define_trace.h> |