Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/mm/fault.c |
| 3 | * |
| 4 | * Copyright (C) 1995 Linus Torvalds |
| 5 | * Copyright (C) 1995-2004 Russell King |
| 6 | * Copyright (C) 2012 ARM Ltd. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
Paul Gortmaker | 0edfa83 | 2016-09-19 17:38:55 -0400 | [diff] [blame] | 21 | #include <linux/extable.h> |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 22 | #include <linux/signal.h> |
| 23 | #include <linux/mm.h> |
| 24 | #include <linux/hardirq.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/kprobes.h> |
| 27 | #include <linux/uaccess.h> |
| 28 | #include <linux/page-flags.h> |
Ingo Molnar | 3f07c01 | 2017-02-08 18:51:30 +0100 | [diff] [blame] | 29 | #include <linux/sched/signal.h> |
Ingo Molnar | b17b015 | 2017-02-08 18:51:35 +0100 | [diff] [blame] | 30 | #include <linux/sched/debug.h> |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 31 | #include <linux/highmem.h> |
| 32 | #include <linux/perf_event.h> |
James Morse | 7209c86 | 2016-10-18 11:27:47 +0100 | [diff] [blame] | 33 | #include <linux/preempt.h> |
Jonathan (Zhixiong) Zhang | e7c600f | 2017-06-08 18:25:27 +0100 | [diff] [blame] | 34 | #include <linux/hugetlb.h> |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 35 | |
James Morse | 7209c86 | 2016-10-18 11:27:47 +0100 | [diff] [blame] | 36 | #include <asm/bug.h> |
Catalin Marinas | 3bbf715 | 2017-06-26 14:27:36 +0100 | [diff] [blame] | 37 | #include <asm/cmpxchg.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 38 | #include <asm/cpufeature.h> |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 39 | #include <asm/exception.h> |
| 40 | #include <asm/debug-monitors.h> |
Catalin Marinas | 9141300 | 2014-04-06 23:04:12 +0100 | [diff] [blame] | 41 | #include <asm/esr.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 42 | #include <asm/sysreg.h> |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 43 | #include <asm/system_misc.h> |
| 44 | #include <asm/pgtable.h> |
| 45 | #include <asm/tlbflush.h> |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 46 | #include <asm/traps.h> |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 47 | |
Tyler Baicar | 7edda08 | 2017-06-21 12:17:09 -0600 | [diff] [blame] | 48 | #include <acpi/ghes.h> |
| 49 | |
Victor Kamensky | 09a6adf | 2017-04-03 22:51:01 -0700 | [diff] [blame] | 50 | struct fault_info { |
| 51 | int (*fn)(unsigned long addr, unsigned int esr, |
| 52 | struct pt_regs *regs); |
| 53 | int sig; |
| 54 | int code; |
| 55 | const char *name; |
| 56 | }; |
| 57 | |
| 58 | static const struct fault_info fault_info[]; |
| 59 | |
| 60 | static inline const struct fault_info *esr_to_fault_info(unsigned int esr) |
| 61 | { |
| 62 | return fault_info + (esr & 63); |
| 63 | } |
Catalin Marinas | 3495386b | 2012-10-24 16:34:02 +0100 | [diff] [blame] | 64 | |
Sandeepa Prabhu | 2dd0e8d | 2016-07-08 12:35:48 -0400 | [diff] [blame] | 65 | #ifdef CONFIG_KPROBES |
| 66 | static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) |
| 67 | { |
| 68 | int ret = 0; |
| 69 | |
| 70 | /* kprobe_running() needs smp_processor_id() */ |
| 71 | if (!user_mode(regs)) { |
| 72 | preempt_disable(); |
| 73 | if (kprobe_running() && kprobe_fault_handler(regs, esr)) |
| 74 | ret = 1; |
| 75 | preempt_enable(); |
| 76 | } |
| 77 | |
| 78 | return ret; |
| 79 | } |
| 80 | #else |
| 81 | static inline int notify_page_fault(struct pt_regs *regs, unsigned int esr) |
| 82 | { |
| 83 | return 0; |
| 84 | } |
| 85 | #endif |
| 86 | |
Julien Thierry | 1f9b893 | 2017-08-04 09:31:42 +0100 | [diff] [blame] | 87 | static void data_abort_decode(unsigned int esr) |
| 88 | { |
| 89 | pr_alert("Data abort info:\n"); |
| 90 | |
| 91 | if (esr & ESR_ELx_ISV) { |
| 92 | pr_alert(" Access size = %u byte(s)\n", |
| 93 | 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); |
| 94 | pr_alert(" SSE = %lu, SRT = %lu\n", |
| 95 | (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, |
| 96 | (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); |
| 97 | pr_alert(" SF = %lu, AR = %lu\n", |
| 98 | (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, |
| 99 | (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); |
| 100 | } else { |
Mark Rutland | 0a6de8b | 2017-10-02 12:42:00 +0100 | [diff] [blame] | 101 | pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); |
Julien Thierry | 1f9b893 | 2017-08-04 09:31:42 +0100 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | pr_alert(" CM = %lu, WnR = %lu\n", |
| 105 | (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, |
| 106 | (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); |
| 107 | } |
| 108 | |
Julien Thierry | 1f9b893 | 2017-08-04 09:31:42 +0100 | [diff] [blame] | 109 | static void mem_abort_decode(unsigned int esr) |
| 110 | { |
| 111 | pr_alert("Mem abort info:\n"); |
| 112 | |
Mark Rutland | 42dbf54 | 2017-10-19 11:19:55 +0100 | [diff] [blame] | 113 | pr_alert(" ESR = 0x%08x\n", esr); |
Julien Thierry | 1f9b893 | 2017-08-04 09:31:42 +0100 | [diff] [blame] | 114 | pr_alert(" Exception class = %s, IL = %u bits\n", |
| 115 | esr_get_class_string(esr), |
| 116 | (esr & ESR_ELx_IL) ? 32 : 16); |
| 117 | pr_alert(" SET = %lu, FnV = %lu\n", |
| 118 | (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, |
| 119 | (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); |
| 120 | pr_alert(" EA = %lu, S1PTW = %lu\n", |
| 121 | (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, |
| 122 | (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); |
| 123 | |
| 124 | if (esr_is_data_abort(esr)) |
| 125 | data_abort_decode(esr); |
| 126 | } |
| 127 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 128 | /* |
Kristina Martsenko | 67ce16e | 2017-06-09 16:35:52 +0100 | [diff] [blame] | 129 | * Dump out the page tables associated with 'addr' in the currently active mm. |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 130 | */ |
Kristina Martsenko | 67ce16e | 2017-06-09 16:35:52 +0100 | [diff] [blame] | 131 | void show_pte(unsigned long addr) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 132 | { |
Kristina Martsenko | 67ce16e | 2017-06-09 16:35:52 +0100 | [diff] [blame] | 133 | struct mm_struct *mm; |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 134 | pgd_t *pgdp; |
| 135 | pgd_t pgd; |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 136 | |
Kristina Martsenko | 67ce16e | 2017-06-09 16:35:52 +0100 | [diff] [blame] | 137 | if (addr < TASK_SIZE) { |
| 138 | /* TTBR0 */ |
| 139 | mm = current->active_mm; |
| 140 | if (mm == &init_mm) { |
| 141 | pr_alert("[%016lx] user address but active_mm is swapper\n", |
| 142 | addr); |
| 143 | return; |
| 144 | } |
| 145 | } else if (addr >= VA_START) { |
| 146 | /* TTBR1 */ |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 147 | mm = &init_mm; |
Kristina Martsenko | 67ce16e | 2017-06-09 16:35:52 +0100 | [diff] [blame] | 148 | } else { |
| 149 | pr_alert("[%016lx] address between user and kernel address ranges\n", |
| 150 | addr); |
| 151 | return; |
| 152 | } |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 153 | |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 154 | pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp = %p\n", |
Will Deacon | 1eb34b6 | 2017-05-15 15:23:58 +0100 | [diff] [blame] | 155 | mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, |
| 156 | VA_BITS, mm->pgd); |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 157 | pgdp = pgd_offset(mm, addr); |
| 158 | pgd = READ_ONCE(*pgdp); |
| 159 | pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 160 | |
| 161 | do { |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 162 | pud_t *pudp, pud; |
| 163 | pmd_t *pmdp, pmd; |
| 164 | pte_t *ptep, pte; |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 165 | |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 166 | if (pgd_none(pgd) || pgd_bad(pgd)) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 167 | break; |
| 168 | |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 169 | pudp = pud_offset(pgdp, addr); |
| 170 | pud = READ_ONCE(*pudp); |
| 171 | pr_cont(", pud=%016llx", pud_val(pud)); |
| 172 | if (pud_none(pud) || pud_bad(pud)) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 173 | break; |
| 174 | |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 175 | pmdp = pmd_offset(pudp, addr); |
| 176 | pmd = READ_ONCE(*pmdp); |
| 177 | pr_cont(", pmd=%016llx", pmd_val(pmd)); |
| 178 | if (pmd_none(pmd) || pmd_bad(pmd)) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 179 | break; |
| 180 | |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 181 | ptep = pte_offset_map(pmdp, addr); |
| 182 | pte = READ_ONCE(*ptep); |
| 183 | pr_cont(", pte=%016llx", pte_val(pte)); |
| 184 | pte_unmap(ptep); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 185 | } while(0); |
| 186 | |
Mark Rutland | 6ef4fb3 | 2017-01-03 14:27:26 +0000 | [diff] [blame] | 187 | pr_cont("\n"); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 188 | } |
| 189 | |
Catalin Marinas | 66dbd6e | 2016-04-13 16:01:22 +0100 | [diff] [blame] | 190 | /* |
| 191 | * This function sets the access flags (dirty, accessed), as well as write |
| 192 | * permission, and only to a more permissive setting. |
| 193 | * |
| 194 | * It needs to cope with hardware update of the accessed/dirty state by other |
| 195 | * agents in the system and can safely skip the __sync_icache_dcache() call as, |
| 196 | * like set_pte_at(), the PTE is never changed from no-exec to exec here. |
| 197 | * |
| 198 | * Returns whether or not the PTE actually changed. |
| 199 | */ |
| 200 | int ptep_set_access_flags(struct vm_area_struct *vma, |
| 201 | unsigned long address, pte_t *ptep, |
| 202 | pte_t entry, int dirty) |
| 203 | { |
Catalin Marinas | 3bbf715 | 2017-06-26 14:27:36 +0100 | [diff] [blame] | 204 | pteval_t old_pteval, pteval; |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 205 | pte_t pte = READ_ONCE(*ptep); |
Catalin Marinas | 66dbd6e | 2016-04-13 16:01:22 +0100 | [diff] [blame] | 206 | |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 207 | if (pte_same(pte, entry)) |
Catalin Marinas | 66dbd6e | 2016-04-13 16:01:22 +0100 | [diff] [blame] | 208 | return 0; |
| 209 | |
| 210 | /* only preserve the access flags and write permission */ |
Catalin Marinas | 73e86cb | 2017-07-04 19:04:18 +0100 | [diff] [blame] | 211 | pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; |
Catalin Marinas | 66dbd6e | 2016-04-13 16:01:22 +0100 | [diff] [blame] | 212 | |
| 213 | /* |
| 214 | * Setting the flags must be done atomically to avoid racing with the |
Catalin Marinas | 6d33274 | 2017-07-25 14:53:03 +0100 | [diff] [blame] | 215 | * hardware update of the access/dirty state. The PTE_RDONLY bit must |
| 216 | * be set to the most permissive (lowest value) of *ptep and entry |
| 217 | * (calculated as: a & b == ~(~a | ~b)). |
Catalin Marinas | 66dbd6e | 2016-04-13 16:01:22 +0100 | [diff] [blame] | 218 | */ |
Catalin Marinas | 6d33274 | 2017-07-25 14:53:03 +0100 | [diff] [blame] | 219 | pte_val(entry) ^= PTE_RDONLY; |
Will Deacon | 20a004e | 2018-02-15 11:14:56 +0000 | [diff] [blame] | 220 | pteval = pte_val(pte); |
Catalin Marinas | 3bbf715 | 2017-06-26 14:27:36 +0100 | [diff] [blame] | 221 | do { |
| 222 | old_pteval = pteval; |
| 223 | pteval ^= PTE_RDONLY; |
| 224 | pteval |= pte_val(entry); |
| 225 | pteval ^= PTE_RDONLY; |
| 226 | pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); |
| 227 | } while (pteval != old_pteval); |
Catalin Marinas | 66dbd6e | 2016-04-13 16:01:22 +0100 | [diff] [blame] | 228 | |
| 229 | flush_tlb_fix_spurious_fault(vma, address); |
| 230 | return 1; |
| 231 | } |
Catalin Marinas | 66dbd6e | 2016-04-13 16:01:22 +0100 | [diff] [blame] | 232 | |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 233 | static bool is_el1_instruction_abort(unsigned int esr) |
| 234 | { |
| 235 | return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; |
| 236 | } |
| 237 | |
Mark Rutland | 969e61b | 2018-05-21 14:14:50 +0100 | [diff] [blame] | 238 | static inline bool is_el1_permission_fault(unsigned int esr, |
| 239 | struct pt_regs *regs, |
| 240 | unsigned long addr) |
Stephen Boyd | b824b93 | 2017-04-05 12:18:31 -0700 | [diff] [blame] | 241 | { |
| 242 | unsigned int ec = ESR_ELx_EC(esr); |
| 243 | unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; |
| 244 | |
| 245 | if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) |
| 246 | return false; |
| 247 | |
| 248 | if (fsc_type == ESR_ELx_FSC_PERM) |
| 249 | return true; |
| 250 | |
Robin Murphy | 51369e3 | 2018-02-05 15:34:18 +0000 | [diff] [blame] | 251 | if (addr < TASK_SIZE && system_uses_ttbr0_pan()) |
Stephen Boyd | b824b93 | 2017-04-05 12:18:31 -0700 | [diff] [blame] | 252 | return fsc_type == ESR_ELx_FSC_FAULT && |
| 253 | (regs->pstate & PSR_PAN_BIT); |
| 254 | |
| 255 | return false; |
| 256 | } |
| 257 | |
Mark Rutland | c870f14 | 2018-05-21 14:14:51 +0100 | [diff] [blame^] | 258 | static void die_kernel_fault(const char *msg, unsigned long addr, |
| 259 | unsigned int esr, struct pt_regs *regs) |
| 260 | { |
| 261 | bust_spinlocks(1); |
| 262 | |
| 263 | pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, |
| 264 | addr); |
| 265 | |
| 266 | mem_abort_decode(esr); |
| 267 | |
| 268 | show_pte(addr); |
| 269 | die("Oops", regs, esr); |
| 270 | bust_spinlocks(0); |
| 271 | do_exit(SIGKILL); |
| 272 | } |
| 273 | |
Kristina Martsenko | 67ce16e | 2017-06-09 16:35:52 +0100 | [diff] [blame] | 274 | static void __do_kernel_fault(unsigned long addr, unsigned int esr, |
| 275 | struct pt_regs *regs) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 276 | { |
Stephen Boyd | b824b93 | 2017-04-05 12:18:31 -0700 | [diff] [blame] | 277 | const char *msg; |
| 278 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 279 | /* |
| 280 | * Are we prepared to handle this kernel fault? |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 281 | * We are almost certainly not prepared to handle instruction faults. |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 282 | */ |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 283 | if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 284 | return; |
| 285 | |
Mark Rutland | 969e61b | 2018-05-21 14:14:50 +0100 | [diff] [blame] | 286 | if (is_el1_permission_fault(esr, regs, addr)) { |
Stephen Boyd | b824b93 | 2017-04-05 12:18:31 -0700 | [diff] [blame] | 287 | if (esr & ESR_ELx_WNR) |
| 288 | msg = "write to read-only memory"; |
| 289 | else |
| 290 | msg = "read from unreadable memory"; |
| 291 | } else if (addr < PAGE_SIZE) { |
| 292 | msg = "NULL pointer dereference"; |
| 293 | } else { |
| 294 | msg = "paging request"; |
| 295 | } |
| 296 | |
Mark Rutland | c870f14 | 2018-05-21 14:14:51 +0100 | [diff] [blame^] | 297 | die_kernel_fault(msg, addr, esr, regs); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 298 | } |
| 299 | |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 300 | static void __do_user_fault(struct siginfo *info, unsigned int esr) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 301 | { |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 302 | current->thread.fault_address = (unsigned long)info->si_addr; |
| 303 | current->thread.fault_code = esr; |
| 304 | arm64_force_sig_info(info, esr_to_fault_info(esr)->name, current); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 305 | } |
| 306 | |
Catalin Marinas | 59f67e1 | 2013-09-16 15:18:28 +0100 | [diff] [blame] | 307 | static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 308 | { |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 309 | /* |
| 310 | * If we are in kernel mode at this point, we have no context to |
| 311 | * handle this fault with. |
| 312 | */ |
Victor Kamensky | 09a6adf | 2017-04-03 22:51:01 -0700 | [diff] [blame] | 313 | if (user_mode(regs)) { |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 314 | const struct fault_info *inf = esr_to_fault_info(esr); |
| 315 | struct siginfo si = { |
| 316 | .si_signo = inf->sig, |
| 317 | .si_code = inf->code, |
| 318 | .si_addr = (void __user *)addr, |
| 319 | }; |
| 320 | |
| 321 | __do_user_fault(&si, esr); |
| 322 | } else { |
Kristina Martsenko | 67ce16e | 2017-06-09 16:35:52 +0100 | [diff] [blame] | 323 | __do_kernel_fault(addr, esr, regs); |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 324 | } |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | #define VM_FAULT_BADMAP 0x010000 |
| 328 | #define VM_FAULT_BADACCESS 0x020000 |
| 329 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 330 | static int __do_page_fault(struct mm_struct *mm, unsigned long addr, |
Will Deacon | db6f410 | 2013-07-19 15:37:12 +0100 | [diff] [blame] | 331 | unsigned int mm_flags, unsigned long vm_flags, |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 332 | struct task_struct *tsk) |
| 333 | { |
| 334 | struct vm_area_struct *vma; |
| 335 | int fault; |
| 336 | |
| 337 | vma = find_vma(mm, addr); |
| 338 | fault = VM_FAULT_BADMAP; |
| 339 | if (unlikely(!vma)) |
| 340 | goto out; |
| 341 | if (unlikely(vma->vm_start > addr)) |
| 342 | goto check_stack; |
| 343 | |
| 344 | /* |
| 345 | * Ok, we have a good vm_area for this memory access, so we can handle |
| 346 | * it. |
| 347 | */ |
| 348 | good_area: |
Will Deacon | db6f410 | 2013-07-19 15:37:12 +0100 | [diff] [blame] | 349 | /* |
| 350 | * Check that the permissions on the VMA allow for the fault which |
Catalin Marinas | cab15ce | 2016-08-11 18:44:50 +0100 | [diff] [blame] | 351 | * occurred. |
Will Deacon | db6f410 | 2013-07-19 15:37:12 +0100 | [diff] [blame] | 352 | */ |
| 353 | if (!(vma->vm_flags & vm_flags)) { |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 354 | fault = VM_FAULT_BADACCESS; |
| 355 | goto out; |
| 356 | } |
| 357 | |
Kirill A. Shutemov | dcddffd | 2016-07-26 15:25:18 -0700 | [diff] [blame] | 358 | return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 359 | |
| 360 | check_stack: |
| 361 | if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr)) |
| 362 | goto good_area; |
| 363 | out: |
| 364 | return fault; |
| 365 | } |
| 366 | |
Mark Rutland | 541ec87 | 2016-05-31 12:33:03 +0100 | [diff] [blame] | 367 | static bool is_el0_instruction_abort(unsigned int esr) |
| 368 | { |
| 369 | return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; |
| 370 | } |
| 371 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 372 | static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, |
| 373 | struct pt_regs *regs) |
| 374 | { |
| 375 | struct task_struct *tsk; |
| 376 | struct mm_struct *mm; |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 377 | struct siginfo si; |
| 378 | int fault, major = 0; |
Catalin Marinas | cab15ce | 2016-08-11 18:44:50 +0100 | [diff] [blame] | 379 | unsigned long vm_flags = VM_READ | VM_WRITE; |
Will Deacon | db6f410 | 2013-07-19 15:37:12 +0100 | [diff] [blame] | 380 | unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; |
| 381 | |
Sandeepa Prabhu | 2dd0e8d | 2016-07-08 12:35:48 -0400 | [diff] [blame] | 382 | if (notify_page_fault(regs, esr)) |
| 383 | return 0; |
| 384 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 385 | tsk = current; |
| 386 | mm = tsk->mm; |
| 387 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 388 | /* |
| 389 | * If we're in an interrupt or have no user context, we must not take |
| 390 | * the fault. |
| 391 | */ |
David Hildenbrand | 70ffdb9 | 2015-05-11 17:52:11 +0200 | [diff] [blame] | 392 | if (faulthandler_disabled() || !mm) |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 393 | goto no_context; |
| 394 | |
Johannes Weiner | 759496b | 2013-09-12 15:13:39 -0700 | [diff] [blame] | 395 | if (user_mode(regs)) |
| 396 | mm_flags |= FAULT_FLAG_USER; |
| 397 | |
Mark Rutland | 541ec87 | 2016-05-31 12:33:03 +0100 | [diff] [blame] | 398 | if (is_el0_instruction_abort(esr)) { |
Johannes Weiner | 759496b | 2013-09-12 15:13:39 -0700 | [diff] [blame] | 399 | vm_flags = VM_EXEC; |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 400 | } else if ((esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM)) { |
Johannes Weiner | 759496b | 2013-09-12 15:13:39 -0700 | [diff] [blame] | 401 | vm_flags = VM_WRITE; |
| 402 | mm_flags |= FAULT_FLAG_WRITE; |
| 403 | } |
| 404 | |
Mark Rutland | 969e61b | 2018-05-21 14:14:50 +0100 | [diff] [blame] | 405 | if (addr < TASK_SIZE && is_el1_permission_fault(esr, regs, addr)) { |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 406 | /* regs->orig_addr_limit may be 0 if we entered from EL0 */ |
| 407 | if (regs->orig_addr_limit == KERNEL_DS) |
Mark Rutland | c870f14 | 2018-05-21 14:14:51 +0100 | [diff] [blame^] | 408 | die_kernel_fault("access to user memory with fs=KERNEL_DS", |
| 409 | addr, esr, regs); |
James Morse | 7054419 | 2016-02-05 14:58:50 +0000 | [diff] [blame] | 410 | |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 411 | if (is_el1_instruction_abort(esr)) |
Mark Rutland | c870f14 | 2018-05-21 14:14:51 +0100 | [diff] [blame^] | 412 | die_kernel_fault("execution of user memory", |
| 413 | addr, esr, regs); |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 414 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 415 | if (!search_exception_tables(regs->pc)) |
Mark Rutland | c870f14 | 2018-05-21 14:14:51 +0100 | [diff] [blame^] | 416 | die_kernel_fault("access to user memory outside uaccess routines", |
| 417 | addr, esr, regs); |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 418 | } |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 419 | |
Punit Agrawal | 0e3a902 | 2017-06-08 18:25:28 +0100 | [diff] [blame] | 420 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); |
| 421 | |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 422 | /* |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 423 | * As per x86, we may deadlock here. However, since the kernel only |
| 424 | * validly references user space from well defined areas of the code, |
| 425 | * we can bug out early if this is from code which shouldn't. |
| 426 | */ |
| 427 | if (!down_read_trylock(&mm->mmap_sem)) { |
| 428 | if (!user_mode(regs) && !search_exception_tables(regs->pc)) |
| 429 | goto no_context; |
| 430 | retry: |
| 431 | down_read(&mm->mmap_sem); |
| 432 | } else { |
| 433 | /* |
| 434 | * The above down_read_trylock() might have succeeded in which |
| 435 | * case, we'll have missed the might_sleep() from down_read(). |
| 436 | */ |
| 437 | might_sleep(); |
| 438 | #ifdef CONFIG_DEBUG_VM |
| 439 | if (!user_mode(regs) && !search_exception_tables(regs->pc)) |
| 440 | goto no_context; |
| 441 | #endif |
| 442 | } |
| 443 | |
Will Deacon | db6f410 | 2013-07-19 15:37:12 +0100 | [diff] [blame] | 444 | fault = __do_page_fault(mm, addr, mm_flags, vm_flags, tsk); |
Punit Agrawal | 0e3a902 | 2017-06-08 18:25:28 +0100 | [diff] [blame] | 445 | major |= fault & VM_FAULT_MAJOR; |
| 446 | |
| 447 | if (fault & VM_FAULT_RETRY) { |
| 448 | /* |
| 449 | * If we need to retry but a fatal signal is pending, |
| 450 | * handle the signal first. We do not need to release |
| 451 | * the mmap_sem because it would already be released |
| 452 | * in __lock_page_or_retry in mm/filemap.c. |
| 453 | */ |
Mark Rutland | 289d07a | 2017-07-11 15:19:22 +0100 | [diff] [blame] | 454 | if (fatal_signal_pending(current)) { |
| 455 | if (!user_mode(regs)) |
| 456 | goto no_context; |
Punit Agrawal | 0e3a902 | 2017-06-08 18:25:28 +0100 | [diff] [blame] | 457 | return 0; |
Mark Rutland | 289d07a | 2017-07-11 15:19:22 +0100 | [diff] [blame] | 458 | } |
Punit Agrawal | 0e3a902 | 2017-06-08 18:25:28 +0100 | [diff] [blame] | 459 | |
| 460 | /* |
| 461 | * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of |
| 462 | * starvation. |
| 463 | */ |
| 464 | if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { |
| 465 | mm_flags &= ~FAULT_FLAG_ALLOW_RETRY; |
| 466 | mm_flags |= FAULT_FLAG_TRIED; |
| 467 | goto retry; |
| 468 | } |
| 469 | } |
| 470 | up_read(&mm->mmap_sem); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 471 | |
| 472 | /* |
Punit Agrawal | 0e3a902 | 2017-06-08 18:25:28 +0100 | [diff] [blame] | 473 | * Handle the "normal" (no error) case first. |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 474 | */ |
Punit Agrawal | 0e3a902 | 2017-06-08 18:25:28 +0100 | [diff] [blame] | 475 | if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | |
| 476 | VM_FAULT_BADACCESS)))) { |
| 477 | /* |
| 478 | * Major/minor page fault accounting is only done |
| 479 | * once. If we go through a retry, it is extremely |
| 480 | * likely that the page will be found in page cache at |
| 481 | * that point. |
| 482 | */ |
| 483 | if (major) { |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 484 | tsk->maj_flt++; |
| 485 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, |
| 486 | addr); |
| 487 | } else { |
| 488 | tsk->min_flt++; |
| 489 | perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, |
| 490 | addr); |
| 491 | } |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 492 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 493 | return 0; |
Punit Agrawal | 0e3a902 | 2017-06-08 18:25:28 +0100 | [diff] [blame] | 494 | } |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 495 | |
Johannes Weiner | 8713410 | 2013-09-12 15:13:38 -0700 | [diff] [blame] | 496 | /* |
| 497 | * If we are in kernel mode at this point, we have no context to |
| 498 | * handle this fault with. |
| 499 | */ |
| 500 | if (!user_mode(regs)) |
| 501 | goto no_context; |
| 502 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 503 | if (fault & VM_FAULT_OOM) { |
| 504 | /* |
| 505 | * We ran out of memory, call the OOM killer, and return to |
| 506 | * userspace (which will retry the fault, or kill us if we got |
| 507 | * oom-killed). |
| 508 | */ |
| 509 | pagefault_out_of_memory(); |
| 510 | return 0; |
| 511 | } |
| 512 | |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 513 | clear_siginfo(&si); |
| 514 | si.si_addr = (void __user *)addr; |
| 515 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 516 | if (fault & VM_FAULT_SIGBUS) { |
| 517 | /* |
| 518 | * We had some memory, but were unable to successfully fix up |
| 519 | * this page fault. |
| 520 | */ |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 521 | si.si_signo = SIGBUS; |
| 522 | si.si_code = BUS_ADRERR; |
| 523 | } else if (fault & VM_FAULT_HWPOISON_LARGE) { |
| 524 | unsigned int hindex = VM_FAULT_GET_HINDEX(fault); |
| 525 | |
| 526 | si.si_signo = SIGBUS; |
| 527 | si.si_code = BUS_MCEERR_AR; |
| 528 | si.si_addr_lsb = hstate_index_to_shift(hindex); |
| 529 | } else if (fault & VM_FAULT_HWPOISON) { |
| 530 | si.si_signo = SIGBUS; |
| 531 | si.si_code = BUS_MCEERR_AR; |
| 532 | si.si_addr_lsb = PAGE_SHIFT; |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 533 | } else { |
| 534 | /* |
| 535 | * Something tried to access memory that isn't in our memory |
| 536 | * map. |
| 537 | */ |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 538 | si.si_signo = SIGSEGV; |
| 539 | si.si_code = fault == VM_FAULT_BADACCESS ? |
| 540 | SEGV_ACCERR : SEGV_MAPERR; |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 541 | } |
| 542 | |
Will Deacon | 92ff067 | 2018-02-20 14:53:22 +0000 | [diff] [blame] | 543 | __do_user_fault(&si, esr); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 544 | return 0; |
| 545 | |
| 546 | no_context: |
Kristina Martsenko | 67ce16e | 2017-06-09 16:35:52 +0100 | [diff] [blame] | 547 | __do_kernel_fault(addr, esr, regs); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 548 | return 0; |
| 549 | } |
| 550 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 551 | static int __kprobes do_translation_fault(unsigned long addr, |
| 552 | unsigned int esr, |
| 553 | struct pt_regs *regs) |
| 554 | { |
| 555 | if (addr < TASK_SIZE) |
| 556 | return do_page_fault(addr, esr, regs); |
| 557 | |
| 558 | do_bad_area(addr, esr, regs); |
| 559 | return 0; |
| 560 | } |
| 561 | |
EunTaik Lee | 52d7523 | 2016-02-16 04:44:35 +0000 | [diff] [blame] | 562 | static int do_alignment_fault(unsigned long addr, unsigned int esr, |
| 563 | struct pt_regs *regs) |
| 564 | { |
| 565 | do_bad_area(addr, esr, regs); |
| 566 | return 0; |
| 567 | } |
| 568 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 569 | static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
| 570 | { |
Will Deacon | f67d5c4 | 2017-09-22 11:01:26 +0100 | [diff] [blame] | 571 | return 1; /* "fault" */ |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 572 | } |
| 573 | |
Tyler Baicar | 32015c2 | 2017-06-21 12:17:08 -0600 | [diff] [blame] | 574 | static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) |
| 575 | { |
| 576 | struct siginfo info; |
| 577 | const struct fault_info *inf; |
| 578 | |
| 579 | inf = esr_to_fault_info(esr); |
Tyler Baicar | 32015c2 | 2017-06-21 12:17:08 -0600 | [diff] [blame] | 580 | |
Tyler Baicar | 7edda08 | 2017-06-21 12:17:09 -0600 | [diff] [blame] | 581 | /* |
| 582 | * Synchronous aborts may interrupt code which had interrupts masked. |
| 583 | * Before calling out into the wider kernel tell the interested |
| 584 | * subsystems. |
| 585 | */ |
| 586 | if (IS_ENABLED(CONFIG_ACPI_APEI_SEA)) { |
| 587 | if (interrupts_enabled(regs)) |
| 588 | nmi_enter(); |
| 589 | |
Dongjiu Geng | faa75e1 | 2017-12-13 18:36:47 +0800 | [diff] [blame] | 590 | ghes_notify_sea(); |
Tyler Baicar | 7edda08 | 2017-06-21 12:17:09 -0600 | [diff] [blame] | 591 | |
| 592 | if (interrupts_enabled(regs)) |
| 593 | nmi_exit(); |
| 594 | } |
| 595 | |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 596 | info.si_signo = inf->sig; |
Tyler Baicar | 32015c2 | 2017-06-21 12:17:08 -0600 | [diff] [blame] | 597 | info.si_errno = 0; |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 598 | info.si_code = inf->code; |
Tyler Baicar | 32015c2 | 2017-06-21 12:17:08 -0600 | [diff] [blame] | 599 | if (esr & ESR_ELx_FnV) |
| 600 | info.si_addr = NULL; |
| 601 | else |
| 602 | info.si_addr = (void __user *)addr; |
Will Deacon | 1049c30 | 2018-02-20 14:41:02 +0000 | [diff] [blame] | 603 | arm64_notify_die(inf->name, regs, &info, esr); |
Tyler Baicar | 32015c2 | 2017-06-21 12:17:08 -0600 | [diff] [blame] | 604 | |
Dongjiu Geng | faa75e1 | 2017-12-13 18:36:47 +0800 | [diff] [blame] | 605 | return 0; |
Tyler Baicar | 32015c2 | 2017-06-21 12:17:08 -0600 | [diff] [blame] | 606 | } |
| 607 | |
Victor Kamensky | 09a6adf | 2017-04-03 22:51:01 -0700 | [diff] [blame] | 608 | static const struct fault_info fault_info[] = { |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 609 | { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, |
| 610 | { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, |
| 611 | { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, |
| 612 | { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, |
Will Deacon | 7f73f7a | 2014-11-21 14:22:22 +0000 | [diff] [blame] | 613 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 614 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, |
| 615 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, |
Will Deacon | 760bfb4 | 2017-09-29 12:27:41 +0100 | [diff] [blame] | 616 | { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 617 | { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, |
Steve Capper | 084bd29 | 2013-04-10 13:48:00 +0100 | [diff] [blame] | 618 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, |
| 619 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 620 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 621 | { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, |
Steve Capper | 084bd29 | 2013-04-10 13:48:00 +0100 | [diff] [blame] | 622 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, |
| 623 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 624 | { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 625 | { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, |
| 626 | { do_bad, SIGKILL, SI_KERNEL, "unknown 17" }, |
| 627 | { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, |
| 628 | { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, |
| 629 | { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, |
| 630 | { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, |
| 631 | { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, |
| 632 | { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, |
| 633 | { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented |
| 634 | { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, |
| 635 | { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, |
| 636 | { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, |
| 637 | { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented |
| 638 | { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented |
| 639 | { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented |
| 640 | { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented |
| 641 | { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, |
EunTaik Lee | 52d7523 | 2016-02-16 04:44:35 +0000 | [diff] [blame] | 642 | { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 643 | { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, |
| 644 | { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, |
| 645 | { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, |
| 646 | { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, |
| 647 | { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, |
| 648 | { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, |
| 649 | { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, |
| 650 | { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, |
| 651 | { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, |
| 652 | { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, |
| 653 | { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, |
| 654 | { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, |
| 655 | { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, |
| 656 | { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, |
| 657 | { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, |
| 658 | { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, |
| 659 | { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, |
| 660 | { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, |
| 661 | { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, |
| 662 | { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, |
| 663 | { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, |
| 664 | { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, |
| 665 | { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, |
| 666 | { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, |
| 667 | { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, |
| 668 | { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, |
| 669 | { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, |
| 670 | { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, |
| 671 | { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, |
| 672 | { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 673 | }; |
| 674 | |
Tyler Baicar | 621f48e | 2017-06-21 12:17:14 -0600 | [diff] [blame] | 675 | int handle_guest_sea(phys_addr_t addr, unsigned int esr) |
| 676 | { |
| 677 | int ret = -ENOENT; |
| 678 | |
| 679 | if (IS_ENABLED(CONFIG_ACPI_APEI_SEA)) |
| 680 | ret = ghes_notify_sea(); |
| 681 | |
| 682 | return ret; |
| 683 | } |
| 684 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 685 | asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, |
| 686 | struct pt_regs *regs) |
| 687 | { |
Victor Kamensky | 09a6adf | 2017-04-03 22:51:01 -0700 | [diff] [blame] | 688 | const struct fault_info *inf = esr_to_fault_info(esr); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 689 | struct siginfo info; |
| 690 | |
| 691 | if (!inf->fn(addr, esr, regs)) |
| 692 | return; |
| 693 | |
Will Deacon | 1049c30 | 2018-02-20 14:41:02 +0000 | [diff] [blame] | 694 | if (!user_mode(regs)) { |
| 695 | pr_alert("Unhandled fault at 0x%016lx\n", addr); |
| 696 | mem_abort_decode(esr); |
Will Deacon | 80b6eb0 | 2017-10-31 15:56:11 +0000 | [diff] [blame] | 697 | show_pte(addr); |
Will Deacon | 1049c30 | 2018-02-20 14:41:02 +0000 | [diff] [blame] | 698 | } |
Mark Rutland | 42dbf54 | 2017-10-19 11:19:55 +0100 | [diff] [blame] | 699 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 700 | info.si_signo = inf->sig; |
| 701 | info.si_errno = 0; |
| 702 | info.si_code = inf->code; |
| 703 | info.si_addr = (void __user *)addr; |
Will Deacon | 1049c30 | 2018-02-20 14:41:02 +0000 | [diff] [blame] | 704 | arm64_notify_die(inf->name, regs, &info, esr); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 705 | } |
| 706 | |
Will Deacon | 30d88c0 | 2018-02-02 17:31:40 +0000 | [diff] [blame] | 707 | asmlinkage void __exception do_el0_irq_bp_hardening(void) |
| 708 | { |
| 709 | /* PC has already been checked in entry.S */ |
| 710 | arm64_apply_bp_hardening(); |
| 711 | } |
| 712 | |
Will Deacon | 0f15adb | 2018-01-03 11:17:58 +0000 | [diff] [blame] | 713 | asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, |
| 714 | unsigned int esr, |
| 715 | struct pt_regs *regs) |
| 716 | { |
| 717 | /* |
| 718 | * We've taken an instruction abort from userspace and not yet |
| 719 | * re-enabled IRQs. If the address is a kernel address, apply |
| 720 | * BP hardening prior to enabling IRQs and pre-emption. |
| 721 | */ |
| 722 | if (addr > TASK_SIZE) |
| 723 | arm64_apply_bp_hardening(); |
| 724 | |
| 725 | local_irq_enable(); |
| 726 | do_mem_abort(addr, esr, regs); |
| 727 | } |
| 728 | |
| 729 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 730 | asmlinkage void __exception do_sp_pc_abort(unsigned long addr, |
| 731 | unsigned int esr, |
| 732 | struct pt_regs *regs) |
| 733 | { |
| 734 | struct siginfo info; |
Vladimir Murzin | 9e793ab | 2015-06-19 15:28:16 +0100 | [diff] [blame] | 735 | |
Will Deacon | 5dfc6ed | 2018-02-02 17:31:39 +0000 | [diff] [blame] | 736 | if (user_mode(regs)) { |
| 737 | if (instruction_pointer(regs) > TASK_SIZE) |
| 738 | arm64_apply_bp_hardening(); |
| 739 | local_irq_enable(); |
| 740 | } |
| 741 | |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 742 | info.si_signo = SIGBUS; |
| 743 | info.si_errno = 0; |
| 744 | info.si_code = BUS_ADRALN; |
| 745 | info.si_addr = (void __user *)addr; |
Will Deacon | 1049c30 | 2018-02-20 14:41:02 +0000 | [diff] [blame] | 746 | arm64_notify_die("SP/PC alignment exception", regs, &info, esr); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 747 | } |
| 748 | |
Dave P Martin | 9fb7410 | 2015-07-24 16:37:48 +0100 | [diff] [blame] | 749 | int __init early_brk64(unsigned long addr, unsigned int esr, |
| 750 | struct pt_regs *regs); |
| 751 | |
| 752 | /* |
| 753 | * __refdata because early_brk64 is __init, but the reference to it is |
| 754 | * clobbered at arch_initcall time. |
| 755 | * See traps.c and debug-monitors.c:debug_traps_init(). |
| 756 | */ |
| 757 | static struct fault_info __refdata debug_fault_info[] = { |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 758 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, |
| 759 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, |
| 760 | { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 761 | { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 762 | { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 763 | { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, |
Dave P Martin | 9fb7410 | 2015-07-24 16:37:48 +0100 | [diff] [blame] | 764 | { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, |
Dave Martin | af40ff6 | 2018-03-08 17:41:05 +0000 | [diff] [blame] | 765 | { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 766 | }; |
| 767 | |
| 768 | void __init hook_debug_fault_code(int nr, |
| 769 | int (*fn)(unsigned long, unsigned int, struct pt_regs *), |
| 770 | int sig, int code, const char *name) |
| 771 | { |
| 772 | BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); |
| 773 | |
| 774 | debug_fault_info[nr].fn = fn; |
| 775 | debug_fault_info[nr].sig = sig; |
| 776 | debug_fault_info[nr].code = code; |
| 777 | debug_fault_info[nr].name = name; |
| 778 | } |
| 779 | |
| 780 | asmlinkage int __exception do_debug_exception(unsigned long addr, |
| 781 | unsigned int esr, |
| 782 | struct pt_regs *regs) |
| 783 | { |
| 784 | const struct fault_info *inf = debug_fault_info + DBG_ESR_EVT(esr); |
| 785 | struct siginfo info; |
James Morse | 6afedcd | 2016-04-13 13:40:00 +0100 | [diff] [blame] | 786 | int rv; |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 787 | |
James Morse | 6afedcd | 2016-04-13 13:40:00 +0100 | [diff] [blame] | 788 | /* |
| 789 | * Tell lockdep we disabled irqs in entry.S. Do nothing if they were |
| 790 | * already disabled to preserve the last enabled/disabled addresses. |
| 791 | */ |
| 792 | if (interrupts_enabled(regs)) |
| 793 | trace_hardirqs_off(); |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 794 | |
Will Deacon | 5dfc6ed | 2018-02-02 17:31:39 +0000 | [diff] [blame] | 795 | if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE) |
| 796 | arm64_apply_bp_hardening(); |
| 797 | |
James Morse | 6afedcd | 2016-04-13 13:40:00 +0100 | [diff] [blame] | 798 | if (!inf->fn(addr, esr, regs)) { |
| 799 | rv = 1; |
| 800 | } else { |
James Morse | 6afedcd | 2016-04-13 13:40:00 +0100 | [diff] [blame] | 801 | info.si_signo = inf->sig; |
| 802 | info.si_errno = 0; |
| 803 | info.si_code = inf->code; |
| 804 | info.si_addr = (void __user *)addr; |
Will Deacon | 1049c30 | 2018-02-20 14:41:02 +0000 | [diff] [blame] | 805 | arm64_notify_die(inf->name, regs, &info, esr); |
James Morse | 6afedcd | 2016-04-13 13:40:00 +0100 | [diff] [blame] | 806 | rv = 0; |
| 807 | } |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 808 | |
James Morse | 6afedcd | 2016-04-13 13:40:00 +0100 | [diff] [blame] | 809 | if (interrupts_enabled(regs)) |
| 810 | trace_hardirqs_on(); |
| 811 | |
| 812 | return rv; |
Catalin Marinas | 1d18c47 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 813 | } |
Sandeepa Prabhu | 2dd0e8d | 2016-07-08 12:35:48 -0400 | [diff] [blame] | 814 | NOKPROBE_SYMBOL(do_debug_exception); |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 815 | |
| 816 | #ifdef CONFIG_ARM64_PAN |
Dave Martin | c0cda3b | 2018-03-26 15:12:28 +0100 | [diff] [blame] | 817 | void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 818 | { |
James Morse | 7209c86 | 2016-10-18 11:27:47 +0100 | [diff] [blame] | 819 | /* |
| 820 | * We modify PSTATE. This won't work from irq context as the PSTATE |
| 821 | * is discarded once we return from the exception. |
| 822 | */ |
| 823 | WARN_ON_ONCE(in_interrupt()); |
| 824 | |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 825 | config_sctlr_el1(SCTLR_EL1_SPAN, 0); |
James Morse | 7209c86 | 2016-10-18 11:27:47 +0100 | [diff] [blame] | 826 | asm(SET_PSTATE_PAN(1)); |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 827 | } |
| 828 | #endif /* CONFIG_ARM64_PAN */ |