blob: 00348d1fc606be47bc471b3010d1c148a829cfed [file] [log] [blame]
Sanyog Kale89e59052018-04-26 18:38:08 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-18 Intel Corporation.
3
4/*
5 * stream.c - SoundWire Bus stream operations.
6 */
7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/mod_devicetable.h>
13#include <linux/slab.h>
Sanyog Kalef8101c72018-04-26 18:38:17 +053014#include <linux/soundwire/sdw_registers.h>
Sanyog Kale89e59052018-04-26 18:38:08 +053015#include <linux/soundwire/sdw.h>
16#include "bus.h"
17
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053018/*
19 * Array of supported rows and columns as per MIPI SoundWire Specification 1.1
20 *
21 * The rows are arranged as per the array index value programmed
22 * in register. The index 15 has dummy value 0 in order to fill hole.
23 */
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050024int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053025 96, 100, 120, 128, 150, 160, 250, 0,
26 192, 200, 240, 256, 72, 144, 90, 180};
27
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050028int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053029
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050030int sdw_find_col_index(int col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053031{
32 int i;
33
34 for (i = 0; i < SDW_FRAME_COLS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050035 if (sdw_cols[i] == col)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053036 return i;
37 }
38
39 pr_warn("Requested column not found, selecting lowest column no: 2\n");
40 return 0;
41}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050042EXPORT_SYMBOL(sdw_find_col_index);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053043
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050044int sdw_find_row_index(int row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053045{
46 int i;
47
48 for (i = 0; i < SDW_FRAME_ROWS; i++) {
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050049 if (sdw_rows[i] == row)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +053050 return i;
51 }
52
53 pr_warn("Requested row not found, selecting lowest row no: 48\n");
54 return 0;
55}
Pierre-Louis Bossartfe4b70f2019-08-05 19:55:10 -050056EXPORT_SYMBOL(sdw_find_row_index);
Vinod Koul897fe402019-05-02 16:29:29 +053057
Sanyog Kalef8101c72018-04-26 18:38:17 +053058static int _sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -050059 struct sdw_slave *slave,
60 struct sdw_transport_params *t_params,
61 enum sdw_dpn_type type)
Sanyog Kalef8101c72018-04-26 18:38:17 +053062{
63 u32 addr1, addr2, addr3, addr4;
64 int ret;
65 u16 wbuf;
66
67 if (bus->params.next_bank) {
68 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
69 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
70 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
71 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
72 } else {
73 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
74 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
75 addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
76 addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
77 }
78
79 /* Program DPN_OffsetCtrl2 registers */
80 ret = sdw_write(slave, addr1, t_params->offset2);
81 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050082 dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053083 return ret;
84 }
85
86 /* Program DPN_BlockCtrl3 register */
87 ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
88 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -050089 dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +053090 return ret;
91 }
92
93 /*
94 * Data ports are FULL, SIMPLE and REDUCED. This function handles
Vinod Koul7d3b3cd2019-05-02 16:29:27 +053095 * FULL and REDUCED only and beyond this point only FULL is
Sanyog Kalef8101c72018-04-26 18:38:17 +053096 * handled, so bail out if we are not FULL data port type
97 */
98 if (type != SDW_DPN_FULL)
99 return ret;
100
101 /* Program DPN_SampleCtrl2 register */
102 wbuf = (t_params->sample_interval - 1);
103 wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
104 wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
105
106 ret = sdw_write(slave, addr3, wbuf);
107 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500108 dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530109 return ret;
110 }
111
112 /* Program DPN_HCtrl register */
113 wbuf = t_params->hstart;
114 wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
115 wbuf |= t_params->hstop;
116
117 ret = sdw_write(slave, addr4, wbuf);
118 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500119 dev_err(bus->dev, "DPN_HCtrl register write failed\n");
Sanyog Kalef8101c72018-04-26 18:38:17 +0530120
121 return ret;
122}
123
124static int sdw_program_slave_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500125 struct sdw_slave_runtime *s_rt,
126 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530127{
128 struct sdw_transport_params *t_params = &p_rt->transport_params;
129 struct sdw_port_params *p_params = &p_rt->port_params;
130 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
131 u32 addr1, addr2, addr3, addr4, addr5, addr6;
132 struct sdw_dpn_prop *dpn_prop;
133 int ret;
134 u8 wbuf;
135
136 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500137 s_rt->direction,
138 t_params->port_num);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530139 if (!dpn_prop)
140 return -EINVAL;
141
142 addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
143 addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
144
145 if (bus->params.next_bank) {
146 addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
147 addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
148 addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
149 addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
150
151 } else {
152 addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
153 addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
154 addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
155 addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
156 }
157
158 /* Program DPN_PortCtrl register */
159 wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
160 wbuf |= p_params->flow_mode;
161
162 ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
163 if (ret < 0) {
164 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500165 "DPN_PortCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530166 t_params->port_num);
167 return ret;
168 }
169
170 /* Program DPN_BlockCtrl1 register */
171 ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
172 if (ret < 0) {
173 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500174 "DPN_BlockCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530175 t_params->port_num);
176 return ret;
177 }
178
179 /* Program DPN_SampleCtrl1 register */
180 wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
181 ret = sdw_write(s_rt->slave, addr3, wbuf);
182 if (ret < 0) {
183 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500184 "DPN_SampleCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530185 t_params->port_num);
186 return ret;
187 }
188
189 /* Program DPN_OffsetCtrl1 registers */
190 ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
191 if (ret < 0) {
192 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500193 "DPN_OffsetCtrl1 register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530194 t_params->port_num);
195 return ret;
196 }
197
198 /* Program DPN_BlockCtrl2 register*/
199 if (t_params->blk_grp_ctrl_valid) {
200 ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
201 if (ret < 0) {
202 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500203 "DPN_BlockCtrl2 reg write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530204 t_params->port_num);
205 return ret;
206 }
207 }
208
209 /* program DPN_LaneCtrl register */
210 if (slave_prop->lane_control_support) {
211 ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
212 if (ret < 0) {
213 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500214 "DPN_LaneCtrl register write failed for port %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530215 t_params->port_num);
216 return ret;
217 }
218 }
219
220 if (dpn_prop->type != SDW_DPN_SIMPLE) {
221 ret = _sdw_program_slave_port_params(bus, s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500222 t_params, dpn_prop->type);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530223 if (ret < 0)
224 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500225 "Transport reg write failed for port: %d\n",
Sanyog Kalef8101c72018-04-26 18:38:17 +0530226 t_params->port_num);
227 }
228
229 return ret;
230}
231
232static int sdw_program_master_port_params(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500233 struct sdw_port_runtime *p_rt)
Sanyog Kalef8101c72018-04-26 18:38:17 +0530234{
235 int ret;
236
237 /*
238 * we need to set transport and port parameters for the port.
Vinod Koul7d3b3cd2019-05-02 16:29:27 +0530239 * Transport parameters refers to the sample interval, offsets and
Sanyog Kalef8101c72018-04-26 18:38:17 +0530240 * hstart/stop etc of the data. Port parameters refers to word
241 * length, flow mode etc of the port
242 */
243 ret = bus->port_ops->dpn_set_port_transport_params(bus,
244 &p_rt->transport_params,
245 bus->params.next_bank);
246 if (ret < 0)
247 return ret;
248
249 return bus->port_ops->dpn_set_port_params(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500250 &p_rt->port_params,
251 bus->params.next_bank);
Sanyog Kalef8101c72018-04-26 18:38:17 +0530252}
253
254/**
255 * sdw_program_port_params() - Programs transport parameters of Master(s)
256 * and Slave(s)
257 *
258 * @m_rt: Master stream runtime
259 */
260static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
261{
262 struct sdw_slave_runtime *s_rt = NULL;
263 struct sdw_bus *bus = m_rt->bus;
264 struct sdw_port_runtime *p_rt;
265 int ret = 0;
266
267 /* Program transport & port parameters for Slave(s) */
268 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
269 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
270 ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
271 if (ret < 0)
272 return ret;
273 }
274 }
275
276 /* Program transport & port parameters for Master(s) */
277 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
278 ret = sdw_program_master_port_params(bus, p_rt);
279 if (ret < 0)
280 return ret;
281 }
282
283 return 0;
284}
285
Sanyog Kale89e59052018-04-26 18:38:08 +0530286/**
Sanyog Kale79df15b2018-04-26 18:38:23 +0530287 * sdw_enable_disable_slave_ports: Enable/disable slave data port
288 *
289 * @bus: bus instance
290 * @s_rt: slave runtime
291 * @p_rt: port runtime
292 * @en: enable or disable operation
293 *
294 * This function only sets the enable/disable bits in the relevant bank, the
295 * actual enable/disable is done with a bank switch
296 */
297static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500298 struct sdw_slave_runtime *s_rt,
299 struct sdw_port_runtime *p_rt,
300 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530301{
302 struct sdw_transport_params *t_params = &p_rt->transport_params;
303 u32 addr;
304 int ret;
305
306 if (bus->params.next_bank)
307 addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
308 else
309 addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
310
311 /*
312 * Since bus doesn't support sharing a port across two streams,
313 * it is safe to reset this register
314 */
315 if (en)
316 ret = sdw_update(s_rt->slave, addr, 0xFF, p_rt->ch_mask);
317 else
318 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
319
320 if (ret < 0)
321 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500322 "Slave chn_en reg write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530323 ret, t_params->port_num);
324
325 return ret;
326}
327
328static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500329 struct sdw_port_runtime *p_rt,
330 bool en)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530331{
332 struct sdw_transport_params *t_params = &p_rt->transport_params;
333 struct sdw_bus *bus = m_rt->bus;
334 struct sdw_enable_ch enable_ch;
Pierre-Louis Bossarta25eab22019-04-10 22:17:00 -0500335 int ret;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530336
337 enable_ch.port_num = p_rt->num;
338 enable_ch.ch_mask = p_rt->ch_mask;
339 enable_ch.enable = en;
340
341 /* Perform Master port channel(s) enable/disable */
342 if (bus->port_ops->dpn_port_enable_ch) {
343 ret = bus->port_ops->dpn_port_enable_ch(bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500344 &enable_ch,
345 bus->params.next_bank);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530346 if (ret < 0) {
347 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500348 "Master chn_en write failed:%d port:%d\n",
Sanyog Kale79df15b2018-04-26 18:38:23 +0530349 ret, t_params->port_num);
350 return ret;
351 }
352 } else {
353 dev_err(bus->dev,
354 "dpn_port_enable_ch not supported, %s failed\n",
355 en ? "enable" : "disable");
356 return -EINVAL;
357 }
358
359 return 0;
360}
361
362/**
363 * sdw_enable_disable_ports() - Enable/disable port(s) for Master and
364 * Slave(s)
365 *
366 * @m_rt: Master stream runtime
367 * @en: mode (enable/disable)
368 */
369static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
370{
371 struct sdw_port_runtime *s_port, *m_port;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500372 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530373 int ret = 0;
374
375 /* Enable/Disable Slave port(s) */
376 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
377 list_for_each_entry(s_port, &s_rt->port_list, port_node) {
378 ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500379 s_port, en);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530380 if (ret < 0)
381 return ret;
382 }
383 }
384
385 /* Enable/Disable Master port(s) */
386 list_for_each_entry(m_port, &m_rt->port_list, port_node) {
387 ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
388 if (ret < 0)
389 return ret;
390 }
391
392 return 0;
393}
394
395static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500396 struct sdw_prepare_ch prep_ch,
397 enum sdw_port_prep_ops cmd)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530398{
399 const struct sdw_slave_ops *ops = s_rt->slave->ops;
400 int ret;
401
402 if (ops->port_prep) {
403 ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
404 if (ret < 0) {
405 dev_err(&s_rt->slave->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530406 "Slave Port Prep cmd %d failed: %d\n",
407 cmd, ret);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530408 return ret;
409 }
410 }
411
412 return 0;
413}
414
415static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500416 struct sdw_slave_runtime *s_rt,
417 struct sdw_port_runtime *p_rt,
418 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530419{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500420 struct completion *port_ready;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530421 struct sdw_dpn_prop *dpn_prop;
422 struct sdw_prepare_ch prep_ch;
423 unsigned int time_left;
424 bool intr = false;
425 int ret = 0, val;
426 u32 addr;
427
428 prep_ch.num = p_rt->num;
429 prep_ch.ch_mask = p_rt->ch_mask;
430
431 dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500432 s_rt->direction,
433 prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530434 if (!dpn_prop) {
435 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500436 "Slave Port:%d properties not found\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530437 return -EINVAL;
438 }
439
440 prep_ch.prepare = prep;
441
442 prep_ch.bank = bus->params.next_bank;
443
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500444 if (dpn_prop->imp_def_interrupts || !dpn_prop->simple_ch_prep_sm)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530445 intr = true;
446
447 /*
448 * Enable interrupt before Port prepare.
449 * For Port de-prepare, it is assumed that port
450 * was prepared earlier
451 */
452 if (prep && intr) {
453 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500454 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530455 if (ret < 0)
456 return ret;
457 }
458
459 /* Inform slave about the impending port prepare */
460 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
461
462 /* Prepare Slave port implementing CP_SM */
463 if (!dpn_prop->simple_ch_prep_sm) {
464 addr = SDW_DPN_PREPARECTRL(p_rt->num);
465
466 if (prep)
467 ret = sdw_update(s_rt->slave, addr,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500468 0xFF, p_rt->ch_mask);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530469 else
470 ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
471
472 if (ret < 0) {
473 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500474 "Slave prep_ctrl reg write failed\n");
Sanyog Kale79df15b2018-04-26 18:38:23 +0530475 return ret;
476 }
477
478 /* Wait for completion on port ready */
479 port_ready = &s_rt->slave->port_ready[prep_ch.num];
480 time_left = wait_for_completion_timeout(port_ready,
481 msecs_to_jiffies(dpn_prop->ch_prep_timeout));
482
483 val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
484 val &= p_rt->ch_mask;
485 if (!time_left || val) {
486 dev_err(&s_rt->slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500487 "Chn prep failed for port:%d\n", prep_ch.num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530488 return -ETIMEDOUT;
489 }
490 }
491
492 /* Inform slaves about ports prepared */
493 sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
494
495 /* Disable interrupt after Port de-prepare */
496 if (!prep && intr)
497 ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
Pierre-Louis Bossart8acbbfe2019-05-22 14:47:25 -0500498 dpn_prop->imp_def_interrupts);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530499
500 return ret;
501}
502
503static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500504 struct sdw_port_runtime *p_rt,
505 bool prep)
Sanyog Kale79df15b2018-04-26 18:38:23 +0530506{
507 struct sdw_transport_params *t_params = &p_rt->transport_params;
508 struct sdw_bus *bus = m_rt->bus;
509 const struct sdw_master_port_ops *ops = bus->port_ops;
510 struct sdw_prepare_ch prep_ch;
511 int ret = 0;
512
513 prep_ch.num = p_rt->num;
514 prep_ch.ch_mask = p_rt->ch_mask;
515 prep_ch.prepare = prep; /* Prepare/De-prepare */
516 prep_ch.bank = bus->params.next_bank;
517
518 /* Pre-prepare/Pre-deprepare port(s) */
519 if (ops->dpn_port_prep) {
520 ret = ops->dpn_port_prep(bus, &prep_ch);
521 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500522 dev_err(bus->dev, "Port prepare failed for port:%d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500523 t_params->port_num);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530524 return ret;
525 }
526 }
527
528 return ret;
529}
530
531/**
532 * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
533 * Slave(s)
534 *
535 * @m_rt: Master runtime handle
536 * @prep: Prepare or De-prepare
537 */
538static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
539{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500540 struct sdw_slave_runtime *s_rt;
Sanyog Kale79df15b2018-04-26 18:38:23 +0530541 struct sdw_port_runtime *p_rt;
542 int ret = 0;
543
544 /* Prepare/De-prepare Slave port(s) */
545 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
546 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
547 ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500548 p_rt, prep);
Sanyog Kale79df15b2018-04-26 18:38:23 +0530549 if (ret < 0)
550 return ret;
551 }
552 }
553
554 /* Prepare/De-prepare Master port(s) */
555 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
556 ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
557 if (ret < 0)
558 return ret;
559 }
560
561 return ret;
562}
563
564/**
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530565 * sdw_notify_config() - Notify bus configuration
566 *
567 * @m_rt: Master runtime handle
568 *
569 * This function notifies the Master(s) and Slave(s) of the
570 * new bus configuration.
571 */
572static int sdw_notify_config(struct sdw_master_runtime *m_rt)
573{
574 struct sdw_slave_runtime *s_rt;
575 struct sdw_bus *bus = m_rt->bus;
576 struct sdw_slave *slave;
577 int ret = 0;
578
579 if (bus->ops->set_bus_conf) {
580 ret = bus->ops->set_bus_conf(bus, &bus->params);
581 if (ret < 0)
582 return ret;
583 }
584
585 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
586 slave = s_rt->slave;
587
588 if (slave->ops->bus_config) {
589 ret = slave->ops->bus_config(slave, &bus->params);
Rander Wang60835022020-01-14 17:52:26 -0600590 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500591 dev_err(bus->dev, "Notify Slave: %d failed\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500592 slave->dev_num);
Rander Wang60835022020-01-14 17:52:26 -0600593 return ret;
594 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530595 }
596 }
597
598 return ret;
599}
600
601/**
602 * sdw_program_params() - Program transport and port parameters for Master(s)
603 * and Slave(s)
604 *
605 * @bus: SDW bus instance
Rander Wangbfaa3542020-01-14 17:52:27 -0600606 * @prepare: true if sdw_program_params() is called by _prepare.
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530607 */
Rander Wangbfaa3542020-01-14 17:52:27 -0600608static int sdw_program_params(struct sdw_bus *bus, bool prepare)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530609{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500610 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530611 int ret = 0;
612
613 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
Rander Wangbfaa3542020-01-14 17:52:27 -0600614
615 /*
616 * this loop walks through all master runtimes for a
617 * bus, but the ports can only be configured while
618 * explicitly preparing a stream or handling an
619 * already-prepared stream otherwise.
620 */
621 if (!prepare &&
622 m_rt->stream->state == SDW_STREAM_CONFIGURED)
623 continue;
624
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530625 ret = sdw_program_port_params(m_rt);
626 if (ret < 0) {
627 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500628 "Program transport params failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530629 return ret;
630 }
631
632 ret = sdw_notify_config(m_rt);
633 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +0530634 dev_err(bus->dev,
635 "Notify bus config failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530636 return ret;
637 }
638
639 /* Enable port(s) on alternate bank for all active streams */
640 if (m_rt->stream->state != SDW_STREAM_ENABLED)
641 continue;
642
643 ret = sdw_enable_disable_ports(m_rt, true);
644 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500645 dev_err(bus->dev, "Enable channel failed: %d\n", ret);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530646 return ret;
647 }
648 }
649
650 return ret;
651}
652
Shreyas NCce6e74d2018-07-27 14:44:16 +0530653static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530654{
655 int col_index, row_index;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530656 bool multi_link;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530657 struct sdw_msg *wr_msg;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500658 u8 *wbuf;
659 int ret;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530660 u16 addr;
661
662 wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
663 if (!wr_msg)
664 return -ENOMEM;
665
Shreyas NCce6e74d2018-07-27 14:44:16 +0530666 bus->defer_msg.msg = wr_msg;
667
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530668 wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
669 if (!wbuf) {
670 ret = -ENOMEM;
671 goto error_1;
672 }
673
674 /* Get row and column index to program register */
675 col_index = sdw_find_col_index(bus->params.col);
676 row_index = sdw_find_row_index(bus->params.row);
677 wbuf[0] = col_index | (row_index << 3);
678
679 if (bus->params.next_bank)
680 addr = SDW_SCP_FRAMECTRL_B1;
681 else
682 addr = SDW_SCP_FRAMECTRL_B0;
683
684 sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500685 SDW_MSG_FLAG_WRITE, wbuf);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530686 wr_msg->ssp_sync = true;
687
Shreyas NCce6e74d2018-07-27 14:44:16 +0530688 /*
689 * Set the multi_link flag only when both the hardware supports
690 * and there is a stream handled by multiple masters
691 */
692 multi_link = bus->multi_link && (m_rt_count > 1);
693
694 if (multi_link)
695 ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg);
696 else
697 ret = sdw_transfer(bus, wr_msg);
698
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530699 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500700 dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530701 goto error;
702 }
703
Shreyas NCce6e74d2018-07-27 14:44:16 +0530704 if (!multi_link) {
705 kfree(wr_msg);
706 kfree(wbuf);
707 bus->defer_msg.msg = NULL;
708 bus->params.curr_bank = !bus->params.curr_bank;
709 bus->params.next_bank = !bus->params.next_bank;
710 }
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530711
712 return 0;
713
714error:
715 kfree(wbuf);
716error_1:
717 kfree(wr_msg);
718 return ret;
719}
720
Shreyas NCce6e74d2018-07-27 14:44:16 +0530721/**
722 * sdw_ml_sync_bank_switch: Multilink register bank switch
723 *
724 * @bus: SDW bus instance
725 *
726 * Caller function should free the buffers on error
727 */
728static int sdw_ml_sync_bank_switch(struct sdw_bus *bus)
729{
730 unsigned long time_left;
731
732 if (!bus->multi_link)
733 return 0;
734
735 /* Wait for completion of transfer */
736 time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
737 bus->bank_switch_timeout);
738
739 if (!time_left) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500740 dev_err(bus->dev, "Controller Timed out on bank switch\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530741 return -ETIMEDOUT;
742 }
743
744 bus->params.curr_bank = !bus->params.curr_bank;
745 bus->params.next_bank = !bus->params.next_bank;
746
747 if (bus->defer_msg.msg) {
748 kfree(bus->defer_msg.msg->buf);
749 kfree(bus->defer_msg.msg);
750 }
751
752 return 0;
753}
754
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530755static int do_bank_switch(struct sdw_stream_runtime *stream)
756{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500757 struct sdw_master_runtime *m_rt;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530758 const struct sdw_master_ops *ops;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500759 struct sdw_bus *bus;
Shreyas NCce6e74d2018-07-27 14:44:16 +0530760 bool multi_link = false;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530761 int ret = 0;
762
Vinod Koul48949722018-07-27 14:44:14 +0530763 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
764 bus = m_rt->bus;
765 ops = bus->ops;
766
Shreyas NCce6e74d2018-07-27 14:44:16 +0530767 if (bus->multi_link) {
768 multi_link = true;
769 mutex_lock(&bus->msg_lock);
770 }
771
Vinod Koul48949722018-07-27 14:44:14 +0530772 /* Pre-bank switch */
773 if (ops->pre_bank_switch) {
774 ret = ops->pre_bank_switch(bus);
775 if (ret < 0) {
776 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500777 "Pre bank switch op failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530778 goto msg_unlock;
Vinod Koul48949722018-07-27 14:44:14 +0530779 }
780 }
781
Shreyas NCce6e74d2018-07-27 14:44:16 +0530782 /*
783 * Perform Bank switch operation.
784 * For multi link cases, the actual bank switch is
785 * synchronized across all Masters and happens later as a
786 * part of post_bank_switch ops.
787 */
788 ret = sdw_bank_switch(bus, stream->m_rt_count);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530789 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500790 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530791 goto error;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530792 }
793 }
794
Shreyas NCce6e74d2018-07-27 14:44:16 +0530795 /*
796 * For multi link cases, it is expected that the bank switch is
797 * triggered by the post_bank_switch for the first Master in the list
798 * and for the other Masters the post_bank_switch() should return doing
799 * nothing.
800 */
Vinod Koul48949722018-07-27 14:44:14 +0530801 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
802 bus = m_rt->bus;
803 ops = bus->ops;
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530804
Vinod Koul48949722018-07-27 14:44:14 +0530805 /* Post-bank switch */
806 if (ops->post_bank_switch) {
807 ret = ops->post_bank_switch(bus);
808 if (ret < 0) {
809 dev_err(bus->dev,
Vinod Koul62f0cec2019-05-02 16:29:24 +0530810 "Post bank switch op failed: %d\n",
811 ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530812 goto error;
Vinod Koul48949722018-07-27 14:44:14 +0530813 }
Shreyas NCce6e74d2018-07-27 14:44:16 +0530814 } else if (bus->multi_link && stream->m_rt_count > 1) {
815 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500816 "Post bank switch ops not implemented\n");
Shreyas NCce6e74d2018-07-27 14:44:16 +0530817 goto error;
818 }
819
820 /* Set the bank switch timeout to default, if not set */
821 if (!bus->bank_switch_timeout)
822 bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
823
824 /* Check if bank switch was successful */
825 ret = sdw_ml_sync_bank_switch(bus);
826 if (ret < 0) {
827 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500828 "multi link bank switch failed: %d\n", ret);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530829 goto error;
830 }
831
Srinivas Kandagatla9315d902019-06-06 12:22:22 +0100832 if (bus->multi_link)
833 mutex_unlock(&bus->msg_lock);
Shreyas NCce6e74d2018-07-27 14:44:16 +0530834 }
835
836 return ret;
837
838error:
839 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Shreyas NCce6e74d2018-07-27 14:44:16 +0530840 bus = m_rt->bus;
841
842 kfree(bus->defer_msg.msg->buf);
843 kfree(bus->defer_msg.msg);
844 }
845
846msg_unlock:
847
848 if (multi_link) {
849 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
850 bus = m_rt->bus;
851 if (mutex_is_locked(&bus->msg_lock))
852 mutex_unlock(&bus->msg_lock);
Sanyog Kale99b8a5d2018-04-26 18:38:28 +0530853 }
854 }
855
856 return ret;
857}
858
859/**
Sanyog Kale89e59052018-04-26 18:38:08 +0530860 * sdw_release_stream() - Free the assigned stream runtime
861 *
862 * @stream: SoundWire stream runtime
863 *
864 * sdw_release_stream should be called only once per stream
865 */
866void sdw_release_stream(struct sdw_stream_runtime *stream)
867{
868 kfree(stream);
869}
870EXPORT_SYMBOL(sdw_release_stream);
871
872/**
873 * sdw_alloc_stream() - Allocate and return stream runtime
874 *
875 * @stream_name: SoundWire stream name
876 *
877 * Allocates a SoundWire stream runtime instance.
878 * sdw_alloc_stream should be called only once per stream. Typically
879 * invoked from ALSA/ASoC machine/platform driver.
880 */
Srinivas Kandagatladfcff3f2019-08-13 09:35:47 +0100881struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name)
Sanyog Kale89e59052018-04-26 18:38:08 +0530882{
883 struct sdw_stream_runtime *stream;
884
885 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
886 if (!stream)
887 return NULL;
888
889 stream->name = stream_name;
Sanyog Kale0c4a1042018-07-27 14:44:13 +0530890 INIT_LIST_HEAD(&stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530891 stream->state = SDW_STREAM_ALLOCATED;
Shreyas NC9b5c1322018-07-27 14:44:15 +0530892 stream->m_rt_count = 0;
Sanyog Kale89e59052018-04-26 18:38:08 +0530893
894 return stream;
895}
896EXPORT_SYMBOL(sdw_alloc_stream);
897
Vinod Koul48949722018-07-27 14:44:14 +0530898static struct sdw_master_runtime
899*sdw_find_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500900 struct sdw_stream_runtime *stream)
Vinod Koul48949722018-07-27 14:44:14 +0530901{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500902 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +0530903
904 /* Retrieve Bus handle if already available */
905 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
906 if (m_rt->bus == bus)
907 return m_rt;
908 }
909
910 return NULL;
911}
912
Sanyog Kale89e59052018-04-26 18:38:08 +0530913/**
914 * sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
915 *
916 * @bus: SDW bus instance
917 * @stream_config: Stream configuration
918 * @stream: Stream runtime handle.
919 *
920 * This function is to be called with bus_lock held.
921 */
922static struct sdw_master_runtime
923*sdw_alloc_master_rt(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500924 struct sdw_stream_config *stream_config,
925 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530926{
927 struct sdw_master_runtime *m_rt;
928
Sanyog Kale89e59052018-04-26 18:38:08 +0530929 /*
930 * check if Master is already allocated (as a result of Slave adding
931 * it first), if so skip allocation and go to configure
932 */
Vinod Koul48949722018-07-27 14:44:14 +0530933 m_rt = sdw_find_master_rt(bus, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +0530934 if (m_rt)
935 goto stream_config;
936
937 m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
938 if (!m_rt)
939 return NULL;
940
941 /* Initialization of Master runtime handle */
Sanyog Kalebbe73792018-04-26 18:38:13 +0530942 INIT_LIST_HEAD(&m_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530943 INIT_LIST_HEAD(&m_rt->slave_rt_list);
Vinod Koul48949722018-07-27 14:44:14 +0530944 list_add_tail(&m_rt->stream_node, &stream->master_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530945
946 list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
947
948stream_config:
949 m_rt->ch_count = stream_config->ch_count;
950 m_rt->bus = bus;
951 m_rt->stream = stream;
952 m_rt->direction = stream_config->direction;
953
954 return m_rt;
955}
956
957/**
958 * sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
959 *
960 * @slave: Slave handle
961 * @stream_config: Stream configuration
962 * @stream: Stream runtime handle
963 *
964 * This function is to be called with bus_lock held.
965 */
966static struct sdw_slave_runtime
967*sdw_alloc_slave_rt(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500968 struct sdw_stream_config *stream_config,
969 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +0530970{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -0500971 struct sdw_slave_runtime *s_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +0530972
973 s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
974 if (!s_rt)
975 return NULL;
976
Sanyog Kalebbe73792018-04-26 18:38:13 +0530977 INIT_LIST_HEAD(&s_rt->port_list);
Sanyog Kale89e59052018-04-26 18:38:08 +0530978 s_rt->ch_count = stream_config->ch_count;
979 s_rt->direction = stream_config->direction;
980 s_rt->slave = slave;
981
982 return s_rt;
983}
984
Sanyog Kalebbe73792018-04-26 18:38:13 +0530985static void sdw_master_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500986 struct sdw_master_runtime *m_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530987{
988 struct sdw_port_runtime *p_rt, *_p_rt;
989
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500990 list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) {
Sanyog Kalebbe73792018-04-26 18:38:13 +0530991 list_del(&p_rt->port_node);
992 kfree(p_rt);
993 }
994}
995
996static void sdw_slave_port_release(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -0500997 struct sdw_slave *slave,
998 struct sdw_stream_runtime *stream)
Sanyog Kalebbe73792018-04-26 18:38:13 +0530999{
1000 struct sdw_port_runtime *p_rt, *_p_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301001 struct sdw_master_runtime *m_rt;
Sanyog Kalebbe73792018-04-26 18:38:13 +05301002 struct sdw_slave_runtime *s_rt;
1003
Vinod Koul48949722018-07-27 14:44:14 +05301004 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1005 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301006 if (s_rt->slave != slave)
1007 continue;
1008
1009 list_for_each_entry_safe(p_rt, _p_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001010 &s_rt->port_list, port_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301011 list_del(&p_rt->port_node);
1012 kfree(p_rt);
1013 }
Sanyog Kalebbe73792018-04-26 18:38:13 +05301014 }
1015 }
1016}
1017
Sanyog Kale89e59052018-04-26 18:38:08 +05301018/**
1019 * sdw_release_slave_stream() - Free Slave(s) runtime handle
1020 *
1021 * @slave: Slave handle.
1022 * @stream: Stream runtime handle.
1023 *
1024 * This function is to be called with bus_lock held.
1025 */
1026static void sdw_release_slave_stream(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001027 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301028{
1029 struct sdw_slave_runtime *s_rt, *_s_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301030 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301031
Vinod Koul48949722018-07-27 14:44:14 +05301032 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1033 /* Retrieve Slave runtime handle */
1034 list_for_each_entry_safe(s_rt, _s_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001035 &m_rt->slave_rt_list, m_rt_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301036 if (s_rt->slave == slave) {
1037 list_del(&s_rt->m_rt_node);
1038 kfree(s_rt);
1039 return;
1040 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301041 }
1042 }
1043}
1044
1045/**
1046 * sdw_release_master_stream() - Free Master runtime handle
1047 *
Vinod Koul48949722018-07-27 14:44:14 +05301048 * @m_rt: Master runtime node
Sanyog Kale89e59052018-04-26 18:38:08 +05301049 * @stream: Stream runtime handle.
1050 *
1051 * This function is to be called with bus_lock held
1052 * It frees the Master runtime handle and associated Slave(s) runtime
1053 * handle. If this is called first then sdw_release_slave_stream() will have
1054 * no effect as Slave(s) runtime handle would already be freed up.
1055 */
Vinod Koul48949722018-07-27 14:44:14 +05301056static void sdw_release_master_stream(struct sdw_master_runtime *m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001057 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301058{
Sanyog Kale89e59052018-04-26 18:38:08 +05301059 struct sdw_slave_runtime *s_rt, *_s_rt;
1060
Sanyog Kale8d6ccf52018-07-27 14:44:10 +05301061 list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) {
1062 sdw_slave_port_release(s_rt->slave->bus, s_rt->slave, stream);
1063 sdw_release_slave_stream(s_rt->slave, stream);
1064 }
Sanyog Kale89e59052018-04-26 18:38:08 +05301065
Vinod Koul48949722018-07-27 14:44:14 +05301066 list_del(&m_rt->stream_node);
Sanyog Kale89e59052018-04-26 18:38:08 +05301067 list_del(&m_rt->bus_node);
Vinod Koul48949722018-07-27 14:44:14 +05301068 kfree(m_rt);
Sanyog Kale89e59052018-04-26 18:38:08 +05301069}
1070
1071/**
1072 * sdw_stream_remove_master() - Remove master from sdw_stream
1073 *
1074 * @bus: SDW Bus instance
1075 * @stream: SoundWire stream
1076 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301077 * This removes and frees port_rt and master_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301078 */
1079int sdw_stream_remove_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001080 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301081{
Vinod Koul48949722018-07-27 14:44:14 +05301082 struct sdw_master_runtime *m_rt, *_m_rt;
1083
Sanyog Kale89e59052018-04-26 18:38:08 +05301084 mutex_lock(&bus->bus_lock);
1085
Vinod Koul48949722018-07-27 14:44:14 +05301086 list_for_each_entry_safe(m_rt, _m_rt,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001087 &stream->master_list, stream_node) {
Vinod Koul48949722018-07-27 14:44:14 +05301088 if (m_rt->bus != bus)
1089 continue;
1090
1091 sdw_master_port_release(bus, m_rt);
1092 sdw_release_master_stream(m_rt, stream);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301093 stream->m_rt_count--;
Vinod Koul48949722018-07-27 14:44:14 +05301094 }
1095
1096 if (list_empty(&stream->master_list))
1097 stream->state = SDW_STREAM_RELEASED;
Sanyog Kale89e59052018-04-26 18:38:08 +05301098
1099 mutex_unlock(&bus->bus_lock);
1100
1101 return 0;
1102}
1103EXPORT_SYMBOL(sdw_stream_remove_master);
1104
1105/**
1106 * sdw_stream_remove_slave() - Remove slave from sdw_stream
1107 *
1108 * @slave: SDW Slave instance
1109 * @stream: SoundWire stream
1110 *
Sanyog Kalebbe73792018-04-26 18:38:13 +05301111 * This removes and frees port_rt and slave_rt from a stream
Sanyog Kale89e59052018-04-26 18:38:08 +05301112 */
1113int sdw_stream_remove_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001114 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301115{
1116 mutex_lock(&slave->bus->bus_lock);
1117
Sanyog Kalebbe73792018-04-26 18:38:13 +05301118 sdw_slave_port_release(slave->bus, slave, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301119 sdw_release_slave_stream(slave, stream);
1120
1121 mutex_unlock(&slave->bus->bus_lock);
1122
1123 return 0;
1124}
1125EXPORT_SYMBOL(sdw_stream_remove_slave);
1126
1127/**
1128 * sdw_config_stream() - Configure the allocated stream
1129 *
1130 * @dev: SDW device
1131 * @stream: SoundWire stream
1132 * @stream_config: Stream configuration for audio stream
1133 * @is_slave: is API called from Slave or Master
1134 *
1135 * This function is to be called with bus_lock held.
1136 */
1137static int sdw_config_stream(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001138 struct sdw_stream_runtime *stream,
1139 struct sdw_stream_config *stream_config,
1140 bool is_slave)
Sanyog Kale89e59052018-04-26 18:38:08 +05301141{
1142 /*
1143 * Update the stream rate, channel and bps based on data
1144 * source. For more than one data source (multilink),
1145 * match the rate, bps, stream type and increment number of channels.
1146 *
1147 * If rate/bps is zero, it means the values are not set, so skip
1148 * comparison and allow the value to be set and stored in stream
1149 */
1150 if (stream->params.rate &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001151 stream->params.rate != stream_config->frame_rate) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001152 dev_err(dev, "rate not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301153 return -EINVAL;
1154 }
1155
1156 if (stream->params.bps &&
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001157 stream->params.bps != stream_config->bps) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001158 dev_err(dev, "bps not matching, stream:%s\n", stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301159 return -EINVAL;
1160 }
1161
1162 stream->type = stream_config->type;
1163 stream->params.rate = stream_config->frame_rate;
1164 stream->params.bps = stream_config->bps;
1165
1166 /* TODO: Update this check during Device-device support */
1167 if (is_slave)
1168 stream->params.ch_count += stream_config->ch_count;
1169
1170 return 0;
1171}
1172
Sanyog Kalebbe73792018-04-26 18:38:13 +05301173static int sdw_is_valid_port_range(struct device *dev,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001174 struct sdw_port_runtime *p_rt)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301175{
1176 if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1177 dev_err(dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001178 "SoundWire: Invalid port number :%d\n", p_rt->num);
Sanyog Kalebbe73792018-04-26 18:38:13 +05301179 return -EINVAL;
1180 }
1181
1182 return 0;
1183}
1184
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001185static struct sdw_port_runtime
1186*sdw_port_alloc(struct device *dev,
1187 struct sdw_port_config *port_config,
1188 int port_index)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301189{
1190 struct sdw_port_runtime *p_rt;
1191
1192 p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1193 if (!p_rt)
1194 return NULL;
1195
1196 p_rt->ch_mask = port_config[port_index].ch_mask;
1197 p_rt->num = port_config[port_index].num;
1198
1199 return p_rt;
1200}
1201
1202static int sdw_master_port_config(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001203 struct sdw_master_runtime *m_rt,
1204 struct sdw_port_config *port_config,
1205 unsigned int num_ports)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301206{
1207 struct sdw_port_runtime *p_rt;
1208 int i;
1209
1210 /* Iterate for number of ports to perform initialization */
1211 for (i = 0; i < num_ports; i++) {
1212 p_rt = sdw_port_alloc(bus->dev, port_config, i);
1213 if (!p_rt)
1214 return -ENOMEM;
1215
1216 /*
1217 * TODO: Check port capabilities for requested
1218 * configuration (audio mode support)
1219 */
1220
1221 list_add_tail(&p_rt->port_node, &m_rt->port_list);
1222 }
1223
1224 return 0;
1225}
1226
1227static int sdw_slave_port_config(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001228 struct sdw_slave_runtime *s_rt,
1229 struct sdw_port_config *port_config,
1230 unsigned int num_config)
Sanyog Kalebbe73792018-04-26 18:38:13 +05301231{
1232 struct sdw_port_runtime *p_rt;
1233 int i, ret;
1234
1235 /* Iterate for number of ports to perform initialization */
1236 for (i = 0; i < num_config; i++) {
1237 p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1238 if (!p_rt)
1239 return -ENOMEM;
1240
1241 /*
1242 * TODO: Check valid port range as defined by DisCo/
1243 * slave
1244 */
1245 ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1246 if (ret < 0) {
1247 kfree(p_rt);
1248 return ret;
1249 }
1250
1251 /*
1252 * TODO: Check port capabilities for requested
1253 * configuration (audio mode support)
1254 */
1255
1256 list_add_tail(&p_rt->port_node, &s_rt->port_list);
1257 }
1258
1259 return 0;
1260}
1261
Sanyog Kale89e59052018-04-26 18:38:08 +05301262/**
1263 * sdw_stream_add_master() - Allocate and add master runtime to a stream
1264 *
1265 * @bus: SDW Bus instance
1266 * @stream_config: Stream configuration for audio stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301267 * @port_config: Port configuration for audio stream
1268 * @num_ports: Number of ports
Sanyog Kale89e59052018-04-26 18:38:08 +05301269 * @stream: SoundWire stream
1270 */
1271int sdw_stream_add_master(struct sdw_bus *bus,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001272 struct sdw_stream_config *stream_config,
1273 struct sdw_port_config *port_config,
1274 unsigned int num_ports,
1275 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301276{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001277 struct sdw_master_runtime *m_rt;
Sanyog Kale89e59052018-04-26 18:38:08 +05301278 int ret;
1279
1280 mutex_lock(&bus->bus_lock);
1281
Shreyas NCce6e74d2018-07-27 14:44:16 +05301282 /*
1283 * For multi link streams, add the second master only if
1284 * the bus supports it.
1285 * Check if bus->multi_link is set
1286 */
1287 if (!bus->multi_link && stream->m_rt_count > 0) {
1288 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001289 "Multilink not supported, link %d\n", bus->link_id);
Shreyas NCce6e74d2018-07-27 14:44:16 +05301290 ret = -EINVAL;
1291 goto unlock;
1292 }
1293
Sanyog Kale89e59052018-04-26 18:38:08 +05301294 m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1295 if (!m_rt) {
1296 dev_err(bus->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001297 "Master runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001298 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301299 ret = -ENOMEM;
Shreyas NC3fef1a22018-07-27 14:44:09 +05301300 goto unlock;
Sanyog Kale89e59052018-04-26 18:38:08 +05301301 }
1302
1303 ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1304 if (ret)
1305 goto stream_error;
1306
Sanyog Kalebbe73792018-04-26 18:38:13 +05301307 ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1308 if (ret)
1309 goto stream_error;
1310
Shreyas NCce6e74d2018-07-27 14:44:16 +05301311 stream->m_rt_count++;
1312
Shreyas NC3fef1a22018-07-27 14:44:09 +05301313 goto unlock;
1314
Sanyog Kale89e59052018-04-26 18:38:08 +05301315stream_error:
Vinod Koul48949722018-07-27 14:44:14 +05301316 sdw_release_master_stream(m_rt, stream);
Shreyas NC3fef1a22018-07-27 14:44:09 +05301317unlock:
Sanyog Kale89e59052018-04-26 18:38:08 +05301318 mutex_unlock(&bus->bus_lock);
1319 return ret;
1320}
1321EXPORT_SYMBOL(sdw_stream_add_master);
1322
1323/**
1324 * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1325 *
1326 * @slave: SDW Slave instance
1327 * @stream_config: Stream configuration for audio stream
1328 * @stream: SoundWire stream
Sanyog Kalebbe73792018-04-26 18:38:13 +05301329 * @port_config: Port configuration for audio stream
1330 * @num_ports: Number of ports
Shreyas NC0aebe402018-07-27 14:44:08 +05301331 *
1332 * It is expected that Slave is added before adding Master
1333 * to the Stream.
1334 *
Sanyog Kale89e59052018-04-26 18:38:08 +05301335 */
1336int sdw_stream_add_slave(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001337 struct sdw_stream_config *stream_config,
1338 struct sdw_port_config *port_config,
1339 unsigned int num_ports,
1340 struct sdw_stream_runtime *stream)
Sanyog Kale89e59052018-04-26 18:38:08 +05301341{
1342 struct sdw_slave_runtime *s_rt;
1343 struct sdw_master_runtime *m_rt;
1344 int ret;
1345
1346 mutex_lock(&slave->bus->bus_lock);
1347
1348 /*
1349 * If this API is invoked by Slave first then m_rt is not valid.
1350 * So, allocate m_rt and add Slave to it.
1351 */
1352 m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1353 if (!m_rt) {
1354 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001355 "alloc master runtime failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001356 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301357 ret = -ENOMEM;
1358 goto error;
1359 }
1360
1361 s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1362 if (!s_rt) {
1363 dev_err(&slave->dev,
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001364 "Slave runtime config failed for stream:%s\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001365 stream->name);
Sanyog Kale89e59052018-04-26 18:38:08 +05301366 ret = -ENOMEM;
1367 goto stream_error;
1368 }
1369
1370 ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1371 if (ret)
1372 goto stream_error;
1373
1374 list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1375
Sanyog Kalebbe73792018-04-26 18:38:13 +05301376 ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1377 if (ret)
1378 goto stream_error;
1379
Shreyas NC0aebe402018-07-27 14:44:08 +05301380 /*
1381 * Change stream state to CONFIGURED on first Slave add.
1382 * Bus is not aware of number of Slave(s) in a stream at this
1383 * point so cannot depend on all Slave(s) to be added in order to
1384 * change stream state to CONFIGURED.
1385 */
Sanyog Kale89e59052018-04-26 18:38:08 +05301386 stream->state = SDW_STREAM_CONFIGURED;
1387 goto error;
1388
1389stream_error:
1390 /*
1391 * we hit error so cleanup the stream, release all Slave(s) and
1392 * Master runtime
1393 */
Vinod Koul48949722018-07-27 14:44:14 +05301394 sdw_release_master_stream(m_rt, stream);
Sanyog Kale89e59052018-04-26 18:38:08 +05301395error:
1396 mutex_unlock(&slave->bus->bus_lock);
1397 return ret;
1398}
1399EXPORT_SYMBOL(sdw_stream_add_slave);
Sanyog Kalef8101c72018-04-26 18:38:17 +05301400
1401/**
1402 * sdw_get_slave_dpn_prop() - Get Slave port capabilities
1403 *
1404 * @slave: Slave handle
1405 * @direction: Data direction.
1406 * @port_num: Port number
1407 */
1408struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001409 enum sdw_data_direction direction,
1410 unsigned int port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301411{
1412 struct sdw_dpn_prop *dpn_prop;
1413 u8 num_ports;
1414 int i;
1415
1416 if (direction == SDW_DATA_DIR_TX) {
1417 num_ports = hweight32(slave->prop.source_ports);
1418 dpn_prop = slave->prop.src_dpn_prop;
1419 } else {
1420 num_ports = hweight32(slave->prop.sink_ports);
1421 dpn_prop = slave->prop.sink_dpn_prop;
1422 }
1423
1424 for (i = 0; i < num_ports; i++) {
Srinivas Kandagatla03ecad92019-05-22 17:24:43 +01001425 if (dpn_prop[i].num == port_num)
Sanyog Kalef8101c72018-04-26 18:38:17 +05301426 return &dpn_prop[i];
1427 }
1428
1429 return NULL;
1430}
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301431
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301432/**
1433 * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s)
1434 *
1435 * @stream: SoundWire stream
1436 *
1437 * Acquire bus_lock for each of the master runtime(m_rt) part of this
1438 * stream to reconfigure the bus.
1439 * NOTE: This function is called from SoundWire stream ops and is
1440 * expected that a global lock is held before acquiring bus_lock.
1441 */
1442static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream)
1443{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001444 struct sdw_master_runtime *m_rt;
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301445 struct sdw_bus *bus = NULL;
1446
1447 /* Iterate for all Master(s) in Master list */
1448 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1449 bus = m_rt->bus;
1450
1451 mutex_lock(&bus->bus_lock);
1452 }
1453}
1454
1455/**
1456 * sdw_release_bus_lock: Release bus lock for all Master runtime(s)
1457 *
1458 * @stream: SoundWire stream
1459 *
1460 * Release the previously held bus_lock after reconfiguring the bus.
Vinod Koul48949722018-07-27 14:44:14 +05301461 * NOTE: This function is called from SoundWire stream ops and is
1462 * expected that a global lock is held before releasing bus_lock.
Sanyog Kale0c4a1042018-07-27 14:44:13 +05301463 */
1464static void sdw_release_bus_lock(struct sdw_stream_runtime *stream)
1465{
1466 struct sdw_master_runtime *m_rt = NULL;
1467 struct sdw_bus *bus = NULL;
1468
1469 /* Iterate for all Master(s) in Master list */
1470 list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) {
1471 bus = m_rt->bus;
1472 mutex_unlock(&bus->bus_lock);
1473 }
1474}
1475
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001476static int _sdw_prepare_stream(struct sdw_stream_runtime *stream,
1477 bool update_params)
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301478{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001479 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301480 struct sdw_bus *bus = NULL;
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001481 struct sdw_master_prop *prop;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301482 struct sdw_bus_params params;
1483 int ret;
1484
Vinod Koul48949722018-07-27 14:44:14 +05301485 /* Prepare Master(s) and Slave(s) port(s) associated with stream */
1486 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1487 bus = m_rt->bus;
1488 prop = &bus->prop;
1489 memcpy(&params, &bus->params, sizeof(params));
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301490
Vinod Koul48949722018-07-27 14:44:14 +05301491 /* TODO: Support Asynchronous mode */
Pierre-Louis Bossart34243052019-05-22 14:47:22 -05001492 if ((prop->max_clk_freq % stream->params.rate) != 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001493 dev_err(bus->dev, "Async mode not supported\n");
Vinod Koul48949722018-07-27 14:44:14 +05301494 return -EINVAL;
1495 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301496
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001497 if (!update_params)
1498 goto program_params;
1499
Vinod Koul48949722018-07-27 14:44:14 +05301500 /* Increment cumulative bus bandwidth */
1501 /* TODO: Update this during Device-Device support */
1502 bus->params.bandwidth += m_rt->stream->params.rate *
1503 m_rt->ch_count * m_rt->stream->params.bps;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301504
Vinod Koulc7578c12019-08-13 09:35:46 +01001505 /* Compute params */
1506 if (bus->compute_params) {
1507 ret = bus->compute_params(bus);
1508 if (ret < 0) {
1509 dev_err(bus->dev, "Compute params failed: %d",
1510 ret);
1511 return ret;
1512 }
1513 }
1514
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001515program_params:
Vinod Koul48949722018-07-27 14:44:14 +05301516 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001517 ret = sdw_program_params(bus, true);
Vinod Koul48949722018-07-27 14:44:14 +05301518 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001519 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301520 goto restore_params;
1521 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301522 }
1523
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001524 if (!bus) {
1525 pr_err("Configuration error in %s\n", __func__);
1526 return -EINVAL;
1527 }
1528
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301529 ret = do_bank_switch(stream);
1530 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001531 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301532 goto restore_params;
1533 }
1534
Vinod Koul48949722018-07-27 14:44:14 +05301535 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1536 bus = m_rt->bus;
1537
1538 /* Prepare port(s) on the new clock configuration */
1539 ret = sdw_prep_deprep_ports(m_rt, true);
1540 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001541 dev_err(bus->dev, "Prepare port(s) failed ret = %d\n",
Pierre-Louis Bossart1fe74a5e2019-05-01 10:57:35 -05001542 ret);
Vinod Koul48949722018-07-27 14:44:14 +05301543 return ret;
1544 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301545 }
1546
1547 stream->state = SDW_STREAM_PREPARED;
1548
1549 return ret;
1550
1551restore_params:
1552 memcpy(&bus->params, &params, sizeof(params));
1553 return ret;
1554}
1555
1556/**
1557 * sdw_prepare_stream() - Prepare SoundWire stream
1558 *
1559 * @stream: Soundwire stream
1560 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001561 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301562 */
1563int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1564{
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001565 bool update_params = true;
Bard Liaoc32464c2020-01-14 17:52:24 -06001566 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301567
1568 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001569 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301570 return -EINVAL;
1571 }
1572
Vinod Koul48949722018-07-27 14:44:14 +05301573 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301574
Bard Liaoc32464c2020-01-14 17:52:24 -06001575 if (stream->state == SDW_STREAM_PREPARED) {
1576 ret = 0;
1577 goto state_err;
1578 }
1579
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001580 if (stream->state != SDW_STREAM_CONFIGURED &&
1581 stream->state != SDW_STREAM_DEPREPARED &&
1582 stream->state != SDW_STREAM_DISABLED) {
1583 pr_err("%s: %s: inconsistent state state %d\n",
1584 __func__, stream->name, stream->state);
1585 ret = -EINVAL;
1586 goto state_err;
1587 }
1588
Pierre-Louis Bossartc7a8f042020-01-14 17:52:25 -06001589 /*
1590 * when the stream is DISABLED, this means sdw_prepare_stream()
1591 * is called as a result of an underflow or a resume operation.
1592 * In this case, the bus parameters shall not be recomputed, but
1593 * still need to be re-applied
1594 */
1595 if (stream->state == SDW_STREAM_DISABLED)
1596 update_params = false;
1597
1598 ret = _sdw_prepare_stream(stream, update_params);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301599
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001600state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301601 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301602 return ret;
1603}
1604EXPORT_SYMBOL(sdw_prepare_stream);
1605
1606static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1607{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001608 struct sdw_master_runtime *m_rt;
Vinod Koul48949722018-07-27 14:44:14 +05301609 struct sdw_bus *bus = NULL;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301610 int ret;
1611
Vinod Koul48949722018-07-27 14:44:14 +05301612 /* Enable Master(s) and Slave(s) port(s) associated with stream */
1613 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1614 bus = m_rt->bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301615
Vinod Koul48949722018-07-27 14:44:14 +05301616 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001617 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301618 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001619 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301620 return ret;
1621 }
1622
1623 /* Enable port(s) */
1624 ret = sdw_enable_disable_ports(m_rt, true);
1625 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301626 dev_err(bus->dev,
1627 "Enable port(s) failed ret: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301628 return ret;
1629 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301630 }
1631
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001632 if (!bus) {
1633 pr_err("Configuration error in %s\n", __func__);
1634 return -EINVAL;
1635 }
1636
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301637 ret = do_bank_switch(stream);
1638 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001639 dev_err(bus->dev, "Bank switch failed: %d\n", ret);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301640 return ret;
1641 }
1642
1643 stream->state = SDW_STREAM_ENABLED;
1644 return 0;
1645}
1646
1647/**
1648 * sdw_enable_stream() - Enable SoundWire stream
1649 *
1650 * @stream: Soundwire stream
1651 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001652 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301653 */
1654int sdw_enable_stream(struct sdw_stream_runtime *stream)
1655{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001656 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301657
1658 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001659 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301660 return -EINVAL;
1661 }
1662
Vinod Koul48949722018-07-27 14:44:14 +05301663 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301664
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001665 if (stream->state != SDW_STREAM_PREPARED &&
1666 stream->state != SDW_STREAM_DISABLED) {
1667 pr_err("%s: %s: inconsistent state state %d\n",
1668 __func__, stream->name, stream->state);
1669 ret = -EINVAL;
1670 goto state_err;
1671 }
1672
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301673 ret = _sdw_enable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301674
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001675state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301676 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301677 return ret;
1678}
1679EXPORT_SYMBOL(sdw_enable_stream);
1680
1681static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1682{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001683 struct sdw_master_runtime *m_rt;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301684 int ret;
1685
Vinod Koul48949722018-07-27 14:44:14 +05301686 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001687 struct sdw_bus *bus = m_rt->bus;
1688
Vinod Koul48949722018-07-27 14:44:14 +05301689 /* Disable port(s) */
1690 ret = sdw_enable_disable_ports(m_rt, false);
1691 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001692 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301693 return ret;
1694 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301695 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301696 stream->state = SDW_STREAM_DISABLED;
1697
Vinod Koul48949722018-07-27 14:44:14 +05301698 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001699 struct sdw_bus *bus = m_rt->bus;
1700
Vinod Koul48949722018-07-27 14:44:14 +05301701 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001702 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301703 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001704 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301705 return ret;
1706 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301707 }
1708
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001709 ret = do_bank_switch(stream);
1710 if (ret < 0) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001711 pr_err("Bank switch failed: %d\n", ret);
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001712 return ret;
1713 }
1714
1715 /* make sure alternate bank (previous current) is also disabled */
1716 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001717 struct sdw_bus *bus = m_rt->bus;
1718
Pierre-Louis Bossarte0279b62019-08-05 19:55:13 -05001719 /* Disable port(s) */
1720 ret = sdw_enable_disable_ports(m_rt, false);
1721 if (ret < 0) {
1722 dev_err(bus->dev, "Disable port(s) failed: %d\n", ret);
1723 return ret;
1724 }
1725 }
1726
1727 return 0;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301728}
1729
1730/**
1731 * sdw_disable_stream() - Disable SoundWire stream
1732 *
1733 * @stream: Soundwire stream
1734 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001735 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301736 */
1737int sdw_disable_stream(struct sdw_stream_runtime *stream)
1738{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001739 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301740
1741 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001742 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301743 return -EINVAL;
1744 }
1745
Vinod Koul48949722018-07-27 14:44:14 +05301746 sdw_acquire_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301747
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001748 if (stream->state != SDW_STREAM_ENABLED) {
1749 pr_err("%s: %s: inconsistent state state %d\n",
1750 __func__, stream->name, stream->state);
1751 ret = -EINVAL;
1752 goto state_err;
1753 }
1754
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301755 ret = _sdw_disable_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301756
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001757state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301758 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301759 return ret;
1760}
1761EXPORT_SYMBOL(sdw_disable_stream);
1762
1763static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1764{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001765 struct sdw_master_runtime *m_rt;
1766 struct sdw_bus *bus;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301767 int ret = 0;
1768
Vinod Koul48949722018-07-27 14:44:14 +05301769 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1770 bus = m_rt->bus;
1771 /* De-prepare port(s) */
1772 ret = sdw_prep_deprep_ports(m_rt, false);
1773 if (ret < 0) {
Vinod Koul62f0cec2019-05-02 16:29:24 +05301774 dev_err(bus->dev,
1775 "De-prepare port(s) failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301776 return ret;
1777 }
1778
1779 /* TODO: Update this during Device-Device support */
1780 bus->params.bandwidth -= m_rt->stream->params.rate *
1781 m_rt->ch_count * m_rt->stream->params.bps;
1782
1783 /* Program params */
Rander Wangbfaa3542020-01-14 17:52:27 -06001784 ret = sdw_program_params(bus, false);
Vinod Koul48949722018-07-27 14:44:14 +05301785 if (ret < 0) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001786 dev_err(bus->dev, "Program params failed: %d\n", ret);
Vinod Koul48949722018-07-27 14:44:14 +05301787 return ret;
1788 }
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301789 }
1790
1791 stream->state = SDW_STREAM_DEPREPARED;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301792 return do_bank_switch(stream);
1793}
1794
1795/**
1796 * sdw_deprepare_stream() - Deprepare SoundWire stream
1797 *
1798 * @stream: Soundwire stream
1799 *
Mauro Carvalho Chehab34962fb2018-05-08 15:14:57 -03001800 * Documentation/driver-api/soundwire/stream.rst explains this API in detail
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301801 */
1802int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1803{
Pierre-Louis Bossart3a0be1a2019-08-05 19:55:14 -05001804 int ret;
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301805
1806 if (!stream) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001807 pr_err("SoundWire: Handle not found for stream\n");
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301808 return -EINVAL;
1809 }
1810
Vinod Koul48949722018-07-27 14:44:14 +05301811 sdw_acquire_bus_lock(stream);
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001812
1813 if (stream->state != SDW_STREAM_PREPARED &&
1814 stream->state != SDW_STREAM_DISABLED) {
1815 pr_err("%s: %s: inconsistent state state %d\n",
1816 __func__, stream->name, stream->state);
1817 ret = -EINVAL;
1818 goto state_err;
1819 }
1820
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301821 ret = _sdw_deprepare_stream(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301822
Pierre-Louis Bossart59528802020-01-14 17:52:23 -06001823state_err:
Vinod Koul48949722018-07-27 14:44:14 +05301824 sdw_release_bus_lock(stream);
Sanyog Kale5c3eb9f2018-04-26 18:38:33 +05301825 return ret;
1826}
1827EXPORT_SYMBOL(sdw_deprepare_stream);