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review.shift-gmbh.com / SHIFTPHONES / kernel / common / bddb3636737f658886a0a02b64db5366bba3428e / . / drivers / thermal / ti-soc-thermal / omap4xxx-bandgap.h
blob: a453ff8eb313e185895208ac4855639a388ef011 [file] [log] [blame]
Thomas Gleixner2b27bdc2019-05-29 16:57:50 -0700[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Eduardo Valentin787f3c22013-03-15 08:59:51 -0400[diff] [blame]2/*
3 * OMAP4xxx bandgap registers, bitfields and temperature definitions
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 * Contact:
7 * Eduardo Valentin <eduardo.valentin@ti.com>
Eduardo Valentin787f3c22013-03-15 08:59:51 -0400[diff] [blame]8 */
9#ifndef __OMAP4XXX_BANDGAP_H
10#define __OMAP4XXX_BANDGAP_H
11
12/**
13 * *** OMAP4430 ***
14 *
15 * Below, in sequence, are the Register definitions,
16 * the bitfields and the temperature definitions for OMAP4430.
17 */
18
19/**
20 * OMAP4430 register definitions
21 *
22 * Registers are defined as offsets. The offsets are
23 * relative to FUSE_OPP_BGAP on 4430.
24 */
25
26/* OMAP4430.FUSE_OPP_BGAP */
27#define OMAP4430_FUSE_OPP_BGAP 0x0
28
29/* OMAP4430.TEMP_SENSOR */
30#define OMAP4430_TEMP_SENSOR_CTRL_OFFSET 0xCC
31
32/**
33 * Register and bit definitions for OMAP4430
34 *
35 * All the macros bellow define the required bits for
36 * controlling temperature on OMAP4430. Bit defines are
37 * grouped by register.
38 */
39
40/* OMAP4430.TEMP_SENSOR bits */
41#define OMAP4430_BGAP_TEMPSOFF_MASK BIT(12)
42#define OMAP4430_BGAP_TSHUT_MASK BIT(11)
43#define OMAP4430_SINGLE_MODE_MASK BIT(10)
44#define OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK BIT(9)
45#define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(8)
46#define OMAP4430_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
47
48/**
49 * Temperature limits and thresholds for OMAP4430
50 *
51 * All the macros bellow are definitions for handling the
52 * ADC conversions and representation of temperature limits
53 * and thresholds for OMAP4430.
54 */
55
56/* ADC conversion table limits */
57#define OMAP4430_ADC_START_VALUE 0
58#define OMAP4430_ADC_END_VALUE 127
59/* bandgap clock limits (no control on 4430) */
60#define OMAP4430_MAX_FREQ 32768
61#define OMAP4430_MIN_FREQ 32768
Eduardo Valentin787f3c22013-03-15 08:59:51 -0400[diff] [blame]62
63/**
64 * *** OMAP4460 *** Applicable for OMAP4470
65 *
66 * Below, in sequence, are the Register definitions,
67 * the bitfields and the temperature definitions for OMAP4460.
68 */
69
70/**
71 * OMAP4460 register definitions
72 *
73 * Registers are defined as offsets. The offsets are
74 * relative to FUSE_OPP_BGAP on 4460.
75 */
76
77/* OMAP4460.FUSE_OPP_BGAP */
78#define OMAP4460_FUSE_OPP_BGAP 0x0
79
80/* OMAP4460.TEMP_SENSOR */
81#define OMAP4460_TEMP_SENSOR_CTRL_OFFSET 0xCC
82
83/* OMAP4460.BANDGAP_CTRL */
84#define OMAP4460_BGAP_CTRL_OFFSET 0x118
85
86/* OMAP4460.BANDGAP_COUNTER */
87#define OMAP4460_BGAP_COUNTER_OFFSET 0x11C
88
89/* OMAP4460.BANDGAP_THRESHOLD */
90#define OMAP4460_BGAP_THRESHOLD_OFFSET 0x120
91
92/* OMAP4460.TSHUT_THRESHOLD */
93#define OMAP4460_BGAP_TSHUT_OFFSET 0x124
94
95/* OMAP4460.BANDGAP_STATUS */
96#define OMAP4460_BGAP_STATUS_OFFSET 0x128
97
98/**
99 * Register bitfields for OMAP4460
100 *
101 * All the macros bellow define the required bits for
102 * controlling temperature on OMAP4460. Bit defines are
103 * grouped by register.
104 */
105/* OMAP4460.TEMP_SENSOR bits */
106#define OMAP4460_BGAP_TEMPSOFF_MASK BIT(13)
107#define OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK BIT(11)
108#define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
109#define OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
110
111/* OMAP4460.BANDGAP_CTRL bits */
112#define OMAP4460_SINGLE_MODE_MASK BIT(31)
113#define OMAP4460_MASK_HOT_MASK BIT(1)
114#define OMAP4460_MASK_COLD_MASK BIT(0)
115
116/* OMAP4460.BANDGAP_COUNTER bits */
117#define OMAP4460_COUNTER_MASK (0xffffff << 0)
118
119/* OMAP4460.BANDGAP_THRESHOLD bits */
120#define OMAP4460_T_HOT_MASK (0x3ff << 16)
121#define OMAP4460_T_COLD_MASK (0x3ff << 0)
122
123/* OMAP4460.TSHUT_THRESHOLD bits */
124#define OMAP4460_TSHUT_HOT_MASK (0x3ff << 16)
125#define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0)
126
127/* OMAP4460.BANDGAP_STATUS bits */
Eduardo Valentin787f3c22013-03-15 08:59:51 -0400[diff] [blame]128#define OMAP4460_HOT_FLAG_MASK BIT(1)
129#define OMAP4460_COLD_FLAG_MASK BIT(0)
130
131/**
132 * Temperature limits and thresholds for OMAP4460
133 *
134 * All the macros bellow are definitions for handling the
135 * ADC conversions and representation of temperature limits
136 * and thresholds for OMAP4460.
137 */
138
139/* ADC conversion table limits */
140#define OMAP4460_ADC_START_VALUE 530
141#define OMAP4460_ADC_END_VALUE 932
142/* bandgap clock limits */
143#define OMAP4460_MAX_FREQ 1500000
144#define OMAP4460_MIN_FREQ 1000000
Eduardo Valentin787f3c22013-03-15 08:59:51 -0400[diff] [blame]145/* interrupts thresholds */
146#define OMAP4460_TSHUT_HOT 900 /* 122 deg C */
147#define OMAP4460_TSHUT_COLD 895 /* 100 deg C */
148#define OMAP4460_T_HOT 800 /* 73 deg C */
149#define OMAP4460_T_COLD 795 /* 71 deg C */
150
151#endif /* __OMAP4XXX_BANDGAP_H */