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review.shift-gmbh.com / SHIFTPHONES / kernel / common / bddb3636737f658886a0a02b64db5366bba3428e / . / arch / arm / boot / dts / imx51.dtsi
blob: 0a4b9a5d9a9c9698fd71c5e4b6378a6fc77659c5 [file] [log] [blame]
Fabio Estevam241f76b2018-05-07 15:23:40 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]5
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]6#include "imx51-pinfunc.h"
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]7#include <dt-bindings/clock/imx5-clock.h>
Alexander Shiyanbdb3eec2013-11-19 15:47:27 +0400[diff] [blame]8#include <dt-bindings/gpio/gpio.h>
Alexander Shiyan72d86d22014-01-11 10:54:19 +0400[diff] [blame]9#include <dt-bindings/input/input.h>
10#include <dt-bindings/interrupt-controller/irq.h>
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]11
12/ {
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame]13 #address-cells = <1>;
14 #size-cells = <1>;
Fabio Estevama971c552017-01-23 14:54:10 -0200[diff] [blame]15 /*
16 * The decompressor and also some bootloaders rely on a
17 * pre-existing /chosen node to be available to insert the
18 * command line and merge other ATAGS info.
Fabio Estevama971c552017-01-23 14:54:10 -0200[diff] [blame]19 */
20 chosen {};
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame]21
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]22 aliases {
Marek Vasut22970072014-02-28 12:58:41 +0100[diff] [blame]23 ethernet0 = &fec;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
Sascha Hauere3b73c62013-06-25 15:51:55 +0200[diff] [blame]28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
Sascha Hauerf742c222014-01-16 13:44:21 +0100[diff] [blame]30 mmc0 = &esdhc1;
31 mmc1 = &esdhc2;
32 mmc2 = &esdhc3;
33 mmc3 = &esdhc4;
Sascha Hauere3b73c62013-06-25 15:51:55 +0200[diff] [blame]34 serial0 = &uart1;
35 serial1 = &uart2;
36 serial2 = &uart3;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &cspi;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]40 };
41
42 tzic: tz-interrupt-controller@e0000000 {
43 compatible = "fsl,imx51-tzic", "fsl,tzic";
44 interrupt-controller;
45 #interrupt-cells = <1>;
46 reg = <0xe0000000 0x4000>;
47 };
48
49 clocks {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]50 ckil {
51 compatible = "fsl,imx-ckil", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +0800[diff] [blame]52 #clock-cells = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]53 clock-frequency = <32768>;
54 };
55
56 ckih1 {
57 compatible = "fsl,imx-ckih1", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +0800[diff] [blame]58 #clock-cells = <0>;
Alexander Shiyan677e28b2013-07-27 11:19:45 +0400[diff] [blame]59 clock-frequency = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]60 };
61
62 ckih2 {
63 compatible = "fsl,imx-ckih2", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +0800[diff] [blame]64 #clock-cells = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]65 clock-frequency = <0>;
66 };
67
68 osc {
69 compatible = "fsl,imx-osc", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +0800[diff] [blame]70 #clock-cells = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]71 clock-frequency = <24000000>;
72 };
73 };
74
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
Alexander Shiyan6acde882013-11-07 12:45:05 +0400[diff] [blame]78 cpu: cpu@0 {
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]79 device_type = "cpu";
80 compatible = "arm,cortex-a8";
81 reg = <0>;
Alexander Shiyan6acde882013-11-07 12:45:05 +0400[diff] [blame]82 clock-latency = <62500>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]83 clocks = <&clks IMX5_CLK_CPU_PODF>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]84 clock-names = "cpu";
85 operating-points = <
Alexander Shiyan6acde882013-11-07 12:45:05 +0400[diff] [blame]86 166000 1000000
87 600000 1050000
88 800000 1100000
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]89 >;
Alexander Shiyan6acde882013-11-07 12:45:05 +0400[diff] [blame]90 voltage-tolerance = <5>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +0200[diff] [blame]91 };
92 };
93
Fabio Estevam4b301222018-07-10 13:31:44 -0300[diff] [blame]94 pmu: pmu {
95 compatible = "arm,cortex-a8-pmu";
96 interrupt-parent = <&tzic>;
97 interrupts = <77>;
98 };
99
Fabio Estevam82210bf2018-07-03 10:05:54 -0300[diff] [blame]100 usbphy0: usbphy0 {
101 compatible = "usb-nop-xceiv";
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
103 clock-names = "main_clk";
104 #phy-cells = <0>;
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]105 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]106
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]107 display-subsystem {
108 compatible = "fsl,imx-display-subsystem";
109 ports = <&ipu_di0>, <&ipu_di1>;
110 };
111
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]112 soc {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 compatible = "simple-bus";
116 interrupt-parent = <&tzic>;
117 ranges;
118
Alexander Shiyanda38ea32013-08-21 11:28:24 +0400[diff] [blame]119 iram: iram@1ffe0000 {
120 compatible = "mmio-sram";
121 reg = <0x1ffe0000 0x20000>;
122 };
123
Jonathan Marek006303d2018-12-04 10:17:00 -0500[diff] [blame]124 gpu: gpu@30000000 {
125 compatible = "amd,imageon-200.1", "amd,imageon";
126 reg = <0x30000000 0x20000>;
127 reg-names = "kgsl_3d0_reg_memory";
128 interrupts = <12>;
129 interrupt-names = "kgsl_3d0_irq";
130 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
131 clock-names = "core_clk", "mem_iface_clk";
132 };
133
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]134 ipu: ipu@40000000 {
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]135 #address-cells = <1>;
136 #size-cells = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]137 compatible = "fsl,imx51-ipu";
138 reg = <0x40000000 0x20000000>;
139 interrupts = <11 10>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]140 clocks = <&clks IMX5_CLK_IPU_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]141 <&clks IMX5_CLK_IPU_DI0_GATE>,
142 <&clks IMX5_CLK_IPU_DI1_GATE>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]143 clock-names = "bus", "di0", "di1";
144 resets = <&src 2>;
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]145
146 ipu_di0: port@2 {
147 reg = <2>;
148
Marco Franchif7059422017-10-05 11:31:41 -0300[diff] [blame]149 ipu_di0_disp1: endpoint {
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]150 };
151 };
152
153 ipu_di1: port@3 {
154 reg = <3>;
155
Marco Franchif7059422017-10-05 11:31:41 -0300[diff] [blame]156 ipu_di1_disp2: endpoint {
Philipp Zabelde10e042014-03-05 10:20:59 +0100[diff] [blame]157 };
158 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]159 };
160
161 aips@70000000 { /* AIPS1 */
162 compatible = "fsl,aips-bus", "simple-bus";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 reg = <0x70000000 0x10000000>;
166 ranges;
167
168 spba@70000000 {
169 compatible = "fsl,spba-bus", "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 reg = <0x70000000 0x40000>;
173 ranges;
174
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]175 esdhc1: esdhc@70004000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]176 compatible = "fsl,imx51-esdhc";
177 reg = <0x70004000 0x4000>;
178 interrupts = <1>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]179 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]180 <&clks IMX5_CLK_DUMMY>,
181 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]182 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]183 status = "disabled";
184 };
185
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]186 esdhc2: esdhc@70008000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]187 compatible = "fsl,imx51-esdhc";
188 reg = <0x70008000 0x4000>;
189 interrupts = <2>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]190 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]191 <&clks IMX5_CLK_DUMMY>,
192 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]193 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]194 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]195 status = "disabled";
196 };
197
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]198 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]199 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
200 reg = <0x7000c000 0x4000>;
201 interrupts = <33>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]202 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]203 <&clks IMX5_CLK_UART3_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]204 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]205 status = "disabled";
206 };
207
Rob Herring5a2ecf02018-09-13 13:12:29 -0500[diff] [blame]208 ecspi1: spi@70010000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,imx51-ecspi";
212 reg = <0x70010000 0x4000>;
213 interrupts = <36>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]214 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]215 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]216 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]217 status = "disabled";
218 };
219
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]220 ssi2: ssi@70014000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400[diff] [blame]221 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]222 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
223 reg = <0x70014000 0x4000>;
224 interrupts = <30>;
Fabio Estevam53ec8742014-09-18 20:23:49 -0300[diff] [blame]225 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
226 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
227 clock-names = "ipg", "baud";
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]228 dmas = <&sdma 24 1 0>,
229 <&sdma 25 1 0>;
230 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]231 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]232 status = "disabled";
233 };
234
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]235 esdhc3: esdhc@70020000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]236 compatible = "fsl,imx51-esdhc";
237 reg = <0x70020000 0x4000>;
238 interrupts = <3>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]239 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]240 <&clks IMX5_CLK_DUMMY>,
241 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]242 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]243 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]244 status = "disabled";
245 };
246
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]247 esdhc4: esdhc@70024000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]248 compatible = "fsl,imx51-esdhc";
249 reg = <0x70024000 0x4000>;
250 interrupts = <4>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]251 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]252 <&clks IMX5_CLK_DUMMY>,
253 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]254 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]255 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]256 status = "disabled";
257 };
258 };
259
Fabio Estevamba72b5a2018-06-20 15:06:19 -0300[diff] [blame]260 aipstz1: bridge@73f00000 {
261 compatible = "fsl,imx51-aipstz";
262 reg = <0x73f00000 0x60>;
263 };
264
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]265 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]266 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
267 reg = <0x73f80000 0x0200>;
268 interrupts = <18>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]269 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]270 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]271 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]272 status = "disabled";
273 };
274
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]275 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]276 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
277 reg = <0x73f80200 0x0200>;
278 interrupts = <14>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]279 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]280 fsl,usbmisc = <&usbmisc 1>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]281 dr_mode = "host";
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]282 status = "disabled";
283 };
284
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]285 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]286 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
287 reg = <0x73f80400 0x0200>;
288 interrupts = <16>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]289 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]290 fsl,usbmisc = <&usbmisc 2>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]291 dr_mode = "host";
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]292 status = "disabled";
293 };
294
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]295 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]296 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
297 reg = <0x73f80600 0x0200>;
298 interrupts = <17>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]299 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]300 fsl,usbmisc = <&usbmisc 3>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]301 dr_mode = "host";
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]302 status = "disabled";
303 };
304
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]305 usbmisc: usbmisc@73f80800 {
306 #index-cells = <1>;
307 compatible = "fsl,imx51-usbmisc";
308 reg = <0x73f80800 0x200>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]310 };
311
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]312 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]313 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]314 reg = <0x73f84000 0x4000>;
315 interrupts = <50 51>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]319 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]320 };
321
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]322 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]323 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]324 reg = <0x73f88000 0x4000>;
325 interrupts = <52 53>;
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]329 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]330 };
331
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]332 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]333 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]334 reg = <0x73f8c000 0x4000>;
335 interrupts = <54 55>;
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]339 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]340 };
341
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]342 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]343 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]344 reg = <0x73f90000 0x4000>;
345 interrupts = <56 57>;
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]349 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]350 };
351
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]352 kpp: kpp@73f94000 {
353 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
354 reg = <0x73f94000 0x4000>;
355 interrupts = <60>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]356 clocks = <&clks IMX5_CLK_DUMMY>;
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]357 status = "disabled";
358 };
359
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]360 wdog1: wdog@73f98000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]361 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
362 reg = <0x73f98000 0x4000>;
363 interrupts = <58>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]364 clocks = <&clks IMX5_CLK_DUMMY>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]365 };
366
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]367 wdog2: wdog@73f9c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]368 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
369 reg = <0x73f9c000 0x4000>;
370 interrupts = <59>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]371 clocks = <&clks IMX5_CLK_DUMMY>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]372 status = "disabled";
373 };
374
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame]375 gpt: timer@73fa0000 {
376 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
377 reg = <0x73fa0000 0x4000>;
378 interrupts = <39>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]379 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]380 <&clks IMX5_CLK_GPT_HF_GATE>;
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame]381 clock-names = "ipg", "per";
382 };
383
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]384 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]385 compatible = "fsl,imx51-iomuxc";
386 reg = <0x73fa8000 0x4000>;
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]387 };
388
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]389 pwm1: pwm@73fb4000 {
390 #pwm-cells = <2>;
391 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
392 reg = <0x73fb4000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]393 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]394 <&clks IMX5_CLK_PWM1_HF_GATE>;
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]395 clock-names = "ipg", "per";
396 interrupts = <61>;
397 };
398
399 pwm2: pwm@73fb8000 {
400 #pwm-cells = <2>;
401 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
402 reg = <0x73fb8000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]403 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]404 <&clks IMX5_CLK_PWM2_HF_GATE>;
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]405 clock-names = "ipg", "per";
406 interrupts = <94>;
407 };
408
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]409 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]410 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
411 reg = <0x73fbc000 0x4000>;
412 interrupts = <31>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]413 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]414 <&clks IMX5_CLK_UART1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]415 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]416 status = "disabled";
417 };
418
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]419 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]420 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
421 reg = <0x73fc0000 0x4000>;
422 interrupts = <32>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]423 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]424 <&clks IMX5_CLK_UART2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]425 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]426 status = "disabled";
427 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]428
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]429 src: src@73fd0000 {
430 compatible = "fsl,imx51-src";
431 reg = <0x73fd0000 0x4000>;
432 #reset-cells = <1>;
433 };
434
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]435 clks: ccm@73fd4000{
436 compatible = "fsl,imx51-ccm";
437 reg = <0x73fd4000 0x4000>;
438 interrupts = <0 71 0x04 0 72 0x04>;
439 #clock-cells = <1>;
440 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]441 };
442
443 aips@80000000 { /* AIPS2 */
444 compatible = "fsl,aips-bus", "simple-bus";
445 #address-cells = <1>;
446 #size-cells = <1>;
447 reg = <0x80000000 0x10000000>;
448 ranges;
449
Fabio Estevamba72b5a2018-06-20 15:06:19 -0300[diff] [blame]450 aipstz2: bridge@83f00000 {
451 compatible = "fsl,imx51-aipstz";
452 reg = <0x83f00000 0x60>;
453 };
454
Sascha Hauer6510ea252013-06-25 15:51:51 +0200[diff] [blame]455 iim: iim@83f98000 {
456 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
457 reg = <0x83f98000 0x4000>;
458 interrupts = <69>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]459 clocks = <&clks IMX5_CLK_IIM_GATE>;
Sascha Hauer6510ea252013-06-25 15:51:51 +0200[diff] [blame]460 };
461
Fabio Estevamf2254a32018-07-10 13:31:45 -0300[diff] [blame]462 tigerp: tigerp@83fa0000 {
463 compatible = "fsl,imx51-tigerp";
464 reg = <0x83fa0000 0x28>;
465 };
466
Alexander Shiyanad15f082013-08-21 11:28:25 +0400[diff] [blame]467 owire: owire@83fa4000 {
468 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
469 reg = <0x83fa4000 0x4000>;
470 interrupts = <88>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]471 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
Alexander Shiyanad15f082013-08-21 11:28:25 +0400[diff] [blame]472 status = "disabled";
473 };
474
Rob Herring5a2ecf02018-09-13 13:12:29 -0500[diff] [blame]475 ecspi2: spi@83fac000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]476 #address-cells = <1>;
477 #size-cells = <0>;
478 compatible = "fsl,imx51-ecspi";
479 reg = <0x83fac000 0x4000>;
480 interrupts = <37>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]481 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]482 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]483 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]484 status = "disabled";
485 };
486
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]487 sdma: sdma@83fb0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]488 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
489 reg = <0x83fb0000 0x4000>;
490 interrupts = <6>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]491 clocks = <&clks IMX5_CLK_SDMA_GATE>,
Andrey Smirnov918bbde2019-03-28 23:49:23 -0700[diff] [blame]492 <&clks IMX5_CLK_AHB>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]493 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame]494 #dma-cells = <3>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]495 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]496 };
497
Rob Herring5a2ecf02018-09-13 13:12:29 -0500[diff] [blame]498 cspi: spi@83fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]499 #address-cells = <1>;
500 #size-cells = <0>;
501 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
502 reg = <0x83fc0000 0x4000>;
503 interrupts = <38>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]504 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]505 <&clks IMX5_CLK_CSPI_IPG_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]506 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]507 status = "disabled";
508 };
509
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]510 i2c2: i2c@83fc4000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]511 #address-cells = <1>;
512 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]513 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]514 reg = <0x83fc4000 0x4000>;
515 interrupts = <63>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]516 clocks = <&clks IMX5_CLK_I2C2_GATE>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]517 status = "disabled";
518 };
519
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]520 i2c1: i2c@83fc8000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]521 #address-cells = <1>;
522 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]523 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]524 reg = <0x83fc8000 0x4000>;
525 interrupts = <62>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]526 clocks = <&clks IMX5_CLK_I2C1_GATE>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]527 status = "disabled";
528 };
529
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]530 ssi1: ssi@83fcc000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400[diff] [blame]531 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]532 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
533 reg = <0x83fcc000 0x4000>;
534 interrupts = <29>;
Fabio Estevam53ec8742014-09-18 20:23:49 -0300[diff] [blame]535 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
536 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
537 clock-names = "ipg", "baud";
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]538 dmas = <&sdma 28 0 0>,
539 <&sdma 29 0 0>;
540 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]541 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]542 status = "disabled";
543 };
544
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]545 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]546 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
547 reg = <0x83fd0000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]548 clocks = <&clks IMX5_CLK_DUMMY>;
Alexander Shiyane030df92013-11-07 12:45:06 +0400[diff] [blame]549 clock-names = "audmux";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]550 status = "disabled";
551 };
552
Fabio Estevamb6b93a32018-07-09 15:19:14 -0300[diff] [blame]553 m4if: m4if@83fd8000 {
554 compatible = "fsl,imx51-m4if";
555 reg = <0x83fd8000 0x1000>;
556 };
557
Alexander Shiyanedd05282013-07-13 08:30:57 +0400[diff] [blame]558 weim: weim@83fda000 {
559 #address-cells = <2>;
560 #size-cells = <1>;
561 compatible = "fsl,imx51-weim";
562 reg = <0x83fda000 0x1000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]563 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
Alexander Shiyanedd05282013-07-13 08:30:57 +0400[diff] [blame]564 ranges = <
565 0 0 0xb0000000 0x08000000
566 1 0 0xb8000000 0x08000000
567 2 0 0xc0000000 0x08000000
568 3 0 0xc8000000 0x04000000
569 4 0 0xcc000000 0x02000000
570 5 0 0xce000000 0x02000000
571 >;
572 status = "disabled";
573 };
574
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]575 nfc: nand@83fdb000 {
Alexander Shiyanf0e3f892014-04-16 11:24:50 +0400[diff] [blame]576 #address-cells = <1>;
577 #size-cells = <1>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]578 compatible = "fsl,imx51-nand";
579 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
580 interrupts = <8>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]581 clocks = <&clks IMX5_CLK_NFC_GATE>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]582 status = "disabled";
583 };
584
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]585 pata: pata@83fe0000 {
586 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
587 reg = <0x83fe0000 0x4000>;
588 interrupts = <70>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]589 clocks = <&clks IMX5_CLK_PATA_GATE>;
Sascha Hauer718a35002013-04-04 11:25:09 +0200[diff] [blame]590 status = "disabled";
591 };
592
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]593 ssi3: ssi@83fe8000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400[diff] [blame]594 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]595 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
596 reg = <0x83fe8000 0x4000>;
597 interrupts = <96>;
Fabio Estevam53ec8742014-09-18 20:23:49 -0300[diff] [blame]598 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
599 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
600 clock-names = "ipg", "baud";
Shawn Guo5da826a2013-07-17 13:50:54 +0800[diff] [blame]601 dmas = <&sdma 46 0 0>,
602 <&sdma 47 0 0>;
603 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]604 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]605 status = "disabled";
606 };
607
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]608 fec: ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]609 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
610 reg = <0x83fec000 0x4000>;
611 interrupts = <87>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100[diff] [blame]612 clocks = <&clks IMX5_CLK_FEC_GATE>,
Jagan Teki46311702016-10-26 15:31:01 +0530[diff] [blame]613 <&clks IMX5_CLK_FEC_GATE>,
614 <&clks IMX5_CLK_FEC_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]615 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]616 status = "disabled";
617 };
Philipp Zabel328bd822017-12-13 15:24:06 +0100[diff] [blame]618
Fabio Estevam41d9feb2018-09-11 17:10:42 -0300[diff] [blame]619 vpu: vpu@83ff4000 {
Philipp Zabel328bd822017-12-13 15:24:06 +0100[diff] [blame]620 compatible = "fsl,imx51-vpu", "cnm,codahx4";
621 reg = <0x83ff4000 0x1000>;
622 interrupts = <9>;
623 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
624 <&clks IMX5_CLK_VPU_GATE>;
625 clock-names = "per", "ahb";
626 resets = <&src 1>;
627 iram = <&iram>;
628 };
Fabio Estevam91527432018-06-26 20:18:52 -0300[diff] [blame]629
630 sahara: crypto@83ff8000 {
631 compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
632 reg = <0x83ff8000 0x4000>;
633 interrupts = <19 20>;
634 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
635 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
636 clock-names = "ipg", "ahb";
637 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]638 };
639 };
640};