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review.shift-gmbh.com / SHIFTPHONES / kernel / common / b81fd5ba6002306f0c2bf82514b2eeae6ee2bf32 / . / drivers / net / wireless / rtlwifi / rtl8723be / pwrseq.h
blob: a62f43ed8d325b14ad0cf4bbfaa47e2e9384977d [file] [log] [blame]
Larry Fingera619d1a2014-02-28 15:16:50 -0600[diff] [blame]1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8723BE_PWRSEQ_H__
27#define __RTL8723BE_PWRSEQ_H__
28
Larry Fingera619d1a2014-02-28 15:16:50 -0600[diff] [blame]29/* Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
30 * There are 6 HW Power States:
31 * 0: POFF--Power Off
32 * 1: PDN--Power Down
33 * 2: CARDEMU--Card Emulation
34 * 3: ACT--Active Mode
35 * 4: LPS--Low Power State
36 * 5: SUS--Suspend
37 *
38 * The transition from different states are defined below
39 * TRANS_CARDEMU_TO_ACT
40 * TRANS_ACT_TO_CARDEMU
41 * TRANS_CARDEMU_TO_SUS
42 * TRANS_SUS_TO_CARDEMU
43 * TRANS_CARDEMU_TO_PDN
44 * TRANS_ACT_TO_LPS
45 * TRANS_LPS_TO_ACT
46 *
47 * TRANS_END
48 */
49#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 23
50#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15
51#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15
52#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15
53#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15
54#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15
55#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15
56#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15
57#define RTL8723B_TRANS_END_STEPS 1
58
59#define RTL8723B_TRANS_CARDEMU_TO_ACT \
60 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
61 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
62 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
63 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
64 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
65 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
66 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
67 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
68 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \
69 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
70 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
72 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
74 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
75 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
76 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
77 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
78 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
80 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
81 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
82 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
84 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
85 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
86 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
87 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
88 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
89 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
90 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
91 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
92 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
94 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
96 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
98 {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
100 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
102 {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
104 {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
106
107#define RTL8723B_TRANS_ACT_TO_CARDEMU \
108 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
110 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
111 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
112 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
113 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
114 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
116 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
117 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
118 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
119 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
120 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
121 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
122 PWR_CMD_WRITE, BIT(5), BIT(5)}, \
123 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
124 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
125 PWR_CMD_WRITE, BIT(0), 0},
126
127#define RTL8723B_TRANS_CARDEMU_TO_SUS \
128 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
129 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
130 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
131 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
132 PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
133 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
134 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
135 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
136 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
137 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
138 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
139 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
140 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
141 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
142 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
143
144#define RTL8723B_TRANS_SUS_TO_CARDEMU \
145 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
146 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
147 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
148 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
149 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
150 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
151 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
153 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
154 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
155
156#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \
157 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
158 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
159 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
160 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
161 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
162 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
163 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
164 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
165 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
166 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
167 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
168 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
169 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
170 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
171 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
172
173#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \
174 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
175 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
176 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
177 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
178 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
179 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
180 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
182 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
184 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
185 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
186 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
187 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
188
189#define RTL8723B_TRANS_CARDEMU_TO_PDN \
190 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
191 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
192 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
193 PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, \
194 PWR_CMD_WRITE, 0xFF, 0x20}, \
195 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
196 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
197 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
198 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
199
200#define RTL8723B_TRANS_PDN_TO_CARDEMU \
201 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
203
204#define RTL8723B_TRANS_ACT_TO_LPS \
205 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
207 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
208 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
209 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
210 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
211 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
212 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
213 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
214 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
215 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
216 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
217 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
218 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
219 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
220 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
221 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
222 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
223 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \
225 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
226 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
227 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
228 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \
229 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
231
232#define RTL8723B_TRANS_LPS_TO_ACT \
233 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
234 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
235 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
236 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
237 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
238 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
239 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
240 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
241 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
242 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
243 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
244 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
245 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
246 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
247 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
249 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
250 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
251 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
252 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
253 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
254 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
255
256#define RTL8723B_TRANS_END \
257 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \
258 PWR_CMD_END, 0, 0},
259
260extern struct wlan_pwr_cfg rtl8723B_power_on_flow
261 [RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS +
262 RTL8723B_TRANS_END_STEPS];
263extern struct wlan_pwr_cfg rtl8723B_radio_off_flow
264 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
265 RTL8723B_TRANS_END_STEPS];
266extern struct wlan_pwr_cfg rtl8723B_card_disable_flow
267 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
268 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
269 RTL8723B_TRANS_END_STEPS];
270extern struct wlan_pwr_cfg rtl8723B_card_enable_flow
271 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
272 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
273 RTL8723B_TRANS_END_STEPS];
274extern struct wlan_pwr_cfg rtl8723B_suspend_flow
275 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
276 RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
277 RTL8723B_TRANS_END_STEPS];
278extern struct wlan_pwr_cfg rtl8723B_resume_flow
279 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
280 RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
281 RTL8723B_TRANS_END_STEPS];
282extern struct wlan_pwr_cfg rtl8723B_hwpdn_flow
283 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
284 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
285 RTL8723B_TRANS_END_STEPS];
286extern struct wlan_pwr_cfg rtl8723B_enter_lps_flow
287 [RTL8723B_TRANS_ACT_TO_LPS_STEPS +
288 RTL8723B_TRANS_END_STEPS];
289extern struct wlan_pwr_cfg rtl8723B_leave_lps_flow
290 [RTL8723B_TRANS_LPS_TO_ACT_STEPS +
291 RTL8723B_TRANS_END_STEPS];
292
293/* RTL8723 Power Configuration CMDs for PCIe interface */
294#define RTL8723_NIC_PWR_ON_FLOW rtl8723B_power_on_flow
295#define RTL8723_NIC_RF_OFF_FLOW rtl8723B_radio_off_flow
296#define RTL8723_NIC_DISABLE_FLOW rtl8723B_card_disable_flow
297#define RTL8723_NIC_ENABLE_FLOW rtl8723B_card_enable_flow
298#define RTL8723_NIC_SUSPEND_FLOW rtl8723B_suspend_flow
299#define RTL8723_NIC_RESUME_FLOW rtl8723B_resume_flow
300#define RTL8723_NIC_PDN_FLOW rtl8723B_hwpdn_flow
301#define RTL8723_NIC_LPS_ENTER_FLOW rtl8723B_enter_lps_flow
302#define RTL8723_NIC_LPS_LEAVE_FLOW rtl8723B_leave_lps_flow
303
304#endif