| Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Secondary CPU startup routine source file. |
| 3 | * |
| 4 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 5 | * |
| 6 | * Author: |
| 7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 8 | * |
| 9 | * Interface functions needed for the SMP. This file is based on arm |
| 10 | * realview smp platform. |
| 11 | * Copyright (c) 2003 ARM Limited. |
| 12 | * |
| 13 | * This program is free software,you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/linkage.h> |
| 19 | #include <linux/init.h> |
| 20 | |
| Russell King | 45176f4 | 2012-02-07 10:34:01 +0000 | [diff] [blame] | 21 | __CPUINIT |
| Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 22 | |
| 23 | /* Physical address needed since MMU not enabled yet on secondary core */ |
| 24 | #define AUX_CORE_BOOT0_PA 0x48281800 |
| 25 | |
| 26 | /* |
| 27 | * OMAP5 specific entry point for secondary CPU to jump from ROM |
| 28 | * code. This routine also provides a holding flag into which |
| 29 | * secondary core is held until we're ready for it to initialise. |
| 30 | * The primary core will update this flag using a hardware |
| 31 | + * register AuxCoreBoot0. |
| 32 | */ |
| 33 | ENTRY(omap5_secondary_startup) |
| 34 | wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 |
| 35 | ldr r0, [r2] |
| 36 | mov r0, r0, lsr #5 |
| 37 | mrc p15, 0, r4, c0, c0, 5 |
| 38 | and r4, r4, #0x0f |
| 39 | cmp r0, r4 |
| 40 | bne wait |
| 41 | b secondary_startup |
| 42 | END(omap5_secondary_startup) |
| Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 43 | /* |
| 44 | * OMAP4 specific entry point for secondary CPU to jump from ROM |
| 45 | * code. This routine also provides a holding flag into which |
| 46 | * secondary core is held until we're ready for it to initialise. |
| Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 47 | * The primary core will update this flag using a hardware |
| 48 | * register AuxCoreBoot0. |
| Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 49 | */ |
| 50 | ENTRY(omap_secondary_startup) |
| Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 51 | hold: ldr r12,=0x103 |
| 52 | dsb |
| Richard Woodruff | df571c4a | 2010-04-07 07:47:21 +0000 | [diff] [blame] | 53 | smc #0 @ read from AuxCoreBoot0 |
| Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 54 | mov r0, r0, lsr #9 |
| 55 | mrc p15, 0, r4, c0, c0, 5 |
| 56 | and r4, r4, #0x0f |
| 57 | cmp r0, r4 |
| Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 58 | bne hold |
| 59 | |
| 60 | /* |
| Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 61 | * we've been released from the wait loop,secondary_stack |
| Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 62 | * should now contain the SVC stack for this core |
| 63 | */ |
| 64 | b secondary_startup |
| Dave Martin | f96bdfa | 2011-03-04 15:33:54 +0000 | [diff] [blame] | 65 | ENDPROC(omap_secondary_startup) |
| Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 66 | |