blob: 6a32555971383bc7434eb07a711ff7ef5d060fd4 [file] [log] [blame]
Manivannan Sadhasivam3bba4e22019-01-25 22:12:49 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Linaro Ltd.
4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5 */
6
7/dts-v1/;
8
9#include "bm1880.dtsi"
10
11/ {
12 compatible = "bitmain,sophon-edge", "bitmain,bm1880";
13 model = "Sophon Edge";
14
15 aliases {
16 serial0 = &uart0;
17 serial1 = &uart2;
18 serial2 = &uart1;
19 };
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 };
24
25 memory@0 {
26 device_type = "memory";
27 reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
28 };
29
30 uart_clk: uart-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <500000000>;
33 #clock-cells = <0>;
34 };
35};
36
37&uart0 {
38 status = "okay";
39 clocks = <&uart_clk>;
40};
41
42&uart1 {
43 status = "okay";
44 clocks = <&uart_clk>;
45};
46
47&uart2 {
48 status = "okay";
49 clocks = <&uart_clk>;
50};