| Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 2 | if (BF537 || BF534 || BF536) |
| 3 | |
| Mike Frysinger | 4f25eb8 | 2007-11-15 20:49:44 +0800 | [diff] [blame] | 4 | source "arch/blackfin/mach-bf537/boards/Kconfig" |
| 5 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 6 | menu "BF537 Specific Configuration" |
| 7 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 8 | comment "Interrupt Priority Assignment" |
| 9 | menu "Priority" |
| 10 | |
| 11 | config IRQ_PLL_WAKEUP |
| 12 | int "IRQ_PLL_WAKEUP" |
| 13 | default 7 |
| 14 | config IRQ_DMA_ERROR |
| 15 | int "IRQ_DMA_ERROR Generic" |
| 16 | default 7 |
| 17 | config IRQ_ERROR |
| Michael Hennerich | 2adcf19 | 2010-05-21 13:20:38 +0000 | [diff] [blame] | 18 | int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1" |
| 19 | default 11 |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 20 | config IRQ_RTC |
| 21 | int "IRQ_RTC" |
| 22 | default 8 |
| 23 | config IRQ_PPI |
| 24 | int "IRQ_PPI" |
| 25 | default 8 |
| 26 | config IRQ_SPORT0_RX |
| 27 | int "IRQ_SPORT0_RX" |
| 28 | default 9 |
| 29 | config IRQ_SPORT0_TX |
| 30 | int "IRQ_SPORT0_TX" |
| 31 | default 9 |
| 32 | config IRQ_SPORT1_RX |
| 33 | int "IRQ_SPORT1_RX" |
| 34 | default 9 |
| 35 | config IRQ_SPORT1_TX |
| 36 | int "IRQ_SPORT1_TX" |
| 37 | default 9 |
| 38 | config IRQ_TWI |
| 39 | int "IRQ_TWI" |
| 40 | default 10 |
| 41 | config IRQ_SPI |
| 42 | int "IRQ_SPI" |
| 43 | default 10 |
| 44 | config IRQ_UART0_RX |
| 45 | int "IRQ_UART0_RX" |
| 46 | default 10 |
| 47 | config IRQ_UART0_TX |
| 48 | int "IRQ_UART0_TX" |
| 49 | default 10 |
| 50 | config IRQ_UART1_RX |
| 51 | int "IRQ_UART1_RX" |
| 52 | default 10 |
| 53 | config IRQ_UART1_TX |
| 54 | int "IRQ_UART1_TX" |
| 55 | default 10 |
| 56 | config IRQ_CAN_RX |
| 57 | int "IRQ_CAN_RX" |
| 58 | default 11 |
| 59 | config IRQ_CAN_TX |
| 60 | int "IRQ_CAN_TX" |
| 61 | default 11 |
| 62 | config IRQ_MAC_RX |
| 63 | int "IRQ_MAC_RX" |
| 64 | default 11 |
| 65 | config IRQ_MAC_TX |
| 66 | int "IRQ_MAC_TX" |
| 67 | default 11 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 68 | config IRQ_TIMER0 |
| 69 | int "IRQ_TIMER0" |
| Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 70 | default 7 if TICKSOURCE_GPTMR0 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 71 | default 8 |
| 72 | config IRQ_TIMER1 |
| 73 | int "IRQ_TIMER1" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 74 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 75 | config IRQ_TIMER2 |
| 76 | int "IRQ_TIMER2" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 77 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 78 | config IRQ_TIMER3 |
| 79 | int "IRQ_TIMER3" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 80 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 81 | config IRQ_TIMER4 |
| 82 | int "IRQ_TIMER4" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 83 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 84 | config IRQ_TIMER5 |
| 85 | int "IRQ_TIMER5" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 86 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 87 | config IRQ_TIMER6 |
| 88 | int "IRQ_TIMER6" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 89 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 90 | config IRQ_TIMER7 |
| 91 | int "IRQ_TIMER7" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 92 | default 12 |
| 93 | config IRQ_PROG_INTA |
| 94 | int "IRQ_PROG_INTA" |
| 95 | default 12 |
| 96 | config IRQ_PORTG_INTB |
| 97 | int "IRQ_PORTG_INTB" |
| 98 | default 12 |
| 99 | config IRQ_MEM_DMA0 |
| 100 | int "IRQ_MEM_DMA0" |
| 101 | default 13 |
| 102 | config IRQ_MEM_DMA1 |
| 103 | int "IRQ_MEM_DMA1" |
| 104 | default 13 |
| 105 | config IRQ_WATCH |
| 106 | int "IRQ_WATCH" |
| 107 | default 13 |
| 108 | |
| 109 | help |
| 110 | Enter the priority numbers between 7-13 ONLY. Others are Reserved. |
| 111 | This applies to all the above. It is not recommended to assign the |
| 112 | highest priority number 7 to UART or any other device. |
| 113 | |
| 114 | endmenu |
| 115 | |
| 116 | endmenu |
| 117 | |
| 118 | endif |