Dinh Nguyen | b3ca988 | 2018-11-13 12:50:48 -0600 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2018, Intel Corporation |
| 4 | * Copied from reset-sunxi.c |
| 5 | */ |
| 6 | |
| 7 | #include <linux/err.h> |
| 8 | #include <linux/io.h> |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/of.h> |
| 11 | #include <linux/of_address.h> |
| 12 | #include <linux/platform_device.h> |
| 13 | #include <linux/reset-controller.h> |
Philipp Zabel | cdbeb31 | 2018-12-13 12:24:36 +0100 | [diff] [blame] | 14 | #include <linux/reset/socfpga.h> |
Dinh Nguyen | b3ca988 | 2018-11-13 12:50:48 -0600 | [diff] [blame] | 15 | #include <linux/slab.h> |
| 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/types.h> |
| 18 | |
| 19 | #include "reset-simple.h" |
| 20 | |
| 21 | #define SOCFPGA_NR_BANKS 8 |
Dinh Nguyen | b3ca988 | 2018-11-13 12:50:48 -0600 | [diff] [blame] | 22 | |
| 23 | static int a10_reset_init(struct device_node *np) |
| 24 | { |
| 25 | struct reset_simple_data *data; |
| 26 | struct resource res; |
| 27 | resource_size_t size; |
| 28 | int ret; |
| 29 | u32 reg_offset = 0x10; |
| 30 | |
| 31 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
| 32 | if (!data) |
| 33 | return -ENOMEM; |
| 34 | |
| 35 | ret = of_address_to_resource(np, 0, &res); |
| 36 | if (ret) |
| 37 | goto err_alloc; |
| 38 | |
| 39 | size = resource_size(&res); |
| 40 | if (!request_mem_region(res.start, size, np->name)) { |
| 41 | ret = -EBUSY; |
| 42 | goto err_alloc; |
| 43 | } |
| 44 | |
| 45 | data->membase = ioremap(res.start, size); |
| 46 | if (!data->membase) { |
| 47 | ret = -ENOMEM; |
| 48 | goto err_alloc; |
| 49 | } |
| 50 | |
| 51 | if (of_property_read_u32(np, "altr,modrst-offset", ®_offset)) |
| 52 | pr_warn("missing altr,modrst-offset property, assuming 0x10\n"); |
| 53 | data->membase += reg_offset; |
| 54 | |
| 55 | spin_lock_init(&data->lock); |
| 56 | |
| 57 | data->rcdev.owner = THIS_MODULE; |
| 58 | data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32; |
| 59 | data->rcdev.ops = &reset_simple_ops; |
| 60 | data->rcdev.of_node = np; |
| 61 | data->status_active_low = true; |
| 62 | |
| 63 | return reset_controller_register(&data->rcdev); |
| 64 | |
| 65 | err_alloc: |
| 66 | kfree(data); |
| 67 | return ret; |
| 68 | }; |
| 69 | |
| 70 | /* |
| 71 | * These are the reset controller we need to initialize early on in |
| 72 | * our system, before we can even think of using a regular device |
| 73 | * driver for it. |
| 74 | * The controllers that we can register through the regular device |
| 75 | * model are handled by the simple reset driver directly. |
| 76 | */ |
| 77 | static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = { |
| 78 | { .compatible = "altr,rst-mgr", }, |
| 79 | { /* sentinel */ }, |
| 80 | }; |
| 81 | |
| 82 | void __init socfpga_reset_init(void) |
| 83 | { |
| 84 | struct device_node *np; |
| 85 | |
| 86 | for_each_matching_node(np, socfpga_early_reset_dt_ids) |
| 87 | a10_reset_init(np); |
| 88 | } |