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Maxime Ripardf72f4b42016-07-20 16:11:36 +02001/*
Quentin Schulz23f75d72017-12-05 15:46:41 +01002 * AXP20x pinctrl and GPIO driver
Maxime Ripardf72f4b42016-07-20 16:11:36 +02003 *
4 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
Quentin Schulz23f75d72017-12-05 15:46:41 +01005 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
Maxime Ripardf72f4b42016-07-20 16:11:36 +02006 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/bitops.h>
14#include <linux/device.h>
15#include <linux/gpio/driver.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/mfd/axp20x.h>
20#include <linux/module.h>
21#include <linux/of.h>
Quentin Schulze1190082017-12-05 15:46:46 +010022#include <linux/of_device.h>
Quentin Schulz23f75d72017-12-05 15:46:41 +010023#include <linux/pinctrl/pinconf-generic.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
Maxime Ripardf72f4b42016-07-20 16:11:36 +020026#include <linux/platform_device.h>
27#include <linux/regmap.h>
28#include <linux/slab.h>
29
30#define AXP20X_GPIO_FUNCTIONS 0x7
31#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
32#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
33#define AXP20X_GPIO_FUNCTION_INPUT 2
34
Quentin Schulz23f75d72017-12-05 15:46:41 +010035#define AXP20X_FUNC_GPIO_OUT 0
36#define AXP20X_FUNC_GPIO_IN 1
37#define AXP20X_FUNC_LDO 2
38#define AXP20X_FUNC_ADC 3
39#define AXP20X_FUNCS_NB 4
40
41#define AXP20X_MUX_GPIO_OUT 0
42#define AXP20X_MUX_GPIO_IN BIT(1)
43#define AXP20X_MUX_ADC BIT(2)
44
Quentin Schulze1190082017-12-05 15:46:46 +010045#define AXP813_MUX_ADC (BIT(2) | BIT(0))
46
Quentin Schulz23f75d72017-12-05 15:46:41 +010047struct axp20x_pctrl_desc {
48 const struct pinctrl_pin_desc *pins;
49 unsigned int npins;
50 /* Stores the pins supporting LDO function. Bit offset is pin number. */
51 u8 ldo_mask;
52 /* Stores the pins supporting ADC function. Bit offset is pin number. */
53 u8 adc_mask;
Quentin Schulz48e706f2017-12-05 15:46:44 +010054 u8 gpio_status_offset;
Quentin Schulza0a4b4c2017-12-05 15:46:45 +010055 u8 adc_mux;
Quentin Schulz23f75d72017-12-05 15:46:41 +010056};
57
58struct axp20x_pinctrl_function {
59 const char *name;
60 unsigned int muxval;
61 const char **groups;
62 unsigned int ngroups;
63};
64
Quentin Schulzd242e602017-12-05 15:46:43 +010065struct axp20x_pctl {
Maxime Ripardf72f4b42016-07-20 16:11:36 +020066 struct gpio_chip chip;
67 struct regmap *regmap;
Quentin Schulz23f75d72017-12-05 15:46:41 +010068 struct pinctrl_dev *pctl_dev;
69 struct device *dev;
70 const struct axp20x_pctrl_desc *desc;
71 struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
72};
73
74static const struct pinctrl_pin_desc axp209_pins[] = {
75 PINCTRL_PIN(0, "GPIO0"),
76 PINCTRL_PIN(1, "GPIO1"),
77 PINCTRL_PIN(2, "GPIO2"),
78};
79
Quentin Schulze1190082017-12-05 15:46:46 +010080static const struct pinctrl_pin_desc axp813_pins[] = {
81 PINCTRL_PIN(0, "GPIO0"),
82 PINCTRL_PIN(1, "GPIO1"),
83};
84
Quentin Schulz23f75d72017-12-05 15:46:41 +010085static const struct axp20x_pctrl_desc axp20x_data = {
86 .pins = axp209_pins,
87 .npins = ARRAY_SIZE(axp209_pins),
88 .ldo_mask = BIT(0) | BIT(1),
89 .adc_mask = BIT(0) | BIT(1),
Quentin Schulz48e706f2017-12-05 15:46:44 +010090 .gpio_status_offset = 4,
Quentin Schulza0a4b4c2017-12-05 15:46:45 +010091 .adc_mux = AXP20X_MUX_ADC,
Maxime Ripardf72f4b42016-07-20 16:11:36 +020092};
93
Quentin Schulze1190082017-12-05 15:46:46 +010094static const struct axp20x_pctrl_desc axp813_data = {
95 .pins = axp813_pins,
96 .npins = ARRAY_SIZE(axp813_pins),
97 .ldo_mask = BIT(0) | BIT(1),
98 .adc_mask = BIT(0),
99 .gpio_status_offset = 0,
100 .adc_mux = AXP813_MUX_ADC,
101};
102
Quentin Schulz3cac9912017-12-05 15:46:39 +0100103static int axp20x_gpio_get_reg(unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200104{
105 switch (offset) {
106 case 0:
107 return AXP20X_GPIO0_CTRL;
108 case 1:
109 return AXP20X_GPIO1_CTRL;
110 case 2:
111 return AXP20X_GPIO2_CTRL;
112 }
113
114 return -EINVAL;
115}
116
Quentin Schulz3cac9912017-12-05 15:46:39 +0100117static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200118{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100119 return pinctrl_gpio_direction_input(chip->base + offset);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200120}
121
Quentin Schulz3cac9912017-12-05 15:46:39 +0100122static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200123{
Quentin Schulzd242e602017-12-05 15:46:43 +0100124 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200125 unsigned int val;
Quentin Schulz1d2b2ac2016-11-23 15:11:50 +0100126 int ret;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200127
Quentin Schulzd242e602017-12-05 15:46:43 +0100128 ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200129 if (ret)
130 return ret;
131
Quentin Schulz48e706f2017-12-05 15:46:44 +0100132 return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200133}
134
Quentin Schulz3cac9912017-12-05 15:46:39 +0100135static int axp20x_gpio_get_direction(struct gpio_chip *chip,
136 unsigned int offset)
Maxime Ripard81d37532016-09-21 23:51:22 +0300137{
Quentin Schulzd242e602017-12-05 15:46:43 +0100138 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripard81d37532016-09-21 23:51:22 +0300139 unsigned int val;
140 int reg, ret;
141
142 reg = axp20x_gpio_get_reg(offset);
143 if (reg < 0)
144 return reg;
145
Quentin Schulzd242e602017-12-05 15:46:43 +0100146 ret = regmap_read(pctl->regmap, reg, &val);
Maxime Ripard81d37532016-09-21 23:51:22 +0300147 if (ret)
148 return ret;
149
150 /*
151 * This shouldn't really happen if the pin is in use already,
152 * or if it's not in use yet, it doesn't matter since we're
153 * going to change the value soon anyway. Default to output.
154 */
155 if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
156 return 0;
157
158 /*
159 * The GPIO directions are the three lowest values.
160 * 2 is input, 0 and 1 are output
161 */
162 return val & 2;
163}
164
Quentin Schulz3cac9912017-12-05 15:46:39 +0100165static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200166 int value)
167{
Quentin Schulz23f75d72017-12-05 15:46:41 +0100168 chip->set(chip, offset, value);
169
170 return 0;
171}
172
173static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
174 int value)
175{
Quentin Schulzd242e602017-12-05 15:46:43 +0100176 struct axp20x_pctl *pctl = gpiochip_get_data(chip);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200177 int reg;
178
179 reg = axp20x_gpio_get_reg(offset);
180 if (reg < 0)
Quentin Schulz23f75d72017-12-05 15:46:41 +0100181 return;
182
Quentin Schulzd242e602017-12-05 15:46:43 +0100183 regmap_update_bits(pctl->regmap, reg,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100184 AXP20X_GPIO_FUNCTIONS,
185 value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
186 AXP20X_GPIO_FUNCTION_OUT_LOW);
187}
188
189static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
190 u8 config)
191{
Quentin Schulzd242e602017-12-05 15:46:43 +0100192 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100193 int reg;
194
195 reg = axp20x_gpio_get_reg(offset);
196 if (reg < 0)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200197 return reg;
198
Quentin Schulzd242e602017-12-05 15:46:43 +0100199 return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100200 config);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200201}
202
Quentin Schulz23f75d72017-12-05 15:46:41 +0100203static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200204{
Quentin Schulzd242e602017-12-05 15:46:43 +0100205 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100206
Quentin Schulzd242e602017-12-05 15:46:43 +0100207 return ARRAY_SIZE(pctl->funcs);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100208}
209
210static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
211 unsigned int selector)
212{
Quentin Schulzd242e602017-12-05 15:46:43 +0100213 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100214
Quentin Schulzd242e602017-12-05 15:46:43 +0100215 return pctl->funcs[selector].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100216}
217
218static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
219 unsigned int selector,
220 const char * const **groups,
221 unsigned int *num_groups)
222{
Quentin Schulzd242e602017-12-05 15:46:43 +0100223 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100224
Quentin Schulzd242e602017-12-05 15:46:43 +0100225 *groups = pctl->funcs[selector].groups;
226 *num_groups = pctl->funcs[selector].ngroups;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100227
228 return 0;
229}
230
231static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
232 unsigned int function, unsigned int group)
233{
Quentin Schulzd242e602017-12-05 15:46:43 +0100234 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100235 unsigned int mask;
236
237 /* Every pin supports GPIO_OUT and GPIO_IN functions */
238 if (function <= AXP20X_FUNC_GPIO_IN)
239 return axp20x_pmx_set(pctldev, group,
Quentin Schulzd242e602017-12-05 15:46:43 +0100240 pctl->funcs[function].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100241
242 if (function == AXP20X_FUNC_LDO)
Quentin Schulzd242e602017-12-05 15:46:43 +0100243 mask = pctl->desc->ldo_mask;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100244 else
Quentin Schulzd242e602017-12-05 15:46:43 +0100245 mask = pctl->desc->adc_mask;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100246
247 if (!(BIT(group) & mask))
248 return -EINVAL;
249
250 /*
251 * We let the regulator framework handle the LDO muxing as muxing bits
252 * are basically also regulators on/off bits. It's better not to enforce
253 * any state of the regulator when selecting LDO mux so that we don't
254 * interfere with the regulator driver.
255 */
256 if (function == AXP20X_FUNC_LDO)
257 return 0;
258
Quentin Schulzd242e602017-12-05 15:46:43 +0100259 return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100260}
261
262static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
263 struct pinctrl_gpio_range *range,
264 unsigned int offset, bool input)
265{
Quentin Schulzd242e602017-12-05 15:46:43 +0100266 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100267
268 if (input)
269 return axp20x_pmx_set(pctldev, offset,
Quentin Schulzd242e602017-12-05 15:46:43 +0100270 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100271
272 return axp20x_pmx_set(pctldev, offset,
Quentin Schulzd242e602017-12-05 15:46:43 +0100273 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100274}
275
276static const struct pinmux_ops axp20x_pmx_ops = {
277 .get_functions_count = axp20x_pmx_func_cnt,
278 .get_function_name = axp20x_pmx_func_name,
279 .get_function_groups = axp20x_pmx_func_groups,
280 .set_mux = axp20x_pmx_set_mux,
281 .gpio_set_direction = axp20x_pmx_gpio_set_direction,
282 .strict = true,
283};
284
285static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
286{
Quentin Schulzd242e602017-12-05 15:46:43 +0100287 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100288
Quentin Schulzd242e602017-12-05 15:46:43 +0100289 return pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100290}
291
292static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
293 const unsigned int **pins, unsigned int *num_pins)
294{
Quentin Schulzd242e602017-12-05 15:46:43 +0100295 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100296
Quentin Schulzd242e602017-12-05 15:46:43 +0100297 *pins = (unsigned int *)&pctl->desc->pins[selector];
Quentin Schulz23f75d72017-12-05 15:46:41 +0100298 *num_pins = 1;
299
300 return 0;
301}
302
303static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
304 unsigned int selector)
305{
Quentin Schulzd242e602017-12-05 15:46:43 +0100306 struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100307
Quentin Schulzd242e602017-12-05 15:46:43 +0100308 return pctl->desc->pins[selector].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100309}
310
311static const struct pinctrl_ops axp20x_pctrl_ops = {
312 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
313 .dt_free_map = pinconf_generic_dt_free_map,
314 .get_groups_count = axp20x_groups_cnt,
315 .get_group_name = axp20x_group_name,
316 .get_group_pins = axp20x_group_pins,
317};
318
Anton Vasilyev504c7692018-08-06 19:06:35 +0300319static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
Quentin Schulz23f75d72017-12-05 15:46:41 +0100320 unsigned int mask_len,
321 struct axp20x_pinctrl_function *func,
322 const struct pinctrl_pin_desc *pins)
323{
324 unsigned long int mask_cpy = mask;
325 const char **group;
326 unsigned int ngroups = hweight8(mask);
327 int bit;
328
329 func->ngroups = ngroups;
330 if (func->ngroups > 0) {
Kees Cooka86854d2018-06-12 14:07:58 -0700331 func->groups = devm_kcalloc(dev,
332 ngroups, sizeof(const char *),
Quentin Schulz23f75d72017-12-05 15:46:41 +0100333 GFP_KERNEL);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300334 if (!func->groups)
335 return -ENOMEM;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100336 group = func->groups;
337 for_each_set_bit(bit, &mask_cpy, mask_len) {
338 *group = pins[bit].name;
339 group++;
340 }
341 }
Anton Vasilyev504c7692018-08-06 19:06:35 +0300342
343 return 0;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100344}
345
Anton Vasilyev504c7692018-08-06 19:06:35 +0300346static int axp20x_build_funcs_groups(struct platform_device *pdev)
Quentin Schulz23f75d72017-12-05 15:46:41 +0100347{
Quentin Schulzd242e602017-12-05 15:46:43 +0100348 struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300349 int i, ret, pin, npins = pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100350
Quentin Schulzd242e602017-12-05 15:46:43 +0100351 pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
352 pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
353 pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
354 pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
355 pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
Quentin Schulz23f75d72017-12-05 15:46:41 +0100356 /*
357 * Muxval for LDO is useless as we won't use it.
358 * See comment in axp20x_pmx_set_mux.
359 */
Quentin Schulzd242e602017-12-05 15:46:43 +0100360 pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
Quentin Schulza0a4b4c2017-12-05 15:46:45 +0100361 pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100362
363 /* Every pin supports GPIO_OUT and GPIO_IN functions */
364 for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
Quentin Schulzd242e602017-12-05 15:46:43 +0100365 pctl->funcs[i].ngroups = npins;
Kees Cooka86854d2018-06-12 14:07:58 -0700366 pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
367 npins, sizeof(char *),
Quentin Schulz23f75d72017-12-05 15:46:41 +0100368 GFP_KERNEL);
369 for (pin = 0; pin < npins; pin++)
Quentin Schulzd242e602017-12-05 15:46:43 +0100370 pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100371 }
372
Anton Vasilyev504c7692018-08-06 19:06:35 +0300373 ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
Quentin Schulzd242e602017-12-05 15:46:43 +0100374 npins, &pctl->funcs[AXP20X_FUNC_LDO],
375 pctl->desc->pins);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300376 if (ret)
377 return ret;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100378
Anton Vasilyev504c7692018-08-06 19:06:35 +0300379 ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
Quentin Schulzd242e602017-12-05 15:46:43 +0100380 npins, &pctl->funcs[AXP20X_FUNC_ADC],
381 pctl->desc->pins);
Anton Vasilyev504c7692018-08-06 19:06:35 +0300382 if (ret)
383 return ret;
384
385 return 0;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200386}
387
Quentin Schulze1190082017-12-05 15:46:46 +0100388static const struct of_device_id axp20x_pctl_match[] = {
389 { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
390 { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
391 { }
392};
393MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
394
Quentin Schulzd242e602017-12-05 15:46:43 +0100395static int axp20x_pctl_probe(struct platform_device *pdev)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200396{
397 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
Quentin Schulzd242e602017-12-05 15:46:43 +0100398 struct axp20x_pctl *pctl;
Quentin Schulze1190082017-12-05 15:46:46 +0100399 struct device *dev = &pdev->dev;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100400 struct pinctrl_desc *pctrl_desc;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200401 int ret;
402
403 if (!of_device_is_available(pdev->dev.of_node))
404 return -ENODEV;
405
406 if (!axp20x) {
407 dev_err(&pdev->dev, "Parent drvdata not set\n");
408 return -EINVAL;
409 }
410
Quentin Schulzd242e602017-12-05 15:46:43 +0100411 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
412 if (!pctl)
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200413 return -ENOMEM;
414
Quentin Schulzd242e602017-12-05 15:46:43 +0100415 pctl->chip.base = -1;
416 pctl->chip.can_sleep = true;
417 pctl->chip.request = gpiochip_generic_request;
418 pctl->chip.free = gpiochip_generic_free;
419 pctl->chip.parent = &pdev->dev;
420 pctl->chip.label = dev_name(&pdev->dev);
421 pctl->chip.owner = THIS_MODULE;
422 pctl->chip.get = axp20x_gpio_get;
423 pctl->chip.get_direction = axp20x_gpio_get_direction;
424 pctl->chip.set = axp20x_gpio_set;
425 pctl->chip.direction_input = axp20x_gpio_input;
426 pctl->chip.direction_output = axp20x_gpio_output;
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200427
Julia Lawall9b8ee3c2018-01-02 14:28:04 +0100428 pctl->desc = of_device_get_match_data(dev);
Quentin Schulza0498152017-12-13 09:55:03 +0100429
430 pctl->chip.ngpio = pctl->desc->npins;
431
Quentin Schulzd242e602017-12-05 15:46:43 +0100432 pctl->regmap = axp20x->regmap;
433 pctl->dev = &pdev->dev;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100434
Quentin Schulzd242e602017-12-05 15:46:43 +0100435 platform_set_drvdata(pdev, pctl);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100436
Anton Vasilyev504c7692018-08-06 19:06:35 +0300437 ret = axp20x_build_funcs_groups(pdev);
438 if (ret) {
439 dev_err(&pdev->dev, "failed to build groups\n");
440 return ret;
441 }
Quentin Schulz23f75d72017-12-05 15:46:41 +0100442
443 pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
444 if (!pctrl_desc)
445 return -ENOMEM;
446
447 pctrl_desc->name = dev_name(&pdev->dev);
448 pctrl_desc->owner = THIS_MODULE;
Quentin Schulzd242e602017-12-05 15:46:43 +0100449 pctrl_desc->pins = pctl->desc->pins;
450 pctrl_desc->npins = pctl->desc->npins;
Quentin Schulz23f75d72017-12-05 15:46:41 +0100451 pctrl_desc->pctlops = &axp20x_pctrl_ops;
452 pctrl_desc->pmxops = &axp20x_pmx_ops;
453
Quentin Schulzd242e602017-12-05 15:46:43 +0100454 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
455 if (IS_ERR(pctl->pctl_dev)) {
Quentin Schulz23f75d72017-12-05 15:46:41 +0100456 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
Quentin Schulzd242e602017-12-05 15:46:43 +0100457 return PTR_ERR(pctl->pctl_dev);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100458 }
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200459
Quentin Schulzd242e602017-12-05 15:46:43 +0100460 ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200461 if (ret) {
462 dev_err(&pdev->dev, "Failed to register GPIO chip\n");
463 return ret;
464 }
465
Quentin Schulzd242e602017-12-05 15:46:43 +0100466 ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
467 pctl->desc->pins->number,
468 pctl->desc->pins->number,
469 pctl->desc->npins);
Quentin Schulz23f75d72017-12-05 15:46:41 +0100470 if (ret) {
471 dev_err(&pdev->dev, "failed to add pin range\n");
472 return ret;
473 }
474
475 dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200476
477 return 0;
478}
479
Quentin Schulzd242e602017-12-05 15:46:43 +0100480static struct platform_driver axp20x_pctl_driver = {
481 .probe = axp20x_pctl_probe,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200482 .driver = {
483 .name = "axp20x-gpio",
Quentin Schulzd242e602017-12-05 15:46:43 +0100484 .of_match_table = axp20x_pctl_match,
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200485 },
486};
487
Quentin Schulzd242e602017-12-05 15:46:43 +0100488module_platform_driver(axp20x_pctl_driver);
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200489
490MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
Quentin Schulz23f75d72017-12-05 15:46:41 +0100491MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
492MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
Maxime Ripardf72f4b42016-07-20 16:11:36 +0200493MODULE_LICENSE("GPL");