Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h |
| 3 | * based on: |
| 4 | * author: |
| 5 | * |
| 6 | * created: |
| 7 | * description: |
| 8 | * blackfin serial driver head file |
| 9 | * rev: |
| 10 | * |
| 11 | * modified: |
| 12 | * |
| 13 | * |
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ |
| 15 | * |
| 16 | * this program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the gnu general public license as published by |
| 18 | * the free software foundation; either version 2, or (at your option) |
| 19 | * any later version. |
| 20 | * |
| 21 | * this program is distributed in the hope that it will be useful, |
| 22 | * but without any warranty; without even the implied warranty of |
| 23 | * merchantability or fitness for a particular purpose. see the |
| 24 | * gnu general public license for more details. |
| 25 | * |
| 26 | * you should have received a copy of the gnu general public license |
| 27 | * along with this program; see the file copying. |
| 28 | * if not, write to the free software foundation, |
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. |
| 30 | */ |
| 31 | |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 32 | #include <linux/serial.h> |
| 33 | #include <asm/dma.h> |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 34 | #include <asm/portmux.h> |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 35 | |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 36 | #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) |
| 37 | #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 38 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 39 | #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET)) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 40 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) |
| 41 | #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) |
| 42 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) |
Sonic Zhang | db28838 | 2008-02-02 17:05:02 +0800 | [diff] [blame] | 43 | #define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR)) |
| 44 | #define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR)) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 45 | |
| 46 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) |
| 47 | #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 48 | #define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v) |
| 49 | #define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 50 | #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 51 | #define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 52 | #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) |
Mike Frysinger | 0bcfd70 | 2007-12-24 19:40:05 +0800 | [diff] [blame] | 53 | #define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 54 | #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) |
Sonic Zhang | db28838 | 2008-02-02 17:05:02 +0800 | [diff] [blame] | 55 | #define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 56 | |
Mike Frysinger | 45828b8 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 57 | #define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ |
| 58 | #define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ |
| 59 | |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 60 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) |
| 61 | # define CONFIG_SERIAL_BFIN_CTSRTS |
| 62 | |
| 63 | # ifndef CONFIG_UART0_CTS_PIN |
| 64 | # define CONFIG_UART0_CTS_PIN -1 |
| 65 | # endif |
| 66 | |
| 67 | # ifndef CONFIG_UART0_RTS_PIN |
| 68 | # define CONFIG_UART0_RTS_PIN -1 |
| 69 | # endif |
| 70 | |
| 71 | # ifndef CONFIG_UART1_CTS_PIN |
| 72 | # define CONFIG_UART1_CTS_PIN -1 |
| 73 | # endif |
| 74 | |
| 75 | # ifndef CONFIG_UART1_RTS_PIN |
| 76 | # define CONFIG_UART1_RTS_PIN -1 |
| 77 | # endif |
| 78 | #endif |
| 79 | /* |
| 80 | * The pin configuration is different from schematic |
| 81 | */ |
| 82 | struct bfin_serial_port { |
| 83 | struct uart_port port; |
| 84 | unsigned int old_status; |
| 85 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 86 | int tx_done; |
| 87 | int tx_count; |
| 88 | struct circ_buf rx_dma_buf; |
| 89 | struct timer_list rx_dma_timer; |
| 90 | int rx_dma_nrows; |
| 91 | unsigned int tx_dma_channel; |
| 92 | unsigned int rx_dma_channel; |
| 93 | struct work_struct tx_dma_workqueue; |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 94 | #endif |
| 95 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
Sonic Zhang | 4cb4f22 | 2008-02-02 14:29:25 +0800 | [diff] [blame] | 96 | struct work_struct cts_workqueue; |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 97 | int cts_pin; |
| 98 | int rts_pin; |
| 99 | #endif |
| 100 | }; |
| 101 | |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 102 | struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 103 | struct bfin_serial_res { |
| 104 | unsigned long uart_base_addr; |
| 105 | int uart_irq; |
| 106 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 107 | unsigned int uart_tx_dma_channel; |
| 108 | unsigned int uart_rx_dma_channel; |
| 109 | #endif |
| 110 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 111 | int uart_cts_pin; |
| 112 | int uart_rts_pin; |
| 113 | #endif |
| 114 | }; |
| 115 | |
| 116 | struct bfin_serial_res bfin_serial_resource[] = { |
| 117 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
| 118 | { |
| 119 | 0xFFC00400, |
| 120 | IRQ_UART0_RX, |
| 121 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 122 | CH_UART0_TX, |
| 123 | CH_UART0_RX, |
| 124 | #endif |
| 125 | #ifdef CONFIG_BFIN_UART0_CTSRTS |
| 126 | CONFIG_UART0_CTS_PIN, |
| 127 | CONFIG_UART0_RTS_PIN, |
| 128 | #endif |
| 129 | }, |
| 130 | #endif |
| 131 | #ifdef CONFIG_SERIAL_BFIN_UART1 |
| 132 | { |
| 133 | 0xFFC02000, |
| 134 | IRQ_UART1_RX, |
| 135 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 136 | CH_UART1_TX, |
| 137 | CH_UART1_RX, |
| 138 | #endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 139 | }, |
| 140 | #endif |
| 141 | #ifdef CONFIG_SERIAL_BFIN_UART2 |
| 142 | { |
| 143 | 0xFFC02100, |
| 144 | IRQ_UART2_RX, |
| 145 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 146 | CH_UART2_TX, |
| 147 | CH_UART2_RX, |
| 148 | #endif |
| 149 | #ifdef CONFIG_BFIN_UART2_CTSRTS |
| 150 | CONFIG_UART2_CTS_PIN, |
| 151 | CONFIG_UART2_RTS_PIN, |
| 152 | #endif |
| 153 | }, |
| 154 | #endif |
| 155 | #ifdef CONFIG_SERIAL_BFIN_UART3 |
| 156 | { |
| 157 | 0xFFC03100, |
| 158 | IRQ_UART3_RX, |
| 159 | #ifdef CONFIG_SERIAL_BFIN_DMA |
| 160 | CH_UART3_TX, |
| 161 | CH_UART3_RX, |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 162 | #endif |
| 163 | }, |
| 164 | #endif |
| 165 | }; |
| 166 | |
| 167 | int nr_ports = ARRAY_SIZE(bfin_serial_resource); |
| 168 | |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 169 | #define DRIVER_NAME "bfin-uart" |
| 170 | |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 171 | static void bfin_serial_hw_init(struct bfin_serial_port *uart) |
| 172 | { |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 173 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 174 | peripheral_request(P_UART0_TX, DRIVER_NAME); |
| 175 | peripheral_request(P_UART0_RX, DRIVER_NAME); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 176 | #endif |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 177 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 178 | #ifdef CONFIG_SERIAL_BFIN_UART1 |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 179 | peripheral_request(P_UART1_TX, DRIVER_NAME); |
| 180 | peripheral_request(P_UART1_RX, DRIVER_NAME); |
| 181 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 182 | #ifdef CONFIG_BFIN_UART1_CTSRTS |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 183 | peripheral_request(P_UART1_RTS, DRIVER_NAME); |
| 184 | peripheral_request(P_UART1_CTS DRIVER_NAME); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 185 | #endif |
| 186 | #endif |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 187 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 188 | #ifdef CONFIG_SERIAL_BFIN_UART2 |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 189 | peripheral_request(P_UART2_TX, DRIVER_NAME); |
| 190 | peripheral_request(P_UART2_RX, DRIVER_NAME); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 191 | #endif |
| 192 | |
| 193 | #ifdef CONFIG_SERIAL_BFIN_UART3 |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 194 | peripheral_request(P_UART3_TX, DRIVER_NAME); |
| 195 | peripheral_request(P_UART3_RX, DRIVER_NAME); |
| 196 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 197 | #ifdef CONFIG_BFIN_UART3_CTSRTS |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 198 | peripheral_request(P_UART3_RTS, DRIVER_NAME); |
| 199 | peripheral_request(P_UART3_CTS DRIVER_NAME); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 200 | #endif |
| 201 | #endif |
| 202 | SSYNC(); |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 203 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 204 | if (uart->cts_pin >= 0) { |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 205 | gpio_request(uart->cts_pin, DRIVER_NAME); |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 206 | gpio_direction_input(uart->cts_pin); |
| 207 | } |
| 208 | |
| 209 | if (uart->rts_pin >= 0) { |
Michael Hennerich | b99ab54 | 2007-10-11 10:57:54 +0800 | [diff] [blame] | 210 | gpio_request(uart->rts_pin, DRIVER_NAME); |
Michael Hennerich | acbcd26 | 2008-01-22 18:36:20 +0800 | [diff] [blame] | 211 | gpio_direction_output(uart->rts_pin, 0); |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 212 | } |
| 213 | #endif |
| 214 | } |