blob: 6d9b6906b9d01b6570866e8ee4ab12da3efbc115 [file] [log] [blame]
Erik Gilling3c92db92010-03-15 19:40:06 -07001/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
Linus Walleij11da9052019-02-19 21:32:02 +01005 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
Erik Gilling3c92db92010-03-15 19:40:06 -07006 *
7 * Author:
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
Thierry Reding641d0342013-01-21 11:09:01 +010021#include <linux/err.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070022#include <linux/init.h>
23#include <linux/irq.h>
Colin Cross2e47b8b2010-04-07 12:59:42 -070024#include <linux/interrupt.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070025#include <linux/io.h>
Linus Walleij21041da2018-08-06 17:38:33 +020026#include <linux/gpio/driver.h>
Stephen Warren5c1e2c92012-03-16 17:35:08 -060027#include <linux/of_device.h>
Stephen Warren88d89512011-10-11 16:16:14 -060028#include <linux/platform_device.h>
29#include <linux/module.h>
Stephen Warren6f74dc92012-01-04 08:39:37 +000030#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000031#include <linux/irqchip/chained_irq.h>
Stephen Warren3e215d02012-02-18 01:04:55 -070032#include <linux/pinctrl/consumer.h>
Laxman Dewangan8939ddc2012-11-07 20:31:32 +053033#include <linux/pm.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070034
Erik Gilling3c92db92010-03-15 19:40:06 -070035#define GPIO_BANK(x) ((x) >> 5)
36#define GPIO_PORT(x) (((x) >> 3) & 0x3)
37#define GPIO_BIT(x) ((x) & 0x7)
38
Laxman Dewanganb546be02016-04-25 16:08:33 +053039#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
Stephen Warren5c1e2c92012-03-16 17:35:08 -060040 GPIO_PORT(x) * 4)
Erik Gilling3c92db92010-03-15 19:40:06 -070041
Laxman Dewanganb546be02016-04-25 16:08:33 +053042#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
43#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
44#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
45#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
46#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
47#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
48#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
49#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
Laxman Dewangan3737de42016-04-25 16:08:34 +053050#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
51
Erik Gilling3c92db92010-03-15 19:40:06 -070052
Laxman Dewanganb546be02016-04-25 16:08:33 +053053#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
54#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
55#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
Laxman Dewangan3737de42016-04-25 16:08:34 +053056#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
Laxman Dewanganb546be02016-04-25 16:08:33 +053057#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
58#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
59#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
Erik Gilling3c92db92010-03-15 19:40:06 -070060
61#define GPIO_INT_LVL_MASK 0x010101
62#define GPIO_INT_LVL_EDGE_RISING 0x000101
63#define GPIO_INT_LVL_EDGE_FALLING 0x000100
64#define GPIO_INT_LVL_EDGE_BOTH 0x010100
65#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
66#define GPIO_INT_LVL_LEVEL_LOW 0x000000
67
Laxman Dewanganb546be02016-04-25 16:08:33 +053068struct tegra_gpio_info;
69
Erik Gilling3c92db92010-03-15 19:40:06 -070070struct tegra_gpio_bank {
Thierry Reding539b7a32017-07-24 16:55:08 +020071 unsigned int bank;
72 unsigned int irq;
Erik Gilling3c92db92010-03-15 19:40:06 -070073 spinlock_t lvl_lock[4];
Laxman Dewangan3737de42016-04-25 16:08:34 +053074 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
Laxman Dewangan8939ddc2012-11-07 20:31:32 +053075#ifdef CONFIG_PM_SLEEP
Colin Cross2e47b8b2010-04-07 12:59:42 -070076 u32 cnf[4];
77 u32 out[4];
78 u32 oe[4];
79 u32 int_enb[4];
80 u32 int_lvl[4];
Joseph Lo203f31c2013-04-03 19:31:44 +080081 u32 wake_enb[4];
Laxman Dewangan3737de42016-04-25 16:08:34 +053082 u32 dbc_enb[4];
Colin Cross2e47b8b2010-04-07 12:59:42 -070083#endif
Laxman Dewangan3737de42016-04-25 16:08:34 +053084 u32 dbc_cnt[4];
Laxman Dewanganb546be02016-04-25 16:08:33 +053085 struct tegra_gpio_info *tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -070086};
87
Laxman Dewangan171b92c2016-04-25 16:08:31 +053088struct tegra_gpio_soc_config {
Laxman Dewangan3737de42016-04-25 16:08:34 +053089 bool debounce_supported;
Laxman Dewangan171b92c2016-04-25 16:08:31 +053090 u32 bank_stride;
91 u32 upper_offset;
92};
93
Laxman Dewanganb546be02016-04-25 16:08:33 +053094struct tegra_gpio_info {
95 struct device *dev;
96 void __iomem *regs;
97 struct irq_domain *irq_domain;
98 struct tegra_gpio_bank *bank_info;
99 const struct tegra_gpio_soc_config *soc;
100 struct gpio_chip gc;
101 struct irq_chip ic;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530102 u32 bank_count;
103};
Stephen Warren88d89512011-10-11 16:16:14 -0600104
Laxman Dewanganb546be02016-04-25 16:08:33 +0530105static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
106 u32 val, u32 reg)
Stephen Warren88d89512011-10-11 16:16:14 -0600107{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530108 __raw_writel(val, tgi->regs + reg);
Stephen Warren88d89512011-10-11 16:16:14 -0600109}
110
Laxman Dewanganb546be02016-04-25 16:08:33 +0530111static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
Stephen Warren88d89512011-10-11 16:16:14 -0600112{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530113 return __raw_readl(tgi->regs + reg);
Stephen Warren88d89512011-10-11 16:16:14 -0600114}
Erik Gilling3c92db92010-03-15 19:40:06 -0700115
Thierry Reding539b7a32017-07-24 16:55:08 +0200116static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
117 unsigned int bit)
Erik Gilling3c92db92010-03-15 19:40:06 -0700118{
119 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
120}
121
Laxman Dewanganb546be02016-04-25 16:08:33 +0530122static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
Thierry Reding539b7a32017-07-24 16:55:08 +0200123 unsigned int gpio, u32 value)
Erik Gilling3c92db92010-03-15 19:40:06 -0700124{
125 u32 val;
126
127 val = 0x100 << GPIO_BIT(gpio);
128 if (value)
129 val |= 1 << GPIO_BIT(gpio);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530130 tegra_gpio_writel(tgi, val, reg);
Erik Gilling3c92db92010-03-15 19:40:06 -0700131}
132
Thierry Reding539b7a32017-07-24 16:55:08 +0200133static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
Erik Gilling3c92db92010-03-15 19:40:06 -0700134{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530135 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
Erik Gilling3c92db92010-03-15 19:40:06 -0700136}
137
Thierry Reding539b7a32017-07-24 16:55:08 +0200138static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
Erik Gilling3c92db92010-03-15 19:40:06 -0700139{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530140 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
Erik Gilling3c92db92010-03-15 19:40:06 -0700141}
142
Thierry Reding4bc17862017-07-24 16:55:07 +0200143static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
Stephen Warren3e215d02012-02-18 01:04:55 -0700144{
Linus Walleij11da9052019-02-19 21:32:02 +0100145 return pinctrl_gpio_request(chip->base + offset);
Stephen Warren3e215d02012-02-18 01:04:55 -0700146}
147
Thierry Reding4bc17862017-07-24 16:55:07 +0200148static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
Stephen Warren3e215d02012-02-18 01:04:55 -0700149{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530150 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
151
Linus Walleij11da9052019-02-19 21:32:02 +0100152 pinctrl_gpio_free(chip->base + offset);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530153 tegra_gpio_disable(tgi, offset);
Stephen Warren3e215d02012-02-18 01:04:55 -0700154}
155
Thierry Reding4bc17862017-07-24 16:55:07 +0200156static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
157 int value)
Erik Gilling3c92db92010-03-15 19:40:06 -0700158{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530159 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
160
161 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
Erik Gilling3c92db92010-03-15 19:40:06 -0700162}
163
Thierry Reding4bc17862017-07-24 16:55:07 +0200164static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
Erik Gilling3c92db92010-03-15 19:40:06 -0700165{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530166 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Thierry Reding539b7a32017-07-24 16:55:08 +0200167 unsigned int bval = BIT(GPIO_BIT(offset));
Laxman Dewangan195812e2012-11-09 11:34:20 +0530168
Laxman Dewanganb546be02016-04-25 16:08:33 +0530169 /* If gpio is in output mode then read from the out value */
170 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
171 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
172
173 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
Erik Gilling3c92db92010-03-15 19:40:06 -0700174}
175
Thierry Reding4bc17862017-07-24 16:55:07 +0200176static int tegra_gpio_direction_input(struct gpio_chip *chip,
177 unsigned int offset)
Erik Gilling3c92db92010-03-15 19:40:06 -0700178{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530179 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Linus Walleij11da9052019-02-19 21:32:02 +0100180 int ret;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530181
182 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
183 tegra_gpio_enable(tgi, offset);
Linus Walleij11da9052019-02-19 21:32:02 +0100184
185 ret = pinctrl_gpio_direction_input(chip->base + offset);
186 if (ret < 0)
187 dev_err(tgi->dev,
188 "Failed to set pinctrl input direction of GPIO %d: %d",
189 chip->base + offset, ret);
190
191 return ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700192}
193
Thierry Reding4bc17862017-07-24 16:55:07 +0200194static int tegra_gpio_direction_output(struct gpio_chip *chip,
195 unsigned int offset,
196 int value)
Erik Gilling3c92db92010-03-15 19:40:06 -0700197{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530198 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Linus Walleij11da9052019-02-19 21:32:02 +0100199 int ret;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530200
Erik Gilling3c92db92010-03-15 19:40:06 -0700201 tegra_gpio_set(chip, offset, value);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530202 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
203 tegra_gpio_enable(tgi, offset);
Linus Walleij11da9052019-02-19 21:32:02 +0100204
205 ret = pinctrl_gpio_direction_output(chip->base + offset);
206 if (ret < 0)
207 dev_err(tgi->dev,
208 "Failed to set pinctrl output direction of GPIO %d: %d",
209 chip->base + offset, ret);
210
211 return ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700212}
213
Thierry Reding4bc17862017-07-24 16:55:07 +0200214static int tegra_gpio_get_direction(struct gpio_chip *chip,
215 unsigned int offset)
Laxman Dewanganf002d072016-04-29 21:55:23 +0530216{
217 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
218 u32 pin_mask = BIT(GPIO_BIT(offset));
219 u32 cnf, oe;
220
221 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
222 if (!(cnf & pin_mask))
223 return -EINVAL;
224
225 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
226
Linus Walleij21041da2018-08-06 17:38:33 +0200227 return !(oe & pin_mask);
Laxman Dewanganf002d072016-04-29 21:55:23 +0530228}
229
Laxman Dewangan3737de42016-04-25 16:08:34 +0530230static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
231 unsigned int debounce)
232{
233 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
234 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
235 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
236 unsigned long flags;
Thierry Reding539b7a32017-07-24 16:55:08 +0200237 unsigned int port;
Laxman Dewangan3737de42016-04-25 16:08:34 +0530238
239 if (!debounce_ms) {
240 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
241 offset, 0);
242 return 0;
243 }
244
245 debounce_ms = min(debounce_ms, 255U);
246 port = GPIO_PORT(offset);
247
248 /* There is only one debounce count register per port and hence
249 * set the maximum of current and requested debounce time.
250 */
251 spin_lock_irqsave(&bank->dbc_lock[port], flags);
252 if (bank->dbc_cnt[port] < debounce_ms) {
253 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
254 bank->dbc_cnt[port] = debounce_ms;
255 }
256 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
257
258 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
259
260 return 0;
261}
262
Mika Westerberg2956b5d2017-01-23 15:34:34 +0300263static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
264 unsigned long config)
265{
266 u32 debounce;
267
268 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
269 return -ENOTSUPP;
270
271 debounce = pinconf_to_config_argument(config);
272 return tegra_gpio_set_debounce(chip, offset, debounce);
273}
274
Thierry Reding4bc17862017-07-24 16:55:07 +0200275static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
Stephen Warren438a99c2011-08-23 00:39:56 +0100276{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530277 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Erik Gilling3c92db92010-03-15 19:40:06 -0700278
Laxman Dewanganb546be02016-04-25 16:08:33 +0530279 return irq_find_mapping(tgi->irq_domain, offset);
280}
Erik Gilling3c92db92010-03-15 19:40:06 -0700281
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100282static void tegra_gpio_irq_ack(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700283{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530284 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
285 struct tegra_gpio_info *tgi = bank->tgi;
Thierry Reding539b7a32017-07-24 16:55:08 +0200286 unsigned int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700287
Laxman Dewanganb546be02016-04-25 16:08:33 +0530288 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700289}
290
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100291static void tegra_gpio_irq_mask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700292{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530293 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
294 struct tegra_gpio_info *tgi = bank->tgi;
Thierry Reding539b7a32017-07-24 16:55:08 +0200295 unsigned int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700296
Laxman Dewanganb546be02016-04-25 16:08:33 +0530297 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
Erik Gilling3c92db92010-03-15 19:40:06 -0700298}
299
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100300static void tegra_gpio_irq_unmask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700301{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530302 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
303 struct tegra_gpio_info *tgi = bank->tgi;
Thierry Reding539b7a32017-07-24 16:55:08 +0200304 unsigned int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700305
Laxman Dewanganb546be02016-04-25 16:08:33 +0530306 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
Erik Gilling3c92db92010-03-15 19:40:06 -0700307}
308
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100309static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
Erik Gilling3c92db92010-03-15 19:40:06 -0700310{
Thierry Reding539b7a32017-07-24 16:55:08 +0200311 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100312 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530313 struct tegra_gpio_info *tgi = bank->tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -0700314 unsigned long flags;
Thierry Reding539b7a32017-07-24 16:55:08 +0200315 u32 val;
Stephen Warrendf231f22013-10-16 13:25:33 -0600316 int ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700317
318 switch (type & IRQ_TYPE_SENSE_MASK) {
319 case IRQ_TYPE_EDGE_RISING:
320 lvl_type = GPIO_INT_LVL_EDGE_RISING;
321 break;
322
323 case IRQ_TYPE_EDGE_FALLING:
324 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
325 break;
326
327 case IRQ_TYPE_EDGE_BOTH:
328 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
329 break;
330
331 case IRQ_TYPE_LEVEL_HIGH:
332 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
333 break;
334
335 case IRQ_TYPE_LEVEL_LOW:
336 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
337 break;
338
339 default:
340 return -EINVAL;
341 }
342
343 spin_lock_irqsave(&bank->lvl_lock[port], flags);
344
Laxman Dewanganb546be02016-04-25 16:08:33 +0530345 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700346 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
347 val |= lvl_type << GPIO_BIT(gpio);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530348 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700349
350 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
351
Laxman Dewanganb546be02016-04-25 16:08:33 +0530352 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
353 tegra_gpio_enable(tgi, gpio);
Stephen Warrend9411362012-03-19 10:31:58 -0600354
Dmitry Osipenkof78709a2018-07-17 19:10:38 +0300355 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
356 if (ret) {
357 dev_err(tgi->dev,
358 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
359 tegra_gpio_disable(tgi, gpio);
360 return ret;
361 }
362
Erik Gilling3c92db92010-03-15 19:40:06 -0700363 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixnerf170d712015-06-23 15:52:40 +0200364 irq_set_handler_locked(d, handle_level_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700365 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixnerf170d712015-06-23 15:52:40 +0200366 irq_set_handler_locked(d, handle_edge_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700367
368 return 0;
369}
370
Stephen Warrendf231f22013-10-16 13:25:33 -0600371static void tegra_gpio_irq_shutdown(struct irq_data *d)
372{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530373 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
374 struct tegra_gpio_info *tgi = bank->tgi;
Thierry Reding539b7a32017-07-24 16:55:08 +0200375 unsigned int gpio = d->hwirq;
Stephen Warrendf231f22013-10-16 13:25:33 -0600376
Laxman Dewanganb546be02016-04-25 16:08:33 +0530377 gpiochip_unlock_as_irq(&tgi->gc, gpio);
Stephen Warrendf231f22013-10-16 13:25:33 -0600378}
379
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200380static void tegra_gpio_irq_handler(struct irq_desc *desc)
Erik Gilling3c92db92010-03-15 19:40:06 -0700381{
Thierry Reding539b7a32017-07-24 16:55:08 +0200382 unsigned int port, pin, gpio;
Michał Mirosław9e9509e2017-07-18 14:35:45 +0200383 bool unmasked = false;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530384 u32 lvl;
385 unsigned long sta;
Will Deacon98022942011-02-21 13:58:10 +0000386 struct irq_chip *chip = irq_desc_get_chip(desc);
Jiang Liu476f8b42015-06-04 12:13:15 +0800387 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530388 struct tegra_gpio_info *tgi = bank->tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -0700389
Will Deacon98022942011-02-21 13:58:10 +0000390 chained_irq_enter(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700391
Erik Gilling3c92db92010-03-15 19:40:06 -0700392 for (port = 0; port < 4; port++) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530393 gpio = tegra_gpio_compose(bank->bank, port, 0);
394 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
395 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
396 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700397
398 for_each_set_bit(pin, &sta, 8) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530399 tegra_gpio_writel(tgi, 1 << pin,
400 GPIO_INT_CLR(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700401
402 /* if gpio is edge triggered, clear condition
Colin Cronin20a8a962015-05-18 11:41:43 -0700403 * before executing the handler so that we don't
Erik Gilling3c92db92010-03-15 19:40:06 -0700404 * miss edges
405 */
Michał Mirosław9e9509e2017-07-18 14:35:45 +0200406 if (!unmasked && lvl & (0x100 << pin)) {
407 unmasked = true;
Will Deacon98022942011-02-21 13:58:10 +0000408 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700409 }
410
Grygorii Strashkoc0debb32017-07-08 17:44:11 -0500411 generic_handle_irq(irq_find_mapping(tgi->irq_domain,
412 gpio + pin));
Erik Gilling3c92db92010-03-15 19:40:06 -0700413 }
414 }
415
416 if (!unmasked)
Will Deacon98022942011-02-21 13:58:10 +0000417 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700418
419}
420
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530421#ifdef CONFIG_PM_SLEEP
422static int tegra_gpio_resume(struct device *dev)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700423{
Wolfram Sang7ddb7dc2018-10-21 22:00:00 +0200424 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700425 unsigned long flags;
Thierry Reding539b7a32017-07-24 16:55:08 +0200426 unsigned int b, p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700427
428 local_irq_save(flags);
429
Laxman Dewanganb546be02016-04-25 16:08:33 +0530430 for (b = 0; b < tgi->bank_count; b++) {
431 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
Colin Cross2e47b8b2010-04-07 12:59:42 -0700432
433 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
Thierry Reding4bc17862017-07-24 16:55:07 +0200434 unsigned int gpio = (b << 5) | (p << 3);
435
Laxman Dewanganb546be02016-04-25 16:08:33 +0530436 tegra_gpio_writel(tgi, bank->cnf[p],
437 GPIO_CNF(tgi, gpio));
Laxman Dewangan3737de42016-04-25 16:08:34 +0530438
439 if (tgi->soc->debounce_supported) {
440 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
441 GPIO_DBC_CNT(tgi, gpio));
442 tegra_gpio_writel(tgi, bank->dbc_enb[p],
443 GPIO_MSK_DBC_EN(tgi, gpio));
444 }
445
Laxman Dewanganb546be02016-04-25 16:08:33 +0530446 tegra_gpio_writel(tgi, bank->out[p],
447 GPIO_OUT(tgi, gpio));
448 tegra_gpio_writel(tgi, bank->oe[p],
449 GPIO_OE(tgi, gpio));
450 tegra_gpio_writel(tgi, bank->int_lvl[p],
451 GPIO_INT_LVL(tgi, gpio));
452 tegra_gpio_writel(tgi, bank->int_enb[p],
453 GPIO_INT_ENB(tgi, gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700454 }
455 }
456
457 local_irq_restore(flags);
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530458 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700459}
460
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530461static int tegra_gpio_suspend(struct device *dev)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700462{
Wolfram Sang7ddb7dc2018-10-21 22:00:00 +0200463 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700464 unsigned long flags;
Thierry Reding539b7a32017-07-24 16:55:08 +0200465 unsigned int b, p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700466
Colin Cross2e47b8b2010-04-07 12:59:42 -0700467 local_irq_save(flags);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530468 for (b = 0; b < tgi->bank_count; b++) {
469 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
Colin Cross2e47b8b2010-04-07 12:59:42 -0700470
471 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
Thierry Reding4bc17862017-07-24 16:55:07 +0200472 unsigned int gpio = (b << 5) | (p << 3);
473
Laxman Dewanganb546be02016-04-25 16:08:33 +0530474 bank->cnf[p] = tegra_gpio_readl(tgi,
475 GPIO_CNF(tgi, gpio));
476 bank->out[p] = tegra_gpio_readl(tgi,
477 GPIO_OUT(tgi, gpio));
478 bank->oe[p] = tegra_gpio_readl(tgi,
479 GPIO_OE(tgi, gpio));
Laxman Dewangan3737de42016-04-25 16:08:34 +0530480 if (tgi->soc->debounce_supported) {
481 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
482 GPIO_MSK_DBC_EN(tgi, gpio));
483 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
484 bank->dbc_enb[p];
485 }
486
Laxman Dewanganb546be02016-04-25 16:08:33 +0530487 bank->int_enb[p] = tegra_gpio_readl(tgi,
488 GPIO_INT_ENB(tgi, gpio));
489 bank->int_lvl[p] = tegra_gpio_readl(tgi,
490 GPIO_INT_LVL(tgi, gpio));
Joseph Lo203f31c2013-04-03 19:31:44 +0800491
492 /* Enable gpio irq for wake up source */
Laxman Dewanganb546be02016-04-25 16:08:33 +0530493 tegra_gpio_writel(tgi, bank->wake_enb[p],
494 GPIO_INT_ENB(tgi, gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700495 }
496 }
497 local_irq_restore(flags);
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530498 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700499}
500
Joseph Lo203f31c2013-04-03 19:31:44 +0800501static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700502{
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100503 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Thierry Reding539b7a32017-07-24 16:55:08 +0200504 unsigned int gpio = d->hwirq;
Joseph Lo203f31c2013-04-03 19:31:44 +0800505 u32 port, bit, mask;
506
507 port = GPIO_PORT(gpio);
508 bit = GPIO_BIT(gpio);
509 mask = BIT(bit);
510
511 if (enable)
512 bank->wake_enb[port] |= mask;
513 else
514 bank->wake_enb[port] &= ~mask;
515
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100516 return irq_set_irq_wake(bank->irq, enable);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700517}
518#endif
Erik Gilling3c92db92010-03-15 19:40:06 -0700519
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000520#ifdef CONFIG_DEBUG_FS
521
522#include <linux/debugfs.h>
523#include <linux/seq_file.h>
524
Axel Lin2773eb22018-02-12 22:01:57 +0800525static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000526{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530527 struct tegra_gpio_info *tgi = s->private;
Thierry Reding539b7a32017-07-24 16:55:08 +0200528 unsigned int i, j;
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000529
Laxman Dewanganb546be02016-04-25 16:08:33 +0530530 for (i = 0; i < tgi->bank_count; i++) {
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000531 for (j = 0; j < 4; j++) {
Thierry Reding539b7a32017-07-24 16:55:08 +0200532 unsigned int gpio = tegra_gpio_compose(i, j, 0);
Thierry Reding4bc17862017-07-24 16:55:07 +0200533
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000534 seq_printf(s,
Thierry Reding539b7a32017-07-24 16:55:08 +0200535 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000536 i, j,
Laxman Dewanganb546be02016-04-25 16:08:33 +0530537 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
538 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
539 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
540 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
541 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
542 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
543 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000544 }
545 }
546 return 0;
547}
548
Axel Lin2773eb22018-02-12 22:01:57 +0800549DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000550
Laxman Dewanganb546be02016-04-25 16:08:33 +0530551static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000552{
Thierry Reding4bc17862017-07-24 16:55:07 +0200553 (void) debugfs_create_file("tegra_gpio", 0444,
Axel Lin2773eb22018-02-12 22:01:57 +0800554 NULL, tgi, &tegra_dbg_gpio_fops);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000555}
556
557#else
558
Laxman Dewanganb546be02016-04-25 16:08:33 +0530559static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000560{
561}
562
563#endif
564
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530565static const struct dev_pm_ops tegra_gpio_pm_ops = {
566 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
567};
568
Bill Pemberton38363092012-11-19 13:22:34 -0500569static int tegra_gpio_probe(struct platform_device *pdev)
Erik Gilling3c92db92010-03-15 19:40:06 -0700570{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530571 struct tegra_gpio_info *tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -0700572 struct tegra_gpio_bank *bank;
Thierry Reding539b7a32017-07-24 16:55:08 +0200573 unsigned int gpio, i, j;
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700574 int ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700575
Laxman Dewanganb546be02016-04-25 16:08:33 +0530576 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
577 if (!tgi)
578 return -ENODEV;
579
Thierry Reding20133bd2017-07-24 16:55:05 +0200580 tgi->soc = of_device_get_match_data(&pdev->dev);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530581 tgi->dev = &pdev->dev;
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600582
Thierry Reding56420902017-07-20 18:00:56 +0200583 ret = platform_irq_count(pdev);
584 if (ret < 0)
585 return ret;
586
587 tgi->bank_count = ret;
588
Laxman Dewanganb546be02016-04-25 16:08:33 +0530589 if (!tgi->bank_count) {
Stephen Warren33918112012-01-19 08:16:35 +0000590 dev_err(&pdev->dev, "Missing IRQ resource\n");
591 return -ENODEV;
592 }
593
Laxman Dewanganb546be02016-04-25 16:08:33 +0530594 tgi->gc.label = "tegra-gpio";
595 tgi->gc.request = tegra_gpio_request;
596 tgi->gc.free = tegra_gpio_free;
597 tgi->gc.direction_input = tegra_gpio_direction_input;
598 tgi->gc.get = tegra_gpio_get;
599 tgi->gc.direction_output = tegra_gpio_direction_output;
600 tgi->gc.set = tegra_gpio_set;
Laxman Dewanganf002d072016-04-29 21:55:23 +0530601 tgi->gc.get_direction = tegra_gpio_get_direction;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530602 tgi->gc.to_irq = tegra_gpio_to_irq;
603 tgi->gc.base = 0;
604 tgi->gc.ngpio = tgi->bank_count * 32;
605 tgi->gc.parent = &pdev->dev;
606 tgi->gc.of_node = pdev->dev.of_node;
Stephen Warren33918112012-01-19 08:16:35 +0000607
Laxman Dewanganb546be02016-04-25 16:08:33 +0530608 tgi->ic.name = "GPIO";
609 tgi->ic.irq_ack = tegra_gpio_irq_ack;
610 tgi->ic.irq_mask = tegra_gpio_irq_mask;
611 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
612 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
613 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
614#ifdef CONFIG_PM_SLEEP
615 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
616#endif
617
618 platform_set_drvdata(pdev, tgi);
619
Thierry Reding20133bd2017-07-24 16:55:05 +0200620 if (tgi->soc->debounce_supported)
Mika Westerberg2956b5d2017-01-23 15:34:34 +0300621 tgi->gc.set_config = tegra_gpio_set_config;
Laxman Dewangan3737de42016-04-25 16:08:34 +0530622
Thierry Reding9b882262017-07-24 16:55:06 +0200623 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
Laxman Dewanganb546be02016-04-25 16:08:33 +0530624 sizeof(*tgi->bank_info), GFP_KERNEL);
625 if (!tgi->bank_info)
Thierry Reding9b882262017-07-24 16:55:06 +0200626 return -ENOMEM;
Stephen Warren33918112012-01-19 08:16:35 +0000627
Laxman Dewanganb546be02016-04-25 16:08:33 +0530628 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
629 tgi->gc.ngpio,
630 &irq_domain_simple_ops, NULL);
631 if (!tgi->irq_domain)
Linus Walleijd0235672012-10-16 21:00:09 +0200632 return -ENODEV;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000633
Laxman Dewanganb546be02016-04-25 16:08:33 +0530634 for (i = 0; i < tgi->bank_count; i++) {
Thierry Reding9c074092017-07-20 18:00:57 +0200635 ret = platform_get_irq(pdev, i);
636 if (ret < 0) {
637 dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret);
638 return ret;
Stephen Warren88d89512011-10-11 16:16:14 -0600639 }
640
Laxman Dewanganb546be02016-04-25 16:08:33 +0530641 bank = &tgi->bank_info[i];
Stephen Warren88d89512011-10-11 16:16:14 -0600642 bank->bank = i;
Thierry Reding9c074092017-07-20 18:00:57 +0200643 bank->irq = ret;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530644 bank->tgi = tgi;
Stephen Warren88d89512011-10-11 16:16:14 -0600645 }
646
Enrico Weigelt, metux IT consulta0b81f12019-03-11 19:55:12 +0100647 tgi->regs = devm_platform_ioremap_resource(pdev, 0);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530648 if (IS_ERR(tgi->regs))
649 return PTR_ERR(tgi->regs);
Stephen Warren88d89512011-10-11 16:16:14 -0600650
Laxman Dewanganb546be02016-04-25 16:08:33 +0530651 for (i = 0; i < tgi->bank_count; i++) {
Erik Gilling3c92db92010-03-15 19:40:06 -0700652 for (j = 0; j < 4; j++) {
653 int gpio = tegra_gpio_compose(i, j, 0);
Thierry Reding4bc17862017-07-24 16:55:07 +0200654
Laxman Dewanganb546be02016-04-25 16:08:33 +0530655 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700656 }
657 }
658
Laxman Dewanganb546be02016-04-25 16:08:33 +0530659 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700660 if (ret < 0) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530661 irq_domain_remove(tgi->irq_domain);
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700662 return ret;
663 }
Erik Gilling3c92db92010-03-15 19:40:06 -0700664
Laxman Dewanganb546be02016-04-25 16:08:33 +0530665 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
666 int irq = irq_create_mapping(tgi->irq_domain, gpio);
Stephen Warren47008002011-08-23 00:39:55 +0100667 /* No validity check; all Tegra GPIOs are valid IRQs */
Erik Gilling3c92db92010-03-15 19:40:06 -0700668
Laxman Dewanganb546be02016-04-25 16:08:33 +0530669 bank = &tgi->bank_info[GPIO_BANK(gpio)];
Stephen Warren47008002011-08-23 00:39:55 +0100670
Stephen Warren47008002011-08-23 00:39:55 +0100671 irq_set_chip_data(irq, bank);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530672 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700673 }
674
Laxman Dewanganb546be02016-04-25 16:08:33 +0530675 for (i = 0; i < tgi->bank_count; i++) {
676 bank = &tgi->bank_info[i];
Erik Gilling3c92db92010-03-15 19:40:06 -0700677
Russell Kinge88d2512015-06-16 23:06:50 +0100678 irq_set_chained_handler_and_data(bank->irq,
679 tegra_gpio_irq_handler, bank);
Erik Gilling3c92db92010-03-15 19:40:06 -0700680
Laxman Dewangan3737de42016-04-25 16:08:34 +0530681 for (j = 0; j < 4; j++) {
Erik Gilling3c92db92010-03-15 19:40:06 -0700682 spin_lock_init(&bank->lvl_lock[j]);
Laxman Dewangan3737de42016-04-25 16:08:34 +0530683 spin_lock_init(&bank->dbc_lock[j]);
684 }
Erik Gilling3c92db92010-03-15 19:40:06 -0700685 }
686
Laxman Dewanganb546be02016-04-25 16:08:33 +0530687 tegra_gpio_debuginit(tgi);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000688
Erik Gilling3c92db92010-03-15 19:40:06 -0700689 return 0;
690}
691
Laxman Dewangan804f5682016-04-25 16:08:32 +0530692static const struct tegra_gpio_soc_config tegra20_gpio_config = {
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530693 .bank_stride = 0x80,
694 .upper_offset = 0x800,
695};
696
Laxman Dewangan804f5682016-04-25 16:08:32 +0530697static const struct tegra_gpio_soc_config tegra30_gpio_config = {
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530698 .bank_stride = 0x100,
699 .upper_offset = 0x80,
700};
701
Laxman Dewangan3737de42016-04-25 16:08:34 +0530702static const struct tegra_gpio_soc_config tegra210_gpio_config = {
703 .debounce_supported = true,
704 .bank_stride = 0x100,
705 .upper_offset = 0x80,
706};
707
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530708static const struct of_device_id tegra_gpio_of_match[] = {
Laxman Dewangan3737de42016-04-25 16:08:34 +0530709 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530710 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
711 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
712 { },
713};
714
Stephen Warren88d89512011-10-11 16:16:14 -0600715static struct platform_driver tegra_gpio_driver = {
716 .driver = {
717 .name = "tegra-gpio",
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530718 .pm = &tegra_gpio_pm_ops,
Stephen Warren88d89512011-10-11 16:16:14 -0600719 .of_match_table = tegra_gpio_of_match,
720 },
721 .probe = tegra_gpio_probe,
722};
723
724static int __init tegra_gpio_init(void)
725{
726 return platform_driver_register(&tegra_gpio_driver);
727}
Dmitry Osipenko40b25bc2018-08-02 14:11:44 +0300728subsys_initcall(tegra_gpio_init);