Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-tegra/gpio.c |
| 3 | * |
| 4 | * Copyright (c) 2010 Google, Inc |
Linus Walleij | 11da905 | 2019-02-19 21:32:02 +0100 | [diff] [blame] | 5 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 6 | * |
| 7 | * Author: |
| 8 | * Erik Gilling <konkers@google.com> |
| 9 | * |
| 10 | * This software is licensed under the terms of the GNU General Public |
| 11 | * License version 2, as published by the Free Software Foundation, and |
| 12 | * may be copied, distributed, and modified under those terms. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | */ |
| 20 | |
Thierry Reding | 641d034 | 2013-01-21 11:09:01 +0100 | [diff] [blame] | 21 | #include <linux/err.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 22 | #include <linux/init.h> |
| 23 | #include <linux/irq.h> |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 24 | #include <linux/interrupt.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 25 | #include <linux/io.h> |
Linus Walleij | 21041da | 2018-08-06 17:38:33 +0200 | [diff] [blame] | 26 | #include <linux/gpio/driver.h> |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 27 | #include <linux/of_device.h> |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/module.h> |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 30 | #include <linux/irqdomain.h> |
Catalin Marinas | de88cbb | 2013-01-18 15:31:37 +0000 | [diff] [blame] | 31 | #include <linux/irqchip/chained_irq.h> |
Stephen Warren | 3e215d0 | 2012-02-18 01:04:55 -0700 | [diff] [blame] | 32 | #include <linux/pinctrl/consumer.h> |
Laxman Dewangan | 8939ddc | 2012-11-07 20:31:32 +0530 | [diff] [blame] | 33 | #include <linux/pm.h> |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 34 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 35 | #define GPIO_BANK(x) ((x) >> 5) |
| 36 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) |
| 37 | #define GPIO_BIT(x) ((x) & 0x7) |
| 38 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 39 | #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 40 | GPIO_PORT(x) * 4) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 41 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 42 | #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) |
| 43 | #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) |
| 44 | #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) |
| 45 | #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) |
| 46 | #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) |
| 47 | #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) |
| 48 | #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) |
| 49 | #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 50 | #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) |
| 51 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 52 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 53 | #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) |
| 54 | #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) |
| 55 | #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 56 | #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 57 | #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) |
| 58 | #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) |
| 59 | #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 60 | |
| 61 | #define GPIO_INT_LVL_MASK 0x010101 |
| 62 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 |
| 63 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 |
| 64 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 |
| 65 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 |
| 66 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 |
| 67 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 68 | struct tegra_gpio_info; |
| 69 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 70 | struct tegra_gpio_bank { |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 71 | unsigned int bank; |
| 72 | unsigned int irq; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 73 | spinlock_t lvl_lock[4]; |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 74 | spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */ |
Laxman Dewangan | 8939ddc | 2012-11-07 20:31:32 +0530 | [diff] [blame] | 75 | #ifdef CONFIG_PM_SLEEP |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 76 | u32 cnf[4]; |
| 77 | u32 out[4]; |
| 78 | u32 oe[4]; |
| 79 | u32 int_enb[4]; |
| 80 | u32 int_lvl[4]; |
Joseph Lo | 203f31c | 2013-04-03 19:31:44 +0800 | [diff] [blame] | 81 | u32 wake_enb[4]; |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 82 | u32 dbc_enb[4]; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 83 | #endif |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 84 | u32 dbc_cnt[4]; |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 85 | struct tegra_gpio_info *tgi; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 86 | }; |
| 87 | |
Laxman Dewangan | 171b92c | 2016-04-25 16:08:31 +0530 | [diff] [blame] | 88 | struct tegra_gpio_soc_config { |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 89 | bool debounce_supported; |
Laxman Dewangan | 171b92c | 2016-04-25 16:08:31 +0530 | [diff] [blame] | 90 | u32 bank_stride; |
| 91 | u32 upper_offset; |
| 92 | }; |
| 93 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 94 | struct tegra_gpio_info { |
| 95 | struct device *dev; |
| 96 | void __iomem *regs; |
| 97 | struct irq_domain *irq_domain; |
| 98 | struct tegra_gpio_bank *bank_info; |
| 99 | const struct tegra_gpio_soc_config *soc; |
| 100 | struct gpio_chip gc; |
| 101 | struct irq_chip ic; |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 102 | u32 bank_count; |
| 103 | }; |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 104 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 105 | static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, |
| 106 | u32 val, u32 reg) |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 107 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 108 | __raw_writel(val, tgi->regs + reg); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 109 | } |
| 110 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 111 | static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 112 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 113 | return __raw_readl(tgi->regs + reg); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 114 | } |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 115 | |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 116 | static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, |
| 117 | unsigned int bit) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 118 | { |
| 119 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); |
| 120 | } |
| 121 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 122 | static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 123 | unsigned int gpio, u32 value) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 124 | { |
| 125 | u32 val; |
| 126 | |
| 127 | val = 0x100 << GPIO_BIT(gpio); |
| 128 | if (value) |
| 129 | val |= 1 << GPIO_BIT(gpio); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 130 | tegra_gpio_writel(tgi, val, reg); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 133 | static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 134 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 135 | tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 136 | } |
| 137 | |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 138 | static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 139 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 140 | tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 141 | } |
| 142 | |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 143 | static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) |
Stephen Warren | 3e215d0 | 2012-02-18 01:04:55 -0700 | [diff] [blame] | 144 | { |
Linus Walleij | 11da905 | 2019-02-19 21:32:02 +0100 | [diff] [blame] | 145 | return pinctrl_gpio_request(chip->base + offset); |
Stephen Warren | 3e215d0 | 2012-02-18 01:04:55 -0700 | [diff] [blame] | 146 | } |
| 147 | |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 148 | static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) |
Stephen Warren | 3e215d0 | 2012-02-18 01:04:55 -0700 | [diff] [blame] | 149 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 150 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
| 151 | |
Linus Walleij | 11da905 | 2019-02-19 21:32:02 +0100 | [diff] [blame] | 152 | pinctrl_gpio_free(chip->base + offset); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 153 | tegra_gpio_disable(tgi, offset); |
Stephen Warren | 3e215d0 | 2012-02-18 01:04:55 -0700 | [diff] [blame] | 154 | } |
| 155 | |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 156 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, |
| 157 | int value) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 158 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 159 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
| 160 | |
| 161 | tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 162 | } |
| 163 | |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 164 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 165 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 166 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 167 | unsigned int bval = BIT(GPIO_BIT(offset)); |
Laxman Dewangan | 195812e | 2012-11-09 11:34:20 +0530 | [diff] [blame] | 168 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 169 | /* If gpio is in output mode then read from the out value */ |
| 170 | if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) |
| 171 | return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); |
| 172 | |
| 173 | return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 174 | } |
| 175 | |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 176 | static int tegra_gpio_direction_input(struct gpio_chip *chip, |
| 177 | unsigned int offset) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 178 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 179 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
Linus Walleij | 11da905 | 2019-02-19 21:32:02 +0100 | [diff] [blame] | 180 | int ret; |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 181 | |
| 182 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); |
| 183 | tegra_gpio_enable(tgi, offset); |
Linus Walleij | 11da905 | 2019-02-19 21:32:02 +0100 | [diff] [blame] | 184 | |
| 185 | ret = pinctrl_gpio_direction_input(chip->base + offset); |
| 186 | if (ret < 0) |
| 187 | dev_err(tgi->dev, |
| 188 | "Failed to set pinctrl input direction of GPIO %d: %d", |
| 189 | chip->base + offset, ret); |
| 190 | |
| 191 | return ret; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 192 | } |
| 193 | |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 194 | static int tegra_gpio_direction_output(struct gpio_chip *chip, |
| 195 | unsigned int offset, |
| 196 | int value) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 197 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 198 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
Linus Walleij | 11da905 | 2019-02-19 21:32:02 +0100 | [diff] [blame] | 199 | int ret; |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 200 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 201 | tegra_gpio_set(chip, offset, value); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 202 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); |
| 203 | tegra_gpio_enable(tgi, offset); |
Linus Walleij | 11da905 | 2019-02-19 21:32:02 +0100 | [diff] [blame] | 204 | |
| 205 | ret = pinctrl_gpio_direction_output(chip->base + offset); |
| 206 | if (ret < 0) |
| 207 | dev_err(tgi->dev, |
| 208 | "Failed to set pinctrl output direction of GPIO %d: %d", |
| 209 | chip->base + offset, ret); |
| 210 | |
| 211 | return ret; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 212 | } |
| 213 | |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 214 | static int tegra_gpio_get_direction(struct gpio_chip *chip, |
| 215 | unsigned int offset) |
Laxman Dewangan | f002d07 | 2016-04-29 21:55:23 +0530 | [diff] [blame] | 216 | { |
| 217 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
| 218 | u32 pin_mask = BIT(GPIO_BIT(offset)); |
| 219 | u32 cnf, oe; |
| 220 | |
| 221 | cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); |
| 222 | if (!(cnf & pin_mask)) |
| 223 | return -EINVAL; |
| 224 | |
| 225 | oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); |
| 226 | |
Linus Walleij | 21041da | 2018-08-06 17:38:33 +0200 | [diff] [blame] | 227 | return !(oe & pin_mask); |
Laxman Dewangan | f002d07 | 2016-04-29 21:55:23 +0530 | [diff] [blame] | 228 | } |
| 229 | |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 230 | static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, |
| 231 | unsigned int debounce) |
| 232 | { |
| 233 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
| 234 | struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; |
| 235 | unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); |
| 236 | unsigned long flags; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 237 | unsigned int port; |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 238 | |
| 239 | if (!debounce_ms) { |
| 240 | tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), |
| 241 | offset, 0); |
| 242 | return 0; |
| 243 | } |
| 244 | |
| 245 | debounce_ms = min(debounce_ms, 255U); |
| 246 | port = GPIO_PORT(offset); |
| 247 | |
| 248 | /* There is only one debounce count register per port and hence |
| 249 | * set the maximum of current and requested debounce time. |
| 250 | */ |
| 251 | spin_lock_irqsave(&bank->dbc_lock[port], flags); |
| 252 | if (bank->dbc_cnt[port] < debounce_ms) { |
| 253 | tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); |
| 254 | bank->dbc_cnt[port] = debounce_ms; |
| 255 | } |
| 256 | spin_unlock_irqrestore(&bank->dbc_lock[port], flags); |
| 257 | |
| 258 | tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); |
| 259 | |
| 260 | return 0; |
| 261 | } |
| 262 | |
Mika Westerberg | 2956b5d | 2017-01-23 15:34:34 +0300 | [diff] [blame] | 263 | static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
| 264 | unsigned long config) |
| 265 | { |
| 266 | u32 debounce; |
| 267 | |
| 268 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) |
| 269 | return -ENOTSUPP; |
| 270 | |
| 271 | debounce = pinconf_to_config_argument(config); |
| 272 | return tegra_gpio_set_debounce(chip, offset, debounce); |
| 273 | } |
| 274 | |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 275 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) |
Stephen Warren | 438a99c | 2011-08-23 00:39:56 +0100 | [diff] [blame] | 276 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 277 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 278 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 279 | return irq_find_mapping(tgi->irq_domain, offset); |
| 280 | } |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 281 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 282 | static void tegra_gpio_irq_ack(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 283 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 284 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
| 285 | struct tegra_gpio_info *tgi = bank->tgi; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 286 | unsigned int gpio = d->hwirq; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 287 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 288 | tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 289 | } |
| 290 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 291 | static void tegra_gpio_irq_mask(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 292 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 293 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
| 294 | struct tegra_gpio_info *tgi = bank->tgi; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 295 | unsigned int gpio = d->hwirq; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 296 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 297 | tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 298 | } |
| 299 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 300 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 301 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 302 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
| 303 | struct tegra_gpio_info *tgi = bank->tgi; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 304 | unsigned int gpio = d->hwirq; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 305 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 306 | tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 307 | } |
| 308 | |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 309 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 310 | { |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 311 | unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 312 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 313 | struct tegra_gpio_info *tgi = bank->tgi; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 314 | unsigned long flags; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 315 | u32 val; |
Stephen Warren | df231f2 | 2013-10-16 13:25:33 -0600 | [diff] [blame] | 316 | int ret; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 317 | |
| 318 | switch (type & IRQ_TYPE_SENSE_MASK) { |
| 319 | case IRQ_TYPE_EDGE_RISING: |
| 320 | lvl_type = GPIO_INT_LVL_EDGE_RISING; |
| 321 | break; |
| 322 | |
| 323 | case IRQ_TYPE_EDGE_FALLING: |
| 324 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; |
| 325 | break; |
| 326 | |
| 327 | case IRQ_TYPE_EDGE_BOTH: |
| 328 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; |
| 329 | break; |
| 330 | |
| 331 | case IRQ_TYPE_LEVEL_HIGH: |
| 332 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; |
| 333 | break; |
| 334 | |
| 335 | case IRQ_TYPE_LEVEL_LOW: |
| 336 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; |
| 337 | break; |
| 338 | |
| 339 | default: |
| 340 | return -EINVAL; |
| 341 | } |
| 342 | |
| 343 | spin_lock_irqsave(&bank->lvl_lock[port], flags); |
| 344 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 345 | val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 346 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
| 347 | val |= lvl_type << GPIO_BIT(gpio); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 348 | tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 349 | |
| 350 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); |
| 351 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 352 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); |
| 353 | tegra_gpio_enable(tgi, gpio); |
Stephen Warren | d941136 | 2012-03-19 10:31:58 -0600 | [diff] [blame] | 354 | |
Dmitry Osipenko | f78709a | 2018-07-17 19:10:38 +0300 | [diff] [blame] | 355 | ret = gpiochip_lock_as_irq(&tgi->gc, gpio); |
| 356 | if (ret) { |
| 357 | dev_err(tgi->dev, |
| 358 | "unable to lock Tegra GPIO %u as IRQ\n", gpio); |
| 359 | tegra_gpio_disable(tgi, gpio); |
| 360 | return ret; |
| 361 | } |
| 362 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 363 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
Thomas Gleixner | f170d71 | 2015-06-23 15:52:40 +0200 | [diff] [blame] | 364 | irq_set_handler_locked(d, handle_level_irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 365 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
Thomas Gleixner | f170d71 | 2015-06-23 15:52:40 +0200 | [diff] [blame] | 366 | irq_set_handler_locked(d, handle_edge_irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 367 | |
| 368 | return 0; |
| 369 | } |
| 370 | |
Stephen Warren | df231f2 | 2013-10-16 13:25:33 -0600 | [diff] [blame] | 371 | static void tegra_gpio_irq_shutdown(struct irq_data *d) |
| 372 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 373 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
| 374 | struct tegra_gpio_info *tgi = bank->tgi; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 375 | unsigned int gpio = d->hwirq; |
Stephen Warren | df231f2 | 2013-10-16 13:25:33 -0600 | [diff] [blame] | 376 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 377 | gpiochip_unlock_as_irq(&tgi->gc, gpio); |
Stephen Warren | df231f2 | 2013-10-16 13:25:33 -0600 | [diff] [blame] | 378 | } |
| 379 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 380 | static void tegra_gpio_irq_handler(struct irq_desc *desc) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 381 | { |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 382 | unsigned int port, pin, gpio; |
Michał Mirosław | 9e9509e | 2017-07-18 14:35:45 +0200 | [diff] [blame] | 383 | bool unmasked = false; |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 384 | u32 lvl; |
| 385 | unsigned long sta; |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 386 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Jiang Liu | 476f8b4 | 2015-06-04 12:13:15 +0800 | [diff] [blame] | 387 | struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 388 | struct tegra_gpio_info *tgi = bank->tgi; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 389 | |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 390 | chained_irq_enter(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 391 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 392 | for (port = 0; port < 4; port++) { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 393 | gpio = tegra_gpio_compose(bank->bank, port, 0); |
| 394 | sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & |
| 395 | tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); |
| 396 | lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 397 | |
| 398 | for_each_set_bit(pin, &sta, 8) { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 399 | tegra_gpio_writel(tgi, 1 << pin, |
| 400 | GPIO_INT_CLR(tgi, gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 401 | |
| 402 | /* if gpio is edge triggered, clear condition |
Colin Cronin | 20a8a96 | 2015-05-18 11:41:43 -0700 | [diff] [blame] | 403 | * before executing the handler so that we don't |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 404 | * miss edges |
| 405 | */ |
Michał Mirosław | 9e9509e | 2017-07-18 14:35:45 +0200 | [diff] [blame] | 406 | if (!unmasked && lvl & (0x100 << pin)) { |
| 407 | unmasked = true; |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 408 | chained_irq_exit(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 409 | } |
| 410 | |
Grygorii Strashko | c0debb3 | 2017-07-08 17:44:11 -0500 | [diff] [blame] | 411 | generic_handle_irq(irq_find_mapping(tgi->irq_domain, |
| 412 | gpio + pin)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 413 | } |
| 414 | } |
| 415 | |
| 416 | if (!unmasked) |
Will Deacon | 9802294 | 2011-02-21 13:58:10 +0000 | [diff] [blame] | 417 | chained_irq_exit(chip, desc); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 418 | |
| 419 | } |
| 420 | |
Laxman Dewangan | 8939ddc | 2012-11-07 20:31:32 +0530 | [diff] [blame] | 421 | #ifdef CONFIG_PM_SLEEP |
| 422 | static int tegra_gpio_resume(struct device *dev) |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 423 | { |
Wolfram Sang | 7ddb7dc | 2018-10-21 22:00:00 +0200 | [diff] [blame] | 424 | struct tegra_gpio_info *tgi = dev_get_drvdata(dev); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 425 | unsigned long flags; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 426 | unsigned int b, p; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 427 | |
| 428 | local_irq_save(flags); |
| 429 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 430 | for (b = 0; b < tgi->bank_count; b++) { |
| 431 | struct tegra_gpio_bank *bank = &tgi->bank_info[b]; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 432 | |
| 433 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 434 | unsigned int gpio = (b << 5) | (p << 3); |
| 435 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 436 | tegra_gpio_writel(tgi, bank->cnf[p], |
| 437 | GPIO_CNF(tgi, gpio)); |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 438 | |
| 439 | if (tgi->soc->debounce_supported) { |
| 440 | tegra_gpio_writel(tgi, bank->dbc_cnt[p], |
| 441 | GPIO_DBC_CNT(tgi, gpio)); |
| 442 | tegra_gpio_writel(tgi, bank->dbc_enb[p], |
| 443 | GPIO_MSK_DBC_EN(tgi, gpio)); |
| 444 | } |
| 445 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 446 | tegra_gpio_writel(tgi, bank->out[p], |
| 447 | GPIO_OUT(tgi, gpio)); |
| 448 | tegra_gpio_writel(tgi, bank->oe[p], |
| 449 | GPIO_OE(tgi, gpio)); |
| 450 | tegra_gpio_writel(tgi, bank->int_lvl[p], |
| 451 | GPIO_INT_LVL(tgi, gpio)); |
| 452 | tegra_gpio_writel(tgi, bank->int_enb[p], |
| 453 | GPIO_INT_ENB(tgi, gpio)); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 454 | } |
| 455 | } |
| 456 | |
| 457 | local_irq_restore(flags); |
Laxman Dewangan | 8939ddc | 2012-11-07 20:31:32 +0530 | [diff] [blame] | 458 | return 0; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 459 | } |
| 460 | |
Laxman Dewangan | 8939ddc | 2012-11-07 20:31:32 +0530 | [diff] [blame] | 461 | static int tegra_gpio_suspend(struct device *dev) |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 462 | { |
Wolfram Sang | 7ddb7dc | 2018-10-21 22:00:00 +0200 | [diff] [blame] | 463 | struct tegra_gpio_info *tgi = dev_get_drvdata(dev); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 464 | unsigned long flags; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 465 | unsigned int b, p; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 466 | |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 467 | local_irq_save(flags); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 468 | for (b = 0; b < tgi->bank_count; b++) { |
| 469 | struct tegra_gpio_bank *bank = &tgi->bank_info[b]; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 470 | |
| 471 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 472 | unsigned int gpio = (b << 5) | (p << 3); |
| 473 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 474 | bank->cnf[p] = tegra_gpio_readl(tgi, |
| 475 | GPIO_CNF(tgi, gpio)); |
| 476 | bank->out[p] = tegra_gpio_readl(tgi, |
| 477 | GPIO_OUT(tgi, gpio)); |
| 478 | bank->oe[p] = tegra_gpio_readl(tgi, |
| 479 | GPIO_OE(tgi, gpio)); |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 480 | if (tgi->soc->debounce_supported) { |
| 481 | bank->dbc_enb[p] = tegra_gpio_readl(tgi, |
| 482 | GPIO_MSK_DBC_EN(tgi, gpio)); |
| 483 | bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | |
| 484 | bank->dbc_enb[p]; |
| 485 | } |
| 486 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 487 | bank->int_enb[p] = tegra_gpio_readl(tgi, |
| 488 | GPIO_INT_ENB(tgi, gpio)); |
| 489 | bank->int_lvl[p] = tegra_gpio_readl(tgi, |
| 490 | GPIO_INT_LVL(tgi, gpio)); |
Joseph Lo | 203f31c | 2013-04-03 19:31:44 +0800 | [diff] [blame] | 491 | |
| 492 | /* Enable gpio irq for wake up source */ |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 493 | tegra_gpio_writel(tgi, bank->wake_enb[p], |
| 494 | GPIO_INT_ENB(tgi, gpio)); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 495 | } |
| 496 | } |
| 497 | local_irq_restore(flags); |
Laxman Dewangan | 8939ddc | 2012-11-07 20:31:32 +0530 | [diff] [blame] | 498 | return 0; |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 499 | } |
| 500 | |
Joseph Lo | 203f31c | 2013-04-03 19:31:44 +0800 | [diff] [blame] | 501 | static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 502 | { |
Lennert Buytenhek | 37337a8 | 2010-11-29 11:14:46 +0100 | [diff] [blame] | 503 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 504 | unsigned int gpio = d->hwirq; |
Joseph Lo | 203f31c | 2013-04-03 19:31:44 +0800 | [diff] [blame] | 505 | u32 port, bit, mask; |
| 506 | |
| 507 | port = GPIO_PORT(gpio); |
| 508 | bit = GPIO_BIT(gpio); |
| 509 | mask = BIT(bit); |
| 510 | |
| 511 | if (enable) |
| 512 | bank->wake_enb[port] |= mask; |
| 513 | else |
| 514 | bank->wake_enb[port] &= ~mask; |
| 515 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 516 | return irq_set_irq_wake(bank->irq, enable); |
Colin Cross | 2e47b8b | 2010-04-07 12:59:42 -0700 | [diff] [blame] | 517 | } |
| 518 | #endif |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 519 | |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 520 | #ifdef CONFIG_DEBUG_FS |
| 521 | |
| 522 | #include <linux/debugfs.h> |
| 523 | #include <linux/seq_file.h> |
| 524 | |
Axel Lin | 2773eb2 | 2018-02-12 22:01:57 +0800 | [diff] [blame] | 525 | static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 526 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 527 | struct tegra_gpio_info *tgi = s->private; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 528 | unsigned int i, j; |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 529 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 530 | for (i = 0; i < tgi->bank_count; i++) { |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 531 | for (j = 0; j < 4; j++) { |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 532 | unsigned int gpio = tegra_gpio_compose(i, j, 0); |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 533 | |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 534 | seq_printf(s, |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 535 | "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 536 | i, j, |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 537 | tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), |
| 538 | tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), |
| 539 | tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), |
| 540 | tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), |
| 541 | tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), |
| 542 | tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), |
| 543 | tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 544 | } |
| 545 | } |
| 546 | return 0; |
| 547 | } |
| 548 | |
Axel Lin | 2773eb2 | 2018-02-12 22:01:57 +0800 | [diff] [blame] | 549 | DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio); |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 550 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 551 | static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 552 | { |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 553 | (void) debugfs_create_file("tegra_gpio", 0444, |
Axel Lin | 2773eb2 | 2018-02-12 22:01:57 +0800 | [diff] [blame] | 554 | NULL, tgi, &tegra_dbg_gpio_fops); |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 555 | } |
| 556 | |
| 557 | #else |
| 558 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 559 | static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 560 | { |
| 561 | } |
| 562 | |
| 563 | #endif |
| 564 | |
Laxman Dewangan | 8939ddc | 2012-11-07 20:31:32 +0530 | [diff] [blame] | 565 | static const struct dev_pm_ops tegra_gpio_pm_ops = { |
| 566 | SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) |
| 567 | }; |
| 568 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 569 | static int tegra_gpio_probe(struct platform_device *pdev) |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 570 | { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 571 | struct tegra_gpio_info *tgi; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 572 | struct tegra_gpio_bank *bank; |
Thierry Reding | 539b7a3 | 2017-07-24 16:55:08 +0200 | [diff] [blame] | 573 | unsigned int gpio, i, j; |
Stephen Warren | f57f98a | 2013-12-06 13:36:11 -0700 | [diff] [blame] | 574 | int ret; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 575 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 576 | tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); |
| 577 | if (!tgi) |
| 578 | return -ENODEV; |
| 579 | |
Thierry Reding | 20133bd | 2017-07-24 16:55:05 +0200 | [diff] [blame] | 580 | tgi->soc = of_device_get_match_data(&pdev->dev); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 581 | tgi->dev = &pdev->dev; |
Stephen Warren | 5c1e2c9 | 2012-03-16 17:35:08 -0600 | [diff] [blame] | 582 | |
Thierry Reding | 5642090 | 2017-07-20 18:00:56 +0200 | [diff] [blame] | 583 | ret = platform_irq_count(pdev); |
| 584 | if (ret < 0) |
| 585 | return ret; |
| 586 | |
| 587 | tgi->bank_count = ret; |
| 588 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 589 | if (!tgi->bank_count) { |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 590 | dev_err(&pdev->dev, "Missing IRQ resource\n"); |
| 591 | return -ENODEV; |
| 592 | } |
| 593 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 594 | tgi->gc.label = "tegra-gpio"; |
| 595 | tgi->gc.request = tegra_gpio_request; |
| 596 | tgi->gc.free = tegra_gpio_free; |
| 597 | tgi->gc.direction_input = tegra_gpio_direction_input; |
| 598 | tgi->gc.get = tegra_gpio_get; |
| 599 | tgi->gc.direction_output = tegra_gpio_direction_output; |
| 600 | tgi->gc.set = tegra_gpio_set; |
Laxman Dewangan | f002d07 | 2016-04-29 21:55:23 +0530 | [diff] [blame] | 601 | tgi->gc.get_direction = tegra_gpio_get_direction; |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 602 | tgi->gc.to_irq = tegra_gpio_to_irq; |
| 603 | tgi->gc.base = 0; |
| 604 | tgi->gc.ngpio = tgi->bank_count * 32; |
| 605 | tgi->gc.parent = &pdev->dev; |
| 606 | tgi->gc.of_node = pdev->dev.of_node; |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 607 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 608 | tgi->ic.name = "GPIO"; |
| 609 | tgi->ic.irq_ack = tegra_gpio_irq_ack; |
| 610 | tgi->ic.irq_mask = tegra_gpio_irq_mask; |
| 611 | tgi->ic.irq_unmask = tegra_gpio_irq_unmask; |
| 612 | tgi->ic.irq_set_type = tegra_gpio_irq_set_type; |
| 613 | tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; |
| 614 | #ifdef CONFIG_PM_SLEEP |
| 615 | tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; |
| 616 | #endif |
| 617 | |
| 618 | platform_set_drvdata(pdev, tgi); |
| 619 | |
Thierry Reding | 20133bd | 2017-07-24 16:55:05 +0200 | [diff] [blame] | 620 | if (tgi->soc->debounce_supported) |
Mika Westerberg | 2956b5d | 2017-01-23 15:34:34 +0300 | [diff] [blame] | 621 | tgi->gc.set_config = tegra_gpio_set_config; |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 622 | |
Thierry Reding | 9b88226 | 2017-07-24 16:55:06 +0200 | [diff] [blame] | 623 | tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 624 | sizeof(*tgi->bank_info), GFP_KERNEL); |
| 625 | if (!tgi->bank_info) |
Thierry Reding | 9b88226 | 2017-07-24 16:55:06 +0200 | [diff] [blame] | 626 | return -ENOMEM; |
Stephen Warren | 3391811 | 2012-01-19 08:16:35 +0000 | [diff] [blame] | 627 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 628 | tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, |
| 629 | tgi->gc.ngpio, |
| 630 | &irq_domain_simple_ops, NULL); |
| 631 | if (!tgi->irq_domain) |
Linus Walleij | d023567 | 2012-10-16 21:00:09 +0200 | [diff] [blame] | 632 | return -ENODEV; |
Stephen Warren | 6f74dc9 | 2012-01-04 08:39:37 +0000 | [diff] [blame] | 633 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 634 | for (i = 0; i < tgi->bank_count; i++) { |
Thierry Reding | 9c07409 | 2017-07-20 18:00:57 +0200 | [diff] [blame] | 635 | ret = platform_get_irq(pdev, i); |
| 636 | if (ret < 0) { |
| 637 | dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret); |
| 638 | return ret; |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 639 | } |
| 640 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 641 | bank = &tgi->bank_info[i]; |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 642 | bank->bank = i; |
Thierry Reding | 9c07409 | 2017-07-20 18:00:57 +0200 | [diff] [blame] | 643 | bank->irq = ret; |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 644 | bank->tgi = tgi; |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 645 | } |
| 646 | |
Enrico Weigelt, metux IT consult | a0b81f1 | 2019-03-11 19:55:12 +0100 | [diff] [blame^] | 647 | tgi->regs = devm_platform_ioremap_resource(pdev, 0); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 648 | if (IS_ERR(tgi->regs)) |
| 649 | return PTR_ERR(tgi->regs); |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 650 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 651 | for (i = 0; i < tgi->bank_count; i++) { |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 652 | for (j = 0; j < 4; j++) { |
| 653 | int gpio = tegra_gpio_compose(i, j, 0); |
Thierry Reding | 4bc1786 | 2017-07-24 16:55:07 +0200 | [diff] [blame] | 654 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 655 | tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 656 | } |
| 657 | } |
| 658 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 659 | ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); |
Stephen Warren | f57f98a | 2013-12-06 13:36:11 -0700 | [diff] [blame] | 660 | if (ret < 0) { |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 661 | irq_domain_remove(tgi->irq_domain); |
Stephen Warren | f57f98a | 2013-12-06 13:36:11 -0700 | [diff] [blame] | 662 | return ret; |
| 663 | } |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 664 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 665 | for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) { |
| 666 | int irq = irq_create_mapping(tgi->irq_domain, gpio); |
Stephen Warren | 4700800 | 2011-08-23 00:39:55 +0100 | [diff] [blame] | 667 | /* No validity check; all Tegra GPIOs are valid IRQs */ |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 668 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 669 | bank = &tgi->bank_info[GPIO_BANK(gpio)]; |
Stephen Warren | 4700800 | 2011-08-23 00:39:55 +0100 | [diff] [blame] | 670 | |
Stephen Warren | 4700800 | 2011-08-23 00:39:55 +0100 | [diff] [blame] | 671 | irq_set_chip_data(irq, bank); |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 672 | irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 673 | } |
| 674 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 675 | for (i = 0; i < tgi->bank_count; i++) { |
| 676 | bank = &tgi->bank_info[i]; |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 677 | |
Russell King | e88d251 | 2015-06-16 23:06:50 +0100 | [diff] [blame] | 678 | irq_set_chained_handler_and_data(bank->irq, |
| 679 | tegra_gpio_irq_handler, bank); |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 680 | |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 681 | for (j = 0; j < 4; j++) { |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 682 | spin_lock_init(&bank->lvl_lock[j]); |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 683 | spin_lock_init(&bank->dbc_lock[j]); |
| 684 | } |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 685 | } |
| 686 | |
Laxman Dewangan | b546be0 | 2016-04-25 16:08:33 +0530 | [diff] [blame] | 687 | tegra_gpio_debuginit(tgi); |
Suzuki K. Poulose | b59d5fb | 2015-11-16 16:07:10 +0000 | [diff] [blame] | 688 | |
Erik Gilling | 3c92db9 | 2010-03-15 19:40:06 -0700 | [diff] [blame] | 689 | return 0; |
| 690 | } |
| 691 | |
Laxman Dewangan | 804f568 | 2016-04-25 16:08:32 +0530 | [diff] [blame] | 692 | static const struct tegra_gpio_soc_config tegra20_gpio_config = { |
Laxman Dewangan | 171b92c | 2016-04-25 16:08:31 +0530 | [diff] [blame] | 693 | .bank_stride = 0x80, |
| 694 | .upper_offset = 0x800, |
| 695 | }; |
| 696 | |
Laxman Dewangan | 804f568 | 2016-04-25 16:08:32 +0530 | [diff] [blame] | 697 | static const struct tegra_gpio_soc_config tegra30_gpio_config = { |
Laxman Dewangan | 171b92c | 2016-04-25 16:08:31 +0530 | [diff] [blame] | 698 | .bank_stride = 0x100, |
| 699 | .upper_offset = 0x80, |
| 700 | }; |
| 701 | |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 702 | static const struct tegra_gpio_soc_config tegra210_gpio_config = { |
| 703 | .debounce_supported = true, |
| 704 | .bank_stride = 0x100, |
| 705 | .upper_offset = 0x80, |
| 706 | }; |
| 707 | |
Laxman Dewangan | 171b92c | 2016-04-25 16:08:31 +0530 | [diff] [blame] | 708 | static const struct of_device_id tegra_gpio_of_match[] = { |
Laxman Dewangan | 3737de4 | 2016-04-25 16:08:34 +0530 | [diff] [blame] | 709 | { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, |
Laxman Dewangan | 171b92c | 2016-04-25 16:08:31 +0530 | [diff] [blame] | 710 | { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, |
| 711 | { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, |
| 712 | { }, |
| 713 | }; |
| 714 | |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 715 | static struct platform_driver tegra_gpio_driver = { |
| 716 | .driver = { |
| 717 | .name = "tegra-gpio", |
Laxman Dewangan | 8939ddc | 2012-11-07 20:31:32 +0530 | [diff] [blame] | 718 | .pm = &tegra_gpio_pm_ops, |
Stephen Warren | 88d8951 | 2011-10-11 16:16:14 -0600 | [diff] [blame] | 719 | .of_match_table = tegra_gpio_of_match, |
| 720 | }, |
| 721 | .probe = tegra_gpio_probe, |
| 722 | }; |
| 723 | |
| 724 | static int __init tegra_gpio_init(void) |
| 725 | { |
| 726 | return platform_driver_register(&tegra_gpio_driver); |
| 727 | } |
Dmitry Osipenko | 40b25bc | 2018-08-02 14:11:44 +0300 | [diff] [blame] | 728 | subsys_initcall(tegra_gpio_init); |