blob: e64c0fd82fe4600a7ab274a997a2d62e99fc3d34 [file] [log] [blame]
Stephen Boydcb546b72018-08-14 17:42:22 +05301// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018, The Linux Foundation. All rights reserved.
3
4#include <linux/kernel.h>
5#include <linux/init.h>
6#include <linux/module.h>
7#include <linux/platform_device.h>
8#include <linux/of.h>
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/regmap.h>
12
13#include "clk-regmap.h"
14#include "clk-hfpll.h"
15
16static const struct hfpll_data hdata = {
17 .mode_reg = 0x00,
18 .l_reg = 0x04,
19 .m_reg = 0x08,
20 .n_reg = 0x0c,
21 .user_reg = 0x10,
22 .config_reg = 0x14,
23 .config_val = 0x430405d,
24 .status_reg = 0x1c,
25 .lock_bit = 16,
26
27 .user_val = 0x8,
28 .user_vco_mask = 0x100000,
29 .low_vco_max_rate = 1248000000,
30 .min_rate = 537600000UL,
31 .max_rate = 2900000000UL,
32};
33
34static const struct of_device_id qcom_hfpll_match_table[] = {
35 { .compatible = "qcom,hfpll" },
36 { }
37};
38MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
39
40static const struct regmap_config hfpll_regmap_config = {
41 .reg_bits = 32,
42 .reg_stride = 4,
43 .val_bits = 32,
44 .max_register = 0x30,
45 .fast_io = true,
46};
47
48static int qcom_hfpll_probe(struct platform_device *pdev)
49{
50 struct resource *res;
51 struct device *dev = &pdev->dev;
52 void __iomem *base;
53 struct regmap *regmap;
54 struct clk_hfpll *h;
55 struct clk_init_data init = {
56 .parent_names = (const char *[]){ "xo" },
57 .num_parents = 1,
58 .ops = &clk_ops_hfpll,
59 };
Jorge Ramirez-Ortiz9e406672019-11-25 14:59:05 +010060 int ret;
Stephen Boydcb546b72018-08-14 17:42:22 +053061
62 h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
63 if (!h)
64 return -ENOMEM;
65
66 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
67 base = devm_ioremap_resource(dev, res);
68 if (IS_ERR(base))
69 return PTR_ERR(base);
70
71 regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
72 if (IS_ERR(regmap))
73 return PTR_ERR(regmap);
74
75 if (of_property_read_string_index(dev->of_node, "clock-output-names",
76 0, &init.name))
77 return -ENODEV;
78
79 h->d = &hdata;
80 h->clkr.hw.init = &init;
81 spin_lock_init(&h->lock);
82
Jorge Ramirez-Ortiz9e406672019-11-25 14:59:05 +010083 ret = devm_clk_register_regmap(dev, &h->clkr);
84 if (ret) {
85 dev_err(dev, "failed to register regmap clock: %d\n", ret);
86 return ret;
87 }
88
89 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
90 &h->clkr.hw);
Stephen Boydcb546b72018-08-14 17:42:22 +053091}
92
93static struct platform_driver qcom_hfpll_driver = {
94 .probe = qcom_hfpll_probe,
95 .driver = {
96 .name = "qcom-hfpll",
97 .of_match_table = qcom_hfpll_match_table,
98 },
99};
100module_platform_driver(qcom_hfpll_driver);
101
102MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
103MODULE_LICENSE("GPL v2");
104MODULE_ALIAS("platform:qcom-hfpll");