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Santosh Shilimkar2722e562011-03-07 20:53:10 +05301/*
Sricharan Rc10d5c92014-04-11 13:09:36 -05002 * OMAP L3 Interconnect error handling driver
sricharaned0e3522011-08-24 20:07:45 +05303 *
Nishanth Menonc5f2aea2014-04-11 13:15:43 -05004 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
sricharaned0e3522011-08-24 20:07:45 +05305 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
Nishanth Menonc5f2aea2014-04-11 13:15:43 -05009 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
sricharaned0e3522011-08-24 20:07:45 +053011 *
Nishanth Menonc5f2aea2014-04-11 13:15:43 -050012 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
sricharaned0e3522011-08-24 20:07:45 +053015 * GNU General Public License for more details.
sricharaned0e3522011-08-24 20:07:45 +053016 */
Axel Lind4fc7eb2011-11-02 09:40:11 +080017#include <linux/module.h>
Santosh Shilimkar2722e562011-03-07 20:53:10 +053018#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/platform_device.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/slab.h>
24
25#include "omap_l3_noc.h"
26
27/*
28 * Interrupt Handler for L3 error detection.
29 * 1) Identify the L3 clockdomain partition to which the error belongs to.
30 * 2) Identify the slave where the error information is logged
31 * 3) Print the logged information.
32 * 4) Add dump stack to provide kernel trace.
33 *
34 * Two Types of errors :
35 * 1) Custom errors in L3 :
36 * Target like DMM/FW/EMIF generates SRESP=ERR error
37 * 2) Standard L3 error:
38 * - Unsupported CMD.
39 * L3 tries to access target while it is idle
40 * - OCP disconnect.
41 * - Address hole error:
42 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
43 * do not have connectivity, the error is logged in
44 * their default target which is DMM2.
45 *
46 * On High Secure devices, firewall errors are possible and those
47 * can be trapped as well. But the trapping is implemented as part
48 * secure software and hence need not be implemented here.
49 */
50static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
51{
52
Sricharan Rc10d5c92014-04-11 13:09:36 -050053 struct omap_l3 *l3 = _l3;
sricharan551a9fa2011-09-07 17:25:16 +053054 int inttype, i, k;
Santosh Shilimkar2722e562011-03-07 20:53:10 +053055 int err_src = 0;
sricharan551a9fa2011-09-07 17:25:16 +053056 u32 std_err_main, err_reg, clear, masterid;
sricharan6616aac2011-08-23 12:58:48 +053057 void __iomem *base, *l3_targ_base;
Nishanth Menon9e224c82014-04-11 11:21:47 -050058 void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
sricharan551a9fa2011-09-07 17:25:16 +053059 char *target_name, *master_name = "UN IDENTIFIED";
Santosh Shilimkar2722e562011-03-07 20:53:10 +053060
61 /* Get the Type of interrupt */
omar ramirez35f7b962011-04-18 16:39:42 +000062 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
Santosh Shilimkar2722e562011-03-07 20:53:10 +053063
64 for (i = 0; i < L3_MODULES; i++) {
65 /*
66 * Read the regerr register of the clock domain
67 * to determine the source
68 */
sricharan6616aac2011-08-23 12:58:48 +053069 base = l3->l3_base[i];
Nishanth Menon9e224c82014-04-11 11:21:47 -050070 err_reg = readl_relaxed(base + l3_flagmux[i] +
71 L3_FLAGMUX_REGERR0 + (inttype << 3));
Santosh Shilimkar2722e562011-03-07 20:53:10 +053072
73 /* Get the corresponding error and analyse */
74 if (err_reg) {
75 /* Identify the source from control status register */
Todd Poynor342fd142011-08-24 19:11:39 +053076 err_src = __ffs(err_reg);
Santosh Shilimkar2722e562011-03-07 20:53:10 +053077
Santosh Shilimkar2722e562011-03-07 20:53:10 +053078 /* Read the stderrlog_main_source from clk domain */
Todd Poynor342fd142011-08-24 19:11:39 +053079 l3_targ_base = base + *(l3_targ[i] + err_src);
Nishanth Menon9e224c82014-04-11 11:21:47 -050080 l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
81 l3_targ_slvofslsb = l3_targ_base +
82 L3_TARG_STDERRLOG_SLVOFSLSB;
83 l3_targ_mstaddr = l3_targ_base +
84 L3_TARG_STDERRLOG_MSTADDR;
85
86 std_err_main = readl_relaxed(l3_targ_stderr);
87 masterid = readl_relaxed(l3_targ_mstaddr);
Santosh Shilimkar2722e562011-03-07 20:53:10 +053088
omar ramirez35f7b962011-04-18 16:39:42 +000089 switch (std_err_main & CUSTOM_ERROR) {
Santosh Shilimkar2722e562011-03-07 20:53:10 +053090 case STANDARD_ERROR:
sricharan551a9fa2011-09-07 17:25:16 +053091 target_name =
Todd Poynor342fd142011-08-24 19:11:39 +053092 l3_targ_inst_name[i][err_src];
sricharan551a9fa2011-09-07 17:25:16 +053093 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
94 target_name,
Nishanth Menon9e224c82014-04-11 11:21:47 -050095 readl_relaxed(l3_targ_slvofslsb));
Santosh Shilimkar2722e562011-03-07 20:53:10 +053096 /* clear the std error log*/
97 clear = std_err_main | CLEAR_STDERR_LOG;
Nishanth Menon9e224c82014-04-11 11:21:47 -050098 writel_relaxed(clear, l3_targ_stderr);
Santosh Shilimkar2722e562011-03-07 20:53:10 +053099 break;
100
101 case CUSTOM_ERROR:
sricharan551a9fa2011-09-07 17:25:16 +0530102 target_name =
Todd Poynor342fd142011-08-24 19:11:39 +0530103 l3_targ_inst_name[i][err_src];
sricharan551a9fa2011-09-07 17:25:16 +0530104 for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
105 if (masterid == l3_masters[k].id)
106 master_name =
107 l3_masters[k].name;
108 }
109 WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
110 master_name, target_name);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530111 /* clear the std error log*/
112 clear = std_err_main | CLEAR_STDERR_LOG;
Nishanth Menon9e224c82014-04-11 11:21:47 -0500113 writel_relaxed(clear, l3_targ_stderr);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530114 break;
115
116 default:
117 /* Nothing to be handled here as of now */
118 break;
119 }
120 /* Error found so break the for loop */
121 break;
122 }
123 }
124 return IRQ_HANDLED;
125}
126
Sricharan Rc10d5c92014-04-11 13:09:36 -0500127static int omap_l3_probe(struct platform_device *pdev)
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530128{
Sricharan Rc10d5c92014-04-11 13:09:36 -0500129 static struct omap_l3 *l3;
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300130 int ret, i;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530131
Peter Ujfalusibae74512014-04-01 16:23:46 +0300132 l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530133 if (!l3)
omar ramirez7529b702011-04-18 16:39:41 +0000134 return -ENOMEM;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530135
Nishanth Menonca6a3492014-04-11 12:04:01 -0500136 l3->dev = &pdev->dev;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530137 platform_set_drvdata(pdev, l3);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530138
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300139 /* Get mem resources */
140 for (i = 0; i < L3_MODULES; i++) {
141 struct resource *res = platform_get_resource(pdev,
142 IORESOURCE_MEM, i);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530143
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300144 l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
145 if (IS_ERR(l3->l3_base[i])) {
Nishanth Menonca6a3492014-04-11 12:04:01 -0500146 dev_err(l3->dev, "ioremap %d failed\n", i);
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300147 return PTR_ERR(l3->l3_base[i]);
148 }
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530149 }
150
151 /*
152 * Setup interrupt Handlers
153 */
Todd Poynorc1df2dc2011-08-29 17:42:23 +0530154 l3->debug_irq = platform_get_irq(pdev, 0);
Nishanth Menonca6a3492014-04-11 12:04:01 -0500155 ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
Peter Ujfalusia0ef78f2014-04-01 16:23:48 +0300156 IRQF_DISABLED, "l3-dbg-irq", l3);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530157 if (ret) {
Nishanth Menonca6a3492014-04-11 12:04:01 -0500158 dev_err(l3->dev, "request_irq failed for %d\n",
Peter Ujfalusiae225982014-04-01 16:23:50 +0300159 l3->debug_irq);
Peter Ujfalusi56c4a022014-04-01 16:23:47 +0300160 return ret;
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530161 }
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530162
Todd Poynorc1df2dc2011-08-29 17:42:23 +0530163 l3->app_irq = platform_get_irq(pdev, 1);
Nishanth Menonca6a3492014-04-11 12:04:01 -0500164 ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
Peter Ujfalusia0ef78f2014-04-01 16:23:48 +0300165 IRQF_DISABLED, "l3-app-irq", l3);
166 if (ret)
Nishanth Menonca6a3492014-04-11 12:04:01 -0500167 dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530168
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530169 return ret;
170}
171
Benoit Coussond039c5b2011-08-12 13:52:50 +0200172#if defined(CONFIG_OF)
173static const struct of_device_id l3_noc_match[] = {
174 {.compatible = "ti,omap4-l3-noc", },
175 {},
Govindraj.R8770b072011-11-23 14:45:37 -0800176};
Benoit Coussond039c5b2011-08-12 13:52:50 +0200177MODULE_DEVICE_TABLE(of, l3_noc_match);
178#else
179#define l3_noc_match NULL
180#endif
181
Sricharan Rc10d5c92014-04-11 13:09:36 -0500182static struct platform_driver omap_l3_driver = {
183 .probe = omap_l3_probe,
Benoit Coussond039c5b2011-08-12 13:52:50 +0200184 .driver = {
185 .name = "omap_l3_noc",
186 .owner = THIS_MODULE,
187 .of_match_table = l3_noc_match,
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530188 },
189};
190
Sricharan Rc10d5c92014-04-11 13:09:36 -0500191static int __init omap_l3_init(void)
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530192{
Sricharan Rc10d5c92014-04-11 13:09:36 -0500193 return platform_driver_register(&omap_l3_driver);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530194}
Sricharan Rc10d5c92014-04-11 13:09:36 -0500195postcore_initcall_sync(omap_l3_init);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530196
Sricharan Rc10d5c92014-04-11 13:09:36 -0500197static void __exit omap_l3_exit(void)
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530198{
Sricharan Rc10d5c92014-04-11 13:09:36 -0500199 platform_driver_unregister(&omap_l3_driver);
Santosh Shilimkar2722e562011-03-07 20:53:10 +0530200}
Sricharan Rc10d5c92014-04-11 13:09:36 -0500201module_exit(omap_l3_exit);