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Fabio Estevam5dda6152018-05-01 12:47:29 -03001// SPDX-License-Identifier: GPL-2.0
Fabio Estevam2688a322013-07-16 14:40:29 -03002/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam2688a322013-07-16 14:40:29 -03006 */
7
Dong Aisheng89c1a8cf2015-07-22 20:53:02 +08008#include <dt-bindings/gpio/gpio.h>
9
Fabio Estevam2688a322013-07-16 14:40:29 -030010/ {
Tuomas Tynkkynen3ca5a852018-08-21 00:07:18 +030011 chosen {
12 stdout-path = &uart1;
13 };
14
Fabio Estevam2688a322013-07-16 14:40:29 -030015 sound {
16 compatible = "fsl,imx6-wandboard-sgtl5000",
17 "fsl,imx-audio-sgtl5000";
18 model = "imx6-wandboard-sgtl5000";
19 ssi-controller = <&ssi1>;
20 audio-codec = <&codec>;
21 audio-routing =
22 "MIC_IN", "Mic Jack",
23 "Mic Jack", "Mic Bias",
24 "Headphone Jack", "HP_OUT";
25 mux-int-port = <1>;
26 mux-ext-port = <3>;
27 };
Fabio Estevamc9d96df2013-09-02 23:51:41 -030028
29 sound-spdif {
30 compatible = "fsl,imx-audio-spdif";
31 model = "imx-spdif";
32 spdif-controller = <&spdif>;
33 spdif-out;
34 };
Alexander Kurz9d1b8412018-05-29 06:20:18 +000035
Ezequiel Garcia8ad2d1dc2019-07-22 10:45:45 -030036 reg_1p5v: regulator-1p5v {
37 compatible = "regulator-fixed";
38 regulator-name = "1P5V";
39 regulator-min-microvolt = <1500000>;
40 regulator-max-microvolt = <1500000>;
41 regulator-always-on;
42 };
43
44 reg_1p8v: regulator-1p8v {
45 compatible = "regulator-fixed";
46 regulator-name = "1P8V";
47 regulator-min-microvolt = <1800000>;
48 regulator-max-microvolt = <1800000>;
49 regulator-always-on;
50 };
51
52 reg_2p8v: regulator-2p8v {
53 compatible = "regulator-fixed";
54 regulator-name = "2P8V";
55 regulator-min-microvolt = <2800000>;
56 regulator-max-microvolt = <2800000>;
57 regulator-always-on;
58 };
59
Alexander Kurz9d1b8412018-05-29 06:20:18 +000060 reg_2p5v: regulator-2p5v {
61 compatible = "regulator-fixed";
62 regulator-name = "2P5V";
63 regulator-min-microvolt = <2500000>;
64 regulator-max-microvolt = <2500000>;
65 regulator-always-on;
66 };
67
68 reg_3p3v: regulator-3p3v {
69 compatible = "regulator-fixed";
70 regulator-name = "3P3V";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 regulator-always-on;
74 };
Alexander Kurze732f6d2018-05-29 06:20:20 +000075
76 reg_usb_otg_vbus: regulator-usbotgvbus {
77 compatible = "regulator-fixed";
78 regulator-name = "usb_otg_vbus";
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5000000>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_usbotgvbus>;
83 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
84 };
Fabio Estevam2688a322013-07-16 14:40:29 -030085};
86
87&audmux {
88 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +080089 pinctrl-0 = <&pinctrl_audmux>;
Fabio Estevam2688a322013-07-16 14:40:29 -030090 status = "okay";
91};
92
Fabio Estevamfed687c2014-04-22 11:26:22 -030093&hdmi {
94 ddc-i2c-bus = <&i2c1>;
95 status = "okay";
96};
97
98&i2c1 {
99 clock-frequency = <100000>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c1>;
102 status = "okay";
103};
104
Fabio Estevam2688a322013-07-16 14:40:29 -0300105&i2c2 {
106 clock-frequency = <100000>;
107 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800108 pinctrl-0 = <&pinctrl_i2c2>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300109 status = "okay";
110
Rob Herring8dccafa2017-10-13 12:54:51 -0500111 codec: sgtl5000@a {
Fabio Estevam6e1386b2018-03-14 17:36:26 -0300112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_mclk>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300114 compatible = "fsl,sgtl5000";
115 reg = <0x0a>;
Fabio Estevamb26a68c2016-04-26 22:28:29 -0300116 clocks = <&clks IMX6QDL_CLK_CKO>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300117 VDDA-supply = <&reg_2p5v>;
118 VDDIO-supply = <&reg_3p3v>;
Fabio Estevam79935912017-05-14 11:50:50 -0300119 lrclk-strength = <3>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300120 };
Ezequiel Garcia8ad2d1dc2019-07-22 10:45:45 -0300121
122 camera@3c {
123 compatible = "ovti,ov5645";
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_ov5645>;
126 reg = <0x3c>;
127 clocks = <&clks IMX6QDL_CLK_CKO2>;
128 clock-names = "xclk";
129 clock-frequency = <24000000>;
130 vdddo-supply = <&reg_1p8v>;
131 vdda-supply = <&reg_2p8v>;
132 vddd-supply = <&reg_1p5v>;
133 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
134 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
135
136 port {
137 ov5645_to_mipi_csi2: endpoint {
138 remote-endpoint = <&mipi_csi2_in>;
139 clock-lanes = <0>;
140 data-lanes = <1 2>;
141 };
142 };
143 };
Fabio Estevam2688a322013-07-16 14:40:29 -0300144};
145
146&iomuxc {
147 pinctrl-names = "default";
Fabio Estevam2688a322013-07-16 14:40:29 -0300148
Shawn Guo817c27a2013-10-23 15:36:09 +0800149 imx6qdl-wandboard {
Shawn Guo817c27a2013-10-23 15:36:09 +0800150
151 pinctrl_audmux: audmuxgrp {
152 fsl,pins = <
Nicolin Chen77112dd2014-02-08 10:14:28 +0800153 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
154 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
155 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
156 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800157 >;
158 };
159
160 pinctrl_enet: enetgrp {
161 fsl,pins = <
162 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
163 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
Uwe Kleine-Königc007b3a2016-07-08 23:22:54 +0200164 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
165 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
166 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
167 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
168 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
169 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
Shawn Guo817c27a2013-10-23 15:36:09 +0800170 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
Uwe Kleine-Königc007b3a2016-07-08 23:22:54 +0200171 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
172 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
173 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
174 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
175 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
176 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
Shawn Guo817c27a2013-10-23 15:36:09 +0800177 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
178 >;
179 };
180
Fabio Estevamfed687c2014-04-22 11:26:22 -0300181 pinctrl_i2c1: i2c1grp {
182 fsl,pins = <
Jagan Teki05c183e2016-10-14 15:09:28 +0530183 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
184 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
Fabio Estevamfed687c2014-04-22 11:26:22 -0300185 >;
186 };
187
Shawn Guo817c27a2013-10-23 15:36:09 +0800188 pinctrl_i2c2: i2c2grp {
189 fsl,pins = <
190 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
191 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
192 >;
193 };
194
Fabio Estevam6e1386b2018-03-14 17:36:26 -0300195 pinctrl_mclk: mclkgrp {
196 fsl,pins = <
197 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
198 >;
199 };
200
Ezequiel Garcia8ad2d1dc2019-07-22 10:45:45 -0300201 pinctrl_ov5645: ov5645grp {
202 fsl,pins = <
203 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
204 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
205 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
206 >;
207 };
208
Shawn Guo817c27a2013-10-23 15:36:09 +0800209 pinctrl_spdif: spdifgrp {
210 fsl,pins = <
211 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
212 >;
213 };
214
215 pinctrl_uart1: uart1grp {
216 fsl,pins = <
217 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
218 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
219 >;
220 };
221
222 pinctrl_uart3: uart3grp {
223 fsl,pins = <
224 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
225 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
226 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
227 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
228 >;
229 };
230
231 pinctrl_usbotg: usbotggrp {
232 fsl,pins = <
233 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
234 >;
235 };
236
Alexander Kurze732f6d2018-05-29 06:20:20 +0000237 pinctrl_usbotgvbus: usbotgvbusgrp {
238 fsl,pins = <
239 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
240 >;
241 };
242
Shawn Guo817c27a2013-10-23 15:36:09 +0800243 pinctrl_usdhc1: usdhc1grp {
244 fsl,pins = <
245 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
246 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
247 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
248 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
249 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
250 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
251 >;
252 };
253
254 pinctrl_usdhc2: usdhc2grp {
255 fsl,pins = <
256 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
257 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
258 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
259 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
260 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
261 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
262 >;
263 };
264
265 pinctrl_usdhc3: usdhc3grp {
266 fsl,pins = <
267 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
268 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
269 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
270 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
271 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
272 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
273 >;
274 };
Fabio Estevam2688a322013-07-16 14:40:29 -0300275 };
276};
277
278&fec {
279 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800280 pinctrl-0 = <&pinctrl_enet>;
Fabio Estevam0672d222019-04-03 19:12:41 -0300281 phy-mode = "rgmii-id";
Anatolij Gustschin77591e42019-09-21 14:07:36 +0200282 phy-handle = <&ethphy>;
Fabio Estevam12de44f2017-06-04 14:31:15 -0300283 phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300284 status = "okay";
Anatolij Gustschin77591e42019-09-21 14:07:36 +0200285
286 mdio {
287 #address-cells = <1>;
288 #size-cells = <0>;
289
290 ethphy: ethernet-phy@1 {
291 reg = <1>;
292 };
293 };
Fabio Estevam2688a322013-07-16 14:40:29 -0300294};
295
Ezequiel Garcia8ad2d1dc2019-07-22 10:45:45 -0300296&mipi_csi {
297 status = "okay";
298
299 port@0 {
300 reg = <0>;
301
302 mipi_csi2_in: endpoint {
303 remote-endpoint = <&ov5645_to_mipi_csi2>;
304 clock-lanes = <0>;
305 data-lanes = <1 2>;
306 };
307 };
308};
309
Fabio Estevamc9d96df2013-09-02 23:51:41 -0300310&spdif {
311 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800312 pinctrl-0 = <&pinctrl_spdif>;
Fabio Estevamc9d96df2013-09-02 23:51:41 -0300313 status = "okay";
314};
315
Fabio Estevam2688a322013-07-16 14:40:29 -0300316&ssi1 {
Fabio Estevam2688a322013-07-16 14:40:29 -0300317 status = "okay";
318};
319
320&uart1 {
321 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800322 pinctrl-0 = <&pinctrl_uart1>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300323 status = "okay";
324};
325
326&uart3 {
327 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800328 pinctrl-0 = <&pinctrl_uart3>;
Geert Uytterhoeven2e7c4162016-05-31 16:31:51 +0200329 uart-has-rtscts;
Fabio Estevam2688a322013-07-16 14:40:29 -0300330 status = "okay";
331};
332
333&usbh1 {
334 status = "okay";
335};
336
Fabio Estevame9ac8902013-08-21 10:27:02 -0300337&usbotg {
Alexander Kurze732f6d2018-05-29 06:20:20 +0000338 vbus-supply = <&reg_usb_otg_vbus>;
Fabio Estevame9ac8902013-08-21 10:27:02 -0300339 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800340 pinctrl-0 = <&pinctrl_usbotg>;
Fabio Estevame9ac8902013-08-21 10:27:02 -0300341 disable-over-current;
Alexander Kurze732f6d2018-05-29 06:20:20 +0000342 dr_mode = "otg";
Fabio Estevame9ac8902013-08-21 10:27:02 -0300343 status = "okay";
344};
345
Fabio Estevam2688a322013-07-16 14:40:29 -0300346&usdhc1 {
347 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800348 pinctrl-0 = <&pinctrl_usdhc1>;
Dong Aisheng89c1a8cf2015-07-22 20:53:02 +0800349 cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300350 status = "okay";
351};
352
Fabio Estevam2688a322013-07-16 14:40:29 -0300353&usdhc3 {
354 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800355 pinctrl-0 = <&pinctrl_usdhc3>;
Dong Aisheng89c1a8cf2015-07-22 20:53:02 +0800356 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300357 status = "okay";
358};