Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 1 | /* |
| 2 | * AXP20x regulators driver. |
| 3 | * |
| 4 | * Copyright (C) 2013 Carlo Caione <carlo@caione.org> |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General |
| 7 | * Public License. See the file "COPYING" in the main directory of this |
| 8 | * archive for more details. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/of_device.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/regmap.h> |
| 23 | #include <linux/mfd/axp20x.h> |
| 24 | #include <linux/regulator/driver.h> |
| 25 | #include <linux/regulator/of_regulator.h> |
| 26 | |
| 27 | #define AXP20X_IO_ENABLED 0x03 |
| 28 | #define AXP20X_IO_DISABLED 0x07 |
| 29 | |
Chen-Yu Tsai | 3cb99e2 | 2015-12-22 17:08:06 +0800 | [diff] [blame] | 30 | #define AXP22X_IO_ENABLED 0x03 |
| 31 | #define AXP22X_IO_DISABLED 0x04 |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 32 | |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 33 | #define AXP20X_WORKMODE_DCDC2_MASK BIT(2) |
| 34 | #define AXP20X_WORKMODE_DCDC3_MASK BIT(1) |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 35 | #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT(x) |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 36 | |
| 37 | #define AXP20X_FREQ_DCDC_MASK 0x0f |
| 38 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 39 | #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
| 40 | _vmask, _ereg, _emask, _enable_val, _disable_val) \ |
| 41 | [_family##_##_id] = { \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 42 | .name = #_id, \ |
| 43 | .supply_name = (_supply), \ |
Chen-Yu Tsai | 880fe82 | 2015-01-10 00:23:43 +0800 | [diff] [blame] | 44 | .of_match = of_match_ptr(_match), \ |
| 45 | .regulators_node = of_match_ptr("regulators"), \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 46 | .type = REGULATOR_VOLTAGE, \ |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 47 | .id = _family##_##_id, \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 48 | .n_voltages = (((_max) - (_min)) / (_step) + 1), \ |
| 49 | .owner = THIS_MODULE, \ |
| 50 | .min_uV = (_min) * 1000, \ |
| 51 | .uV_step = (_step) * 1000, \ |
| 52 | .vsel_reg = (_vreg), \ |
| 53 | .vsel_mask = (_vmask), \ |
| 54 | .enable_reg = (_ereg), \ |
| 55 | .enable_mask = (_emask), \ |
| 56 | .enable_val = (_enable_val), \ |
| 57 | .disable_val = (_disable_val), \ |
| 58 | .ops = &axp20x_ops, \ |
| 59 | } |
| 60 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 61 | #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
| 62 | _vmask, _ereg, _emask) \ |
| 63 | [_family##_##_id] = { \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 64 | .name = #_id, \ |
| 65 | .supply_name = (_supply), \ |
Chen-Yu Tsai | 880fe82 | 2015-01-10 00:23:43 +0800 | [diff] [blame] | 66 | .of_match = of_match_ptr(_match), \ |
| 67 | .regulators_node = of_match_ptr("regulators"), \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 68 | .type = REGULATOR_VOLTAGE, \ |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 69 | .id = _family##_##_id, \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 70 | .n_voltages = (((_max) - (_min)) / (_step) + 1), \ |
| 71 | .owner = THIS_MODULE, \ |
| 72 | .min_uV = (_min) * 1000, \ |
| 73 | .uV_step = (_step) * 1000, \ |
| 74 | .vsel_reg = (_vreg), \ |
| 75 | .vsel_mask = (_vmask), \ |
| 76 | .enable_reg = (_ereg), \ |
| 77 | .enable_mask = (_emask), \ |
| 78 | .ops = &axp20x_ops, \ |
| 79 | } |
| 80 | |
Chen-Yu Tsai | 94c3904 | 2016-02-02 18:27:37 +0800 | [diff] [blame^] | 81 | #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \ |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 82 | [_family##_##_id] = { \ |
| 83 | .name = #_id, \ |
| 84 | .supply_name = (_supply), \ |
| 85 | .of_match = of_match_ptr(_match), \ |
| 86 | .regulators_node = of_match_ptr("regulators"), \ |
| 87 | .type = REGULATOR_VOLTAGE, \ |
| 88 | .id = _family##_##_id, \ |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 89 | .owner = THIS_MODULE, \ |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 90 | .enable_reg = (_ereg), \ |
| 91 | .enable_mask = (_emask), \ |
| 92 | .ops = &axp20x_ops_sw, \ |
| 93 | } |
| 94 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 95 | #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \ |
| 96 | [_family##_##_id] = { \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 97 | .name = #_id, \ |
| 98 | .supply_name = (_supply), \ |
Chen-Yu Tsai | 880fe82 | 2015-01-10 00:23:43 +0800 | [diff] [blame] | 99 | .of_match = of_match_ptr(_match), \ |
| 100 | .regulators_node = of_match_ptr("regulators"), \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 101 | .type = REGULATOR_VOLTAGE, \ |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 102 | .id = _family##_##_id, \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 103 | .n_voltages = 1, \ |
| 104 | .owner = THIS_MODULE, \ |
| 105 | .min_uV = (_volt) * 1000, \ |
| 106 | .ops = &axp20x_ops_fixed \ |
| 107 | } |
| 108 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 109 | #define AXP_DESC_TABLE(_family, _id, _match, _supply, _table, _vreg, _vmask, \ |
| 110 | _ereg, _emask) \ |
| 111 | [_family##_##_id] = { \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 112 | .name = #_id, \ |
| 113 | .supply_name = (_supply), \ |
Chen-Yu Tsai | 880fe82 | 2015-01-10 00:23:43 +0800 | [diff] [blame] | 114 | .of_match = of_match_ptr(_match), \ |
| 115 | .regulators_node = of_match_ptr("regulators"), \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 116 | .type = REGULATOR_VOLTAGE, \ |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 117 | .id = _family##_##_id, \ |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 118 | .n_voltages = ARRAY_SIZE(_table), \ |
| 119 | .owner = THIS_MODULE, \ |
| 120 | .vsel_reg = (_vreg), \ |
| 121 | .vsel_mask = (_vmask), \ |
| 122 | .enable_reg = (_ereg), \ |
| 123 | .enable_mask = (_emask), \ |
| 124 | .volt_table = (_table), \ |
| 125 | .ops = &axp20x_ops_table, \ |
| 126 | } |
| 127 | |
| 128 | static const int axp20x_ldo4_data[] = { 1250000, 1300000, 1400000, 1500000, 1600000, |
| 129 | 1700000, 1800000, 1900000, 2000000, 2500000, |
| 130 | 2700000, 2800000, 3000000, 3100000, 3200000, |
| 131 | 3300000 }; |
| 132 | |
| 133 | static struct regulator_ops axp20x_ops_fixed = { |
| 134 | .list_voltage = regulator_list_voltage_linear, |
| 135 | }; |
| 136 | |
| 137 | static struct regulator_ops axp20x_ops_table = { |
| 138 | .set_voltage_sel = regulator_set_voltage_sel_regmap, |
| 139 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
| 140 | .list_voltage = regulator_list_voltage_table, |
Axel Lin | b887035 | 2014-04-15 19:58:42 +0800 | [diff] [blame] | 141 | .map_voltage = regulator_map_voltage_ascend, |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 142 | .enable = regulator_enable_regmap, |
| 143 | .disable = regulator_disable_regmap, |
| 144 | .is_enabled = regulator_is_enabled_regmap, |
| 145 | }; |
| 146 | |
| 147 | static struct regulator_ops axp20x_ops = { |
| 148 | .set_voltage_sel = regulator_set_voltage_sel_regmap, |
| 149 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
| 150 | .list_voltage = regulator_list_voltage_linear, |
| 151 | .enable = regulator_enable_regmap, |
| 152 | .disable = regulator_disable_regmap, |
| 153 | .is_enabled = regulator_is_enabled_regmap, |
| 154 | }; |
| 155 | |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 156 | static struct regulator_ops axp20x_ops_sw = { |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 157 | .enable = regulator_enable_regmap, |
| 158 | .disable = regulator_disable_regmap, |
| 159 | .is_enabled = regulator_is_enabled_regmap, |
| 160 | }; |
| 161 | |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 162 | static const struct regulator_desc axp20x_regulators[] = { |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 163 | AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25, |
| 164 | AXP20X_DCDC2_V_OUT, 0x3f, AXP20X_PWR_OUT_CTRL, 0x10), |
| 165 | AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25, |
| 166 | AXP20X_DCDC3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x02), |
| 167 | AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300), |
| 168 | AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100, |
| 169 | AXP20X_LDO24_V_OUT, 0xf0, AXP20X_PWR_OUT_CTRL, 0x04), |
| 170 | AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25, |
| 171 | AXP20X_LDO3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x40), |
| 172 | AXP_DESC_TABLE(AXP20X, LDO4, "ldo4", "ldo24in", axp20x_ldo4_data, |
| 173 | AXP20X_LDO24_V_OUT, 0x0f, AXP20X_PWR_OUT_CTRL, 0x08), |
| 174 | AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100, |
| 175 | AXP20X_LDO5_V_OUT, 0xf0, AXP20X_GPIO0_CTRL, 0x07, |
| 176 | AXP20X_IO_ENABLED, AXP20X_IO_DISABLED), |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 177 | }; |
| 178 | |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 179 | static const struct regulator_desc axp22x_regulators[] = { |
| 180 | AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, |
| 181 | AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)), |
| 182 | AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20, |
| 183 | AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)), |
| 184 | AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20, |
| 185 | AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)), |
| 186 | AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, |
Chen-Yu Tsai | 6b3600b | 2015-09-26 21:21:12 +0800 | [diff] [blame] | 187 | AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(4)), |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 188 | AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, |
Chen-Yu Tsai | 6b3600b | 2015-09-26 21:21:12 +0800 | [diff] [blame] | 189 | AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(5)), |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 190 | /* secondary switchable output of DCDC1 */ |
Chen-Yu Tsai | 94c3904 | 2016-02-02 18:27:37 +0800 | [diff] [blame^] | 191 | AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2, |
| 192 | BIT(7)), |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 193 | /* LDO regulator internally chained to DCDC5 */ |
Chen-Yu Tsai | 7118f19 | 2015-09-30 14:39:46 +0800 | [diff] [blame] | 194 | AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 195 | AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)), |
| 196 | AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100, |
| 197 | AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)), |
| 198 | AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100, |
| 199 | AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)), |
| 200 | AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100, |
| 201 | AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)), |
| 202 | AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100, |
| 203 | AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)), |
| 204 | AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100, |
| 205 | AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)), |
| 206 | AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100, |
| 207 | AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)), |
| 208 | AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100, |
| 209 | AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)), |
| 210 | AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100, |
| 211 | AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)), |
| 212 | AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100, |
| 213 | AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)), |
| 214 | AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100, |
| 215 | AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)), |
| 216 | AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 1800, 3300, 100, |
| 217 | AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07, |
| 218 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 219 | AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 1800, 3300, 100, |
| 220 | AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07, |
| 221 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), |
| 222 | AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000), |
| 223 | }; |
| 224 | |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 225 | static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) |
| 226 | { |
| 227 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 228 | u32 min, max, def, step; |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 229 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 230 | switch (axp20x->variant) { |
| 231 | case AXP202_ID: |
| 232 | case AXP209_ID: |
| 233 | min = 750; |
| 234 | max = 1875; |
| 235 | def = 1500; |
| 236 | step = 75; |
| 237 | break; |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 238 | case AXP221_ID: |
| 239 | min = 1800; |
| 240 | max = 4050; |
| 241 | def = 3000; |
| 242 | step = 150; |
| 243 | break; |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 244 | default: |
| 245 | dev_err(&pdev->dev, |
| 246 | "Setting DCDC frequency for unsupported AXP variant\n"); |
| 247 | return -EINVAL; |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 248 | } |
| 249 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 250 | if (dcdcfreq == 0) |
| 251 | dcdcfreq = def; |
| 252 | |
| 253 | if (dcdcfreq < min) { |
| 254 | dcdcfreq = min; |
| 255 | dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n", |
| 256 | min); |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 257 | } |
| 258 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 259 | if (dcdcfreq > max) { |
| 260 | dcdcfreq = max; |
| 261 | dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n", |
| 262 | max); |
| 263 | } |
| 264 | |
| 265 | dcdcfreq = (dcdcfreq - min) / step; |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 266 | |
| 267 | return regmap_update_bits(axp20x->regmap, AXP20X_DCDC_FREQ, |
| 268 | AXP20X_FREQ_DCDC_MASK, dcdcfreq); |
| 269 | } |
| 270 | |
| 271 | static int axp20x_regulator_parse_dt(struct platform_device *pdev) |
| 272 | { |
| 273 | struct device_node *np, *regulators; |
| 274 | int ret; |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 275 | u32 dcdcfreq = 0; |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 276 | |
| 277 | np = of_node_get(pdev->dev.parent->of_node); |
| 278 | if (!np) |
| 279 | return 0; |
| 280 | |
Boris BREZILLON | a6016c5 | 2014-05-19 10:25:30 +0200 | [diff] [blame] | 281 | regulators = of_get_child_by_name(np, "regulators"); |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 282 | if (!regulators) { |
| 283 | dev_warn(&pdev->dev, "regulators node not found\n"); |
| 284 | } else { |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 285 | of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq); |
| 286 | ret = axp20x_set_dcdc_freq(pdev, dcdcfreq); |
| 287 | if (ret < 0) { |
| 288 | dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret); |
| 289 | return ret; |
| 290 | } |
| 291 | |
| 292 | of_node_put(regulators); |
| 293 | } |
| 294 | |
| 295 | return 0; |
| 296 | } |
| 297 | |
| 298 | static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode) |
| 299 | { |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 300 | struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); |
| 301 | unsigned int mask; |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 302 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 303 | switch (axp20x->variant) { |
| 304 | case AXP202_ID: |
| 305 | case AXP209_ID: |
| 306 | if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3)) |
| 307 | return -EINVAL; |
| 308 | |
| 309 | mask = AXP20X_WORKMODE_DCDC2_MASK; |
| 310 | if (id == AXP20X_DCDC3) |
| 311 | mask = AXP20X_WORKMODE_DCDC3_MASK; |
| 312 | |
| 313 | workmode <<= ffs(mask) - 1; |
| 314 | break; |
| 315 | |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 316 | case AXP221_ID: |
| 317 | if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5) |
| 318 | return -EINVAL; |
| 319 | |
| 320 | mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1); |
| 321 | workmode <<= id - AXP22X_DCDC1; |
| 322 | break; |
| 323 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 324 | default: |
| 325 | /* should not happen */ |
| 326 | WARN_ON(1); |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 327 | return -EINVAL; |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 328 | } |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 329 | |
| 330 | return regmap_update_bits(rdev->regmap, AXP20X_DCDC_MODE, mask, workmode); |
| 331 | } |
| 332 | |
| 333 | static int axp20x_regulator_probe(struct platform_device *pdev) |
| 334 | { |
| 335 | struct regulator_dev *rdev; |
| 336 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 337 | const struct regulator_desc *regulators; |
Chen-Yu Tsai | 765e802 | 2015-01-10 00:23:44 +0800 | [diff] [blame] | 338 | struct regulator_config config = { |
| 339 | .dev = pdev->dev.parent, |
| 340 | .regmap = axp20x->regmap, |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 341 | .driver_data = axp20x, |
Chen-Yu Tsai | 765e802 | 2015-01-10 00:23:44 +0800 | [diff] [blame] | 342 | }; |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 343 | int ret, i, nregulators; |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 344 | u32 workmode; |
Chen-Yu Tsai | 7118f19 | 2015-09-30 14:39:46 +0800 | [diff] [blame] | 345 | const char *axp22x_dc1_name = axp22x_regulators[AXP22X_DCDC1].name; |
| 346 | const char *axp22x_dc5_name = axp22x_regulators[AXP22X_DCDC5].name; |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 347 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 348 | switch (axp20x->variant) { |
| 349 | case AXP202_ID: |
| 350 | case AXP209_ID: |
| 351 | regulators = axp20x_regulators; |
| 352 | nregulators = AXP20X_REG_ID_MAX; |
| 353 | break; |
Boris BREZILLON | 1b82b4e | 2015-04-10 12:09:04 +0800 | [diff] [blame] | 354 | case AXP221_ID: |
| 355 | regulators = axp22x_regulators; |
| 356 | nregulators = AXP22X_REG_ID_MAX; |
| 357 | break; |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 358 | default: |
| 359 | dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n", |
| 360 | axp20x->variant); |
| 361 | return -EINVAL; |
| 362 | } |
| 363 | |
Chen-Yu Tsai | 765e802 | 2015-01-10 00:23:44 +0800 | [diff] [blame] | 364 | /* This only sets the dcdc freq. Ignore any errors */ |
| 365 | axp20x_regulator_parse_dt(pdev); |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 366 | |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 367 | for (i = 0; i < nregulators; i++) { |
Chen-Yu Tsai | 7118f19 | 2015-09-30 14:39:46 +0800 | [diff] [blame] | 368 | const struct regulator_desc *desc = ®ulators[i]; |
| 369 | struct regulator_desc *new_desc; |
| 370 | |
| 371 | /* |
| 372 | * Regulators DC1SW and DC5LDO are connected internally, |
| 373 | * so we have to handle their supply names separately. |
| 374 | * |
| 375 | * We always register the regulators in proper sequence, |
| 376 | * so the supply names are correctly read. See the last |
| 377 | * part of this loop to see where we save the DT defined |
| 378 | * name. |
| 379 | */ |
| 380 | if (regulators == axp22x_regulators) { |
| 381 | if (i == AXP22X_DC1SW) { |
| 382 | new_desc = devm_kzalloc(&pdev->dev, |
| 383 | sizeof(*desc), |
| 384 | GFP_KERNEL); |
| 385 | *new_desc = regulators[i]; |
| 386 | new_desc->supply_name = axp22x_dc1_name; |
| 387 | desc = new_desc; |
| 388 | } else if (i == AXP22X_DC5LDO) { |
| 389 | new_desc = devm_kzalloc(&pdev->dev, |
| 390 | sizeof(*desc), |
| 391 | GFP_KERNEL); |
| 392 | *new_desc = regulators[i]; |
| 393 | new_desc->supply_name = axp22x_dc5_name; |
| 394 | desc = new_desc; |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | rdev = devm_regulator_register(&pdev->dev, desc, &config); |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 399 | if (IS_ERR(rdev)) { |
| 400 | dev_err(&pdev->dev, "Failed to register %s\n", |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 401 | regulators[i].name); |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 402 | |
| 403 | return PTR_ERR(rdev); |
| 404 | } |
| 405 | |
Chen-Yu Tsai | 765e802 | 2015-01-10 00:23:44 +0800 | [diff] [blame] | 406 | ret = of_property_read_u32(rdev->dev.of_node, |
| 407 | "x-powers,dcdc-workmode", |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 408 | &workmode); |
| 409 | if (!ret) { |
| 410 | if (axp20x_set_dcdc_workmode(rdev, i, workmode)) |
| 411 | dev_err(&pdev->dev, "Failed to set workmode on %s\n", |
Boris BREZILLON | 866bd95 | 2015-04-10 12:09:03 +0800 | [diff] [blame] | 412 | rdev->desc->name); |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 413 | } |
Chen-Yu Tsai | 7118f19 | 2015-09-30 14:39:46 +0800 | [diff] [blame] | 414 | |
| 415 | /* |
| 416 | * Save AXP22X DCDC1 / DCDC5 regulator names for later. |
| 417 | */ |
| 418 | if (regulators == axp22x_regulators) { |
| 419 | /* Can we use rdev->constraints->name instead? */ |
| 420 | if (i == AXP22X_DCDC1) |
| 421 | of_property_read_string(rdev->dev.of_node, |
| 422 | "regulator-name", |
| 423 | &axp22x_dc1_name); |
| 424 | else if (i == AXP22X_DCDC5) |
| 425 | of_property_read_string(rdev->dev.of_node, |
| 426 | "regulator-name", |
| 427 | &axp22x_dc5_name); |
| 428 | } |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 429 | } |
| 430 | |
| 431 | return 0; |
| 432 | } |
| 433 | |
| 434 | static struct platform_driver axp20x_regulator_driver = { |
| 435 | .probe = axp20x_regulator_probe, |
| 436 | .driver = { |
| 437 | .name = "axp20x-regulator", |
Carlo Caione | dfe7a1b | 2014-04-11 11:38:10 +0200 | [diff] [blame] | 438 | }, |
| 439 | }; |
| 440 | |
| 441 | module_platform_driver(axp20x_regulator_driver); |
| 442 | |
| 443 | MODULE_LICENSE("GPL v2"); |
| 444 | MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); |
| 445 | MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC"); |
Ian Campbell | d4ea7d8 | 2015-08-01 18:13:25 +0100 | [diff] [blame] | 446 | MODULE_ALIAS("platform:axp20x-regulator"); |