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Thomas Gleixner97fb5e82019-05-29 07:17:58 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Govind Singhcc53aab2018-10-11 13:16:01 +03002/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
Lina Iyer2ce76a62015-03-02 16:30:29 -07003 * Copyright (C) 2015 Linaro Ltd.
Stephen Boyd2a1eb582010-08-27 10:01:23 -07004 */
Kumar Gala4de43472015-02-04 16:30:46 -06005#ifndef __QCOM_SCM_H
6#define __QCOM_SCM_H
Stephen Boyd2a1eb582010-08-27 10:01:23 -07007
Fabio Estevam20766072018-12-26 10:06:19 -02008#include <linux/err.h>
Jordan Crouse29ff62f2017-12-04 10:18:46 -07009#include <linux/types.h>
10#include <linux/cpumask.h>
11
Stanimir Varbanove1279912016-11-22 19:03:09 +020012#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
13#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
14#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
jilai wang9626b692015-04-10 16:15:59 -040015#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
16
17struct qcom_scm_hdcp_req {
18 u32 addr;
19 u32 val;
20};
21
Avaneesh Kumar Dwivedid82bd352017-10-24 21:22:24 +053022struct qcom_scm_vmperm {
23 int vmid;
24 int perm;
25};
26
27#define QCOM_SCM_VMID_HLOS 0x3
28#define QCOM_SCM_VMID_MSS_MSA 0xF
Govind Singhcc53aab2018-10-11 13:16:01 +030029#define QCOM_SCM_VMID_WLAN 0x18
30#define QCOM_SCM_VMID_WLAN_CE 0x19
Avaneesh Kumar Dwivedid82bd352017-10-24 21:22:24 +053031#define QCOM_SCM_PERM_READ 0x4
32#define QCOM_SCM_PERM_WRITE 0x2
33#define QCOM_SCM_PERM_EXEC 0x1
34#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
35#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
36
Stanimir Varbanove1279912016-11-22 19:03:09 +020037#if IS_ENABLED(CONFIG_QCOM_SCM)
38extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
39extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
Rob Clark2d3c2772015-09-29 15:48:55 -040040extern bool qcom_scm_is_available(void);
jilai wang9626b692015-04-10 16:15:59 -040041extern bool qcom_scm_hdcp_available(void);
42extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
Stanimir Varbanove1279912016-11-22 19:03:09 +020043 u32 *resp);
Bjorn Anderssonf01e90f2015-09-23 12:56:12 -070044extern bool qcom_scm_pas_supported(u32 peripheral);
45extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
Stanimir Varbanove1279912016-11-22 19:03:09 +020046 size_t size);
Bjorn Anderssonf01e90f2015-09-23 12:56:12 -070047extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
Stanimir Varbanove1279912016-11-22 19:03:09 +020048 phys_addr_t size);
Bjorn Anderssonf01e90f2015-09-23 12:56:12 -070049extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
50extern int qcom_scm_pas_shutdown(u32 peripheral);
Avaneesh Kumar Dwivedid82bd352017-10-24 21:22:24 +053051extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
52 unsigned int *src, struct qcom_scm_vmperm *newvm,
53 int dest_cnt);
Lina Iyer767b0232015-03-02 16:30:30 -070054extern void qcom_scm_cpu_power_down(u32 flags);
Kumar Gala4de43472015-02-04 16:30:46 -060055extern u32 qcom_scm_get_version(void);
Andy Grossa811b422017-01-16 23:24:15 -060056extern int qcom_scm_set_remote_state(u32 state, u32 id);
Rob Clarka2c680c2017-03-14 11:18:03 -040057extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
Stanimir Varbanovb182cc42017-03-14 11:18:04 -040058extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
59extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
Bjorn Andersson4e659db2017-08-14 15:46:17 -070060extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
61extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
Stanimir Varbanove1279912016-11-22 19:03:09 +020062#else
Jonathan Marek16ad9502018-11-21 21:32:25 -050063
64#include <linux/errno.h>
65
Stanimir Varbanove1279912016-11-22 19:03:09 +020066static inline
67int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
68{
69 return -ENODEV;
70}
71static inline
72int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
73{
74 return -ENODEV;
75}
76static inline bool qcom_scm_is_available(void) { return false; }
77static inline bool qcom_scm_hdcp_available(void) { return false; }
78static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
79 u32 *resp) { return -ENODEV; }
80static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
81static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
82 size_t size) { return -ENODEV; }
83static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
84 phys_addr_t size) { return -ENODEV; }
85static inline int
86qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
87static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
Niklas Cassela0b15612018-06-12 15:23:13 +020088static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
89 unsigned int *src,
90 struct qcom_scm_vmperm *newvm,
91 int dest_cnt) { return -ENODEV; }
Stanimir Varbanove1279912016-11-22 19:03:09 +020092static inline void qcom_scm_cpu_power_down(u32 flags) {}
93static inline u32 qcom_scm_get_version(void) { return 0; }
Andy Grossa811b422017-01-16 23:24:15 -060094static inline u32
95qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
Rob Clarka2c680c2017-03-14 11:18:03 -040096static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
Stanimir Varbanovb182cc42017-03-14 11:18:04 -040097static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
98static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
Bjorn Andersson4e659db2017-08-14 15:46:17 -070099static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
100static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
Stanimir Varbanove1279912016-11-22 19:03:09 +0200101#endif
Stephen Boyd2a1eb582010-08-27 10:01:23 -0700102#endif