| Lennert Buytenhek | 9dd0b19 | 2008-03-27 14:51:41 -0400 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-arm/arch-orion5x/orion5x.h |
| 3 | * |
| 4 | * Generic definitions of Orion SoC flavors: |
| 5 | * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. |
| 6 | * |
| 7 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #ifndef __ASM_ARCH_ORION5X_H |
| 15 | #define __ASM_ARCH_ORION5X_H |
| 16 | |
| 17 | /***************************************************************************** |
| 18 | * Orion Address Maps |
| 19 | * |
| 20 | * phys |
| 21 | * e0000000 PCIe MEM space |
| 22 | * e8000000 PCI MEM space |
| 23 | * f0000000 PCIe WA space (Orion-1/Orion-NAS only) |
| 24 | * f1000000 on-chip peripheral registers |
| 25 | * f2000000 PCIe I/O space |
| 26 | * f2100000 PCI I/O space |
| 27 | * f4000000 device bus mappings (boot) |
| 28 | * fa000000 device bus mappings (cs0) |
| 29 | * fa800000 device bus mappings (cs2) |
| 30 | * fc000000 device bus mappings (cs0/cs1) |
| 31 | * |
| 32 | * virt phys size |
| 33 | * fdd00000 f1000000 1M on-chip peripheral registers |
| 34 | * fde00000 f2000000 1M PCIe I/O space |
| 35 | * fdf00000 f2100000 1M PCI I/O space |
| 36 | * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) |
| 37 | ****************************************************************************/ |
| 38 | #define ORION5X_REGS_PHYS_BASE 0xf1000000 |
| 39 | #define ORION5X_REGS_VIRT_BASE 0xfdd00000 |
| 40 | #define ORION5X_REGS_SIZE SZ_1M |
| 41 | |
| 42 | #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 |
| 43 | #define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 |
| 44 | #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 |
| 45 | #define ORION5X_PCIE_IO_SIZE SZ_1M |
| 46 | |
| 47 | #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 |
| 48 | #define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 |
| 49 | #define ORION5X_PCI_IO_BUS_BASE 0x00100000 |
| 50 | #define ORION5X_PCI_IO_SIZE SZ_1M |
| 51 | |
| 52 | /* Relevant only for Orion-1/Orion-NAS */ |
| 53 | #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 |
| 54 | #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 |
| 55 | #define ORION5X_PCIE_WA_SIZE SZ_16M |
| 56 | |
| 57 | #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 |
| 58 | #define ORION5X_PCIE_MEM_SIZE SZ_128M |
| 59 | |
| 60 | #define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 |
| 61 | #define ORION5X_PCI_MEM_SIZE SZ_128M |
| 62 | |
| 63 | /******************************************************************************* |
| 64 | * Supported Devices & Revisions |
| 65 | ******************************************************************************/ |
| 66 | /* Orion-1 (88F5181) */ |
| 67 | #define MV88F5181_DEV_ID 0x5181 |
| 68 | #define MV88F5181_REV_B1 3 |
| 69 | /* Orion-NAS (88F5182) */ |
| 70 | #define MV88F5182_DEV_ID 0x5182 |
| 71 | #define MV88F5182_REV_A2 2 |
| 72 | /* Orion-2 (88F5281) */ |
| 73 | #define MV88F5281_DEV_ID 0x5281 |
| 74 | #define MV88F5281_REV_D1 5 |
| 75 | #define MV88F5281_REV_D2 6 |
| 76 | |
| 77 | /******************************************************************************* |
| 78 | * Orion Registers Map |
| 79 | ******************************************************************************/ |
| 80 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) |
| 81 | #define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) |
| 82 | |
| 83 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) |
| 84 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) |
| 85 | #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) |
| 86 | #define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) |
| 87 | #define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) |
| 88 | #define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) |
| 89 | #define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) |
| 90 | #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) |
| 91 | |
| 92 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) |
| 93 | #define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) |
| 94 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) |
| 95 | |
| 96 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) |
| 97 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) |
| 98 | |
| 99 | #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) |
| 100 | #define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) |
| 101 | |
| 102 | #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) |
| 103 | #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) |
| 104 | #define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) |
| 105 | |
| 106 | #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) |
| 107 | #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) |
| 108 | #define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) |
| 109 | |
| 110 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) |
| 111 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) |
| 112 | #define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) |
| 113 | |
| 114 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) |
| 115 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) |
| 116 | #define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) |
| 117 | |
| 118 | /******************************************************************************* |
| 119 | * Device Bus Registers |
| 120 | ******************************************************************************/ |
| 121 | #define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) |
| 122 | #define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) |
| 123 | #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) |
| 124 | #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) |
| 125 | #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) |
| 126 | #define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) |
| 127 | #define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) |
| 128 | #define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) |
| 129 | #define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) |
| 130 | #define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) |
| 131 | #define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) |
| 132 | #define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) |
| 133 | #define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) |
| 134 | #define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) |
| 135 | #define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) |
| 136 | #define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) |
| 137 | #define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) |
| 138 | #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) |
| 139 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) |
| 140 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) |
| 141 | #define GPIO_MAX 32 |
| 142 | |
| 143 | /*************************************************************************** |
| 144 | * Orion CPU Bridge Registers |
| 145 | **************************************************************************/ |
| 146 | #define CPU_CONF ORION5X_BRIDGE_REG(0x100) |
| 147 | #define CPU_CTRL ORION5X_BRIDGE_REG(0x104) |
| 148 | #define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) |
| 149 | #define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) |
| 150 | #define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) |
| 151 | #define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) |
| 152 | #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) |
| 153 | #define BRIDGE_INT_TIMER0 0x0002 |
| 154 | #define BRIDGE_INT_TIMER1 0x0004 |
| 155 | #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) |
| 156 | #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) |
| 157 | |
| 158 | |
| 159 | #endif |