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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 8d8084d85984b3fa4464c72c4db0a785fb10238f / . / arch / arm64 / boot / dts / rockchip / rk3328.dtsi
blob: cae3415544862dfddf06a034ecea62bd50739fd2 [file] [log] [blame]
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]1/*
2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3328-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h>
48#include <dt-bindings/power/rk3328-power.h>
49#include <dt-bindings/soc/rockchip,boot-mode.h>
Rocky Hao87e0d602017-08-04 16:06:15 +0800[diff] [blame]50#include <dt-bindings/thermal/thermal.h>
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]51
52/ {
53 compatible = "rockchip,rk3328";
54
55 interrupt-parent = <&gic>;
56 #address-cells = <2>;
57 #size-cells = <2>;
58
59 aliases {
60 serial0 = &uart0;
61 serial1 = &uart1;
62 serial2 = &uart2;
63 i2c0 = &i2c0;
64 i2c1 = &i2c1;
65 i2c2 = &i2c2;
66 i2c3 = &i2c3;
David Wu9c4cc912017-08-10 22:01:41 +0800[diff] [blame]67 ethernet0 = &gmac2io;
68 ethernet1 = &gmac2phy;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]69 };
70
71 cpus {
72 #address-cells = <2>;
73 #size-cells = <0>;
74
75 cpu0: cpu@0 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a53", "arm,armv8";
78 reg = <0x0 0x0>;
79 clocks = <&cru ARMCLK>;
Rocky Hao87e0d602017-08-04 16:06:15 +0800[diff] [blame]80 #cooling-cells = <2>;
81 dynamic-power-coefficient = <120>;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]82 enable-method = "psci";
83 next-level-cache = <&l2>;
Finley Xiaoe997a6a2017-08-04 11:33:37 +0800[diff] [blame]84 operating-points-v2 = <&cpu0_opp_table>;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]85 };
86
87 cpu1: cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53", "arm,armv8";
90 reg = <0x0 0x1>;
91 clocks = <&cru ARMCLK>;
Rocky Hao87e0d602017-08-04 16:06:15 +0800[diff] [blame]92 dynamic-power-coefficient = <120>;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]93 enable-method = "psci";
94 next-level-cache = <&l2>;
Finley Xiaoe997a6a2017-08-04 11:33:37 +0800[diff] [blame]95 operating-points-v2 = <&cpu0_opp_table>;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]96 };
97
98 cpu2: cpu@2 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53", "arm,armv8";
101 reg = <0x0 0x2>;
102 clocks = <&cru ARMCLK>;
Rocky Hao87e0d602017-08-04 16:06:15 +0800[diff] [blame]103 dynamic-power-coefficient = <120>;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]104 enable-method = "psci";
105 next-level-cache = <&l2>;
Finley Xiaoe997a6a2017-08-04 11:33:37 +0800[diff] [blame]106 operating-points-v2 = <&cpu0_opp_table>;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]107 };
108
109 cpu3: cpu@3 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a53", "arm,armv8";
112 reg = <0x0 0x3>;
113 clocks = <&cru ARMCLK>;
Rocky Hao87e0d602017-08-04 16:06:15 +0800[diff] [blame]114 dynamic-power-coefficient = <120>;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]115 enable-method = "psci";
116 next-level-cache = <&l2>;
Finley Xiaoe997a6a2017-08-04 11:33:37 +0800[diff] [blame]117 operating-points-v2 = <&cpu0_opp_table>;
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]118 };
119
120 l2: l2-cache0 {
121 compatible = "cache";
122 };
123 };
124
Finley Xiaoe997a6a2017-08-04 11:33:37 +0800[diff] [blame]125 cpu0_opp_table: opp_table0 {
126 compatible = "operating-points-v2";
127 opp-shared;
128
129 opp-408000000 {
130 opp-hz = /bits/ 64 <408000000>;
131 opp-microvolt = <950000>;
132 clock-latency-ns = <40000>;
133 opp-suspend;
134 };
135 opp-600000000 {
136 opp-hz = /bits/ 64 <600000000>;
137 opp-microvolt = <950000>;
138 clock-latency-ns = <40000>;
139 };
140 opp-816000000 {
141 opp-hz = /bits/ 64 <816000000>;
142 opp-microvolt = <1000000>;
143 clock-latency-ns = <40000>;
144 };
145 opp-1008000000 {
146 opp-hz = /bits/ 64 <1008000000>;
147 opp-microvolt = <1100000>;
148 clock-latency-ns = <40000>;
149 };
150 opp-1200000000 {
151 opp-hz = /bits/ 64 <1200000000>;
152 opp-microvolt = <1225000>;
153 clock-latency-ns = <40000>;
154 };
155 opp-1296000000 {
156 opp-hz = /bits/ 64 <1296000000>;
157 opp-microvolt = <1300000>;
158 clock-latency-ns = <40000>;
159 };
160 };
161
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]162 amba {
163 compatible = "simple-bus";
164 #address-cells = <2>;
165 #size-cells = <2>;
166 ranges;
167
168 dmac: dmac@ff1f0000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0x0 0xff1f0000 0x0 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cru ACLK_DMAC>;
174 clock-names = "apb_pclk";
175 #dma-cells = <1>;
176 };
177 };
178
179 arm-pmu {
180 compatible = "arm,cortex-a53-pmu";
181 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
186 };
187
188 psci {
189 compatible = "arm,psci-1.0", "arm,psci-0.2";
190 method = "smc";
191 };
192
193 timer {
194 compatible = "arm,armv8-timer";
195 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
196 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
197 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
199 };
200
201 xin24m: xin24m {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <24000000>;
205 clock-output-names = "xin24m";
206 };
207
Sugar Zhangd80ef502017-07-27 16:16:03 +0800[diff] [blame]208 i2s0: i2s@ff000000 {
209 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
210 reg = <0x0 0xff000000 0x0 0x1000>;
211 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
213 clock-names = "i2s_clk", "i2s_hclk";
214 dmas = <&dmac 11>, <&dmac 12>;
215 dma-names = "tx", "rx";
216 status = "disabled";
217 };
218
219 i2s1: i2s@ff010000 {
220 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
221 reg = <0x0 0xff010000 0x0 0x1000>;
222 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
224 clock-names = "i2s_clk", "i2s_hclk";
225 dmas = <&dmac 14>, <&dmac 15>;
226 dma-names = "tx", "rx";
227 status = "disabled";
228 };
229
230 i2s2: i2s@ff020000 {
231 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
232 reg = <0x0 0xff020000 0x0 0x1000>;
233 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
235 clock-names = "i2s_clk", "i2s_hclk";
236 dmas = <&dmac 0>, <&dmac 1>;
237 dma-names = "tx", "rx";
238 status = "disabled";
239 };
240
Sugar Zhangfc982e02017-07-27 16:16:04 +0800[diff] [blame]241 spdif: spdif@ff030000 {
242 compatible = "rockchip,rk3328-spdif";
243 reg = <0x0 0xff030000 0x0 0x1000>;
244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
246 clock-names = "mclk", "hclk";
247 dmas = <&dmac 10>;
248 dma-names = "tx";
249 pinctrl-names = "default";
250 pinctrl-0 = <&spdifm2_tx>;
251 status = "disabled";
252 };
253
Sugar Zhang13ed1502017-08-21 16:25:06 +0800[diff] [blame]254 pdm: pdm@ff040000 {
255 compatible = "rockchip,pdm";
256 reg = <0x0 0xff040000 0x0 0x1000>;
257 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
258 clock-names = "pdm_clk", "pdm_hclk";
259 dmas = <&dmac 16>;
260 dma-names = "rx";
261 pinctrl-names = "default", "sleep";
262 pinctrl-0 = <&pdmm0_clk
263 &pdmm0_sdi0
264 &pdmm0_sdi1
265 &pdmm0_sdi2
266 &pdmm0_sdi3>;
267 pinctrl-1 = <&pdmm0_clk_sleep
268 &pdmm0_sdi0_sleep
269 &pdmm0_sdi1_sleep
270 &pdmm0_sdi2_sleep
271 &pdmm0_sdi3_sleep>;
272 status = "disabled";
273 };
274
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]275 grf: syscon@ff100000 {
276 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
277 reg = <0x0 0xff100000 0x0 0x1000>;
278 #address-cells = <1>;
279 #size-cells = <1>;
280
David Wucc51f502017-07-25 18:08:01 +0800[diff] [blame]281 io_domains: io-domains {
282 compatible = "rockchip,rk3328-io-voltage-domain";
283 status = "disabled";
284 };
285
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]286 power: power-controller {
287 compatible = "rockchip,rk3328-power-controller";
288 #power-domain-cells = <1>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 pd_hevc@RK3328_PD_HEVC {
293 reg = <RK3328_PD_HEVC>;
294 };
295 pd_video@RK3328_PD_VIDEO {
296 reg = <RK3328_PD_VIDEO>;
297 };
298 pd_vpu@RK3328_PD_VPU {
299 reg = <RK3328_PD_VPU>;
300 };
301 };
302
303 reboot-mode {
304 compatible = "syscon-reboot-mode";
305 offset = <0x5c8>;
306 mode-normal = <BOOT_NORMAL>;
307 mode-recovery = <BOOT_RECOVERY>;
308 mode-bootloader = <BOOT_FASTBOOT>;
309 mode-loader = <BOOT_BL_DOWNLOAD>;
310 };
311
312 };
313
314 uart0: serial@ff110000 {
315 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff110000 0x0 0x100>;
317 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
319 clock-names = "baudclk", "apb_pclk";
320 dmas = <&dmac 2>, <&dmac 3>;
321 #dma-cells = <2>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
324 reg-io-width = <4>;
325 reg-shift = <2>;
326 status = "disabled";
327 };
328
329 uart1: serial@ff120000 {
330 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
331 reg = <0x0 0xff120000 0x0 0x100>;
332 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
334 clock-names = "sclk_uart", "pclk_uart";
335 dmas = <&dmac 4>, <&dmac 5>;
336 #dma-cells = <2>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
339 reg-io-width = <4>;
340 reg-shift = <2>;
341 status = "disabled";
342 };
343
344 uart2: serial@ff130000 {
345 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
346 reg = <0x0 0xff130000 0x0 0x100>;
347 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
349 clock-names = "baudclk", "apb_pclk";
350 dmas = <&dmac 6>, <&dmac 7>;
351 #dma-cells = <2>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&uart2m1_xfer>;
354 reg-io-width = <4>;
355 reg-shift = <2>;
356 status = "disabled";
357 };
358
359 i2c0: i2c@ff150000 {
360 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
361 reg = <0x0 0xff150000 0x0 0x1000>;
362 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
366 clock-names = "i2c", "pclk";
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c0_xfer>;
369 status = "disabled";
370 };
371
372 i2c1: i2c@ff160000 {
373 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
374 reg = <0x0 0xff160000 0x0 0x1000>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
379 clock-names = "i2c", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c1_xfer>;
382 status = "disabled";
383 };
384
385 i2c2: i2c@ff170000 {
386 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
387 reg = <0x0 0xff170000 0x0 0x1000>;
388 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
390 #size-cells = <0>;
391 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
392 clock-names = "i2c", "pclk";
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c2_xfer>;
395 status = "disabled";
396 };
397
398 i2c3: i2c@ff180000 {
399 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
400 reg = <0x0 0xff180000 0x0 0x1000>;
401 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
405 clock-names = "i2c", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c3_xfer>;
408 status = "disabled";
409 };
410
411 spi0: spi@ff190000 {
412 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
413 reg = <0x0 0xff190000 0x0 0x1000>;
414 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
416 #size-cells = <0>;
417 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
418 clock-names = "spiclk", "apb_pclk";
419 dmas = <&dmac 8>, <&dmac 9>;
420 dma-names = "tx", "rx";
421 pinctrl-names = "default";
422 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
423 status = "disabled";
424 };
425
426 wdt: watchdog@ff1a0000 {
427 compatible = "snps,dw-wdt";
428 reg = <0x0 0xff1a0000 0x0 0x100>;
429 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
430 };
431
David Wu0bb2ef62017-08-08 23:43:15 +0800[diff] [blame]432 pwm0: pwm@ff1b0000 {
433 compatible = "rockchip,rk3328-pwm";
434 reg = <0x0 0xff1b0000 0x0 0x10>;
435 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
436 clock-names = "pwm", "pclk";
437 pinctrl-names = "default";
438 pinctrl-0 = <&pwm0_pin>;
439 #pwm-cells = <3>;
440 status = "disabled";
441 };
442
443 pwm1: pwm@ff1b0010 {
444 compatible = "rockchip,rk3328-pwm";
445 reg = <0x0 0xff1b0010 0x0 0x10>;
446 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
447 clock-names = "pwm", "pclk";
448 pinctrl-names = "default";
449 pinctrl-0 = <&pwm1_pin>;
450 #pwm-cells = <3>;
451 status = "disabled";
452 };
453
454 pwm2: pwm@ff1b0020 {
455 compatible = "rockchip,rk3328-pwm";
456 reg = <0x0 0xff1b0020 0x0 0x10>;
457 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
458 clock-names = "pwm", "pclk";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pwm2_pin>;
461 #pwm-cells = <3>;
462 status = "disabled";
463 };
464
465 pwm3: pwm@ff1b0030 {
466 compatible = "rockchip,rk3328-pwm";
467 reg = <0x0 0xff1b0030 0x0 0x10>;
468 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
470 clock-names = "pwm", "pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwmir_pin>;
473 #pwm-cells = <3>;
474 status = "disabled";
475 };
476
Rocky Hao87e0d602017-08-04 16:06:15 +0800[diff] [blame]477 thermal-zones {
478 soc_thermal: soc-thermal {
479 polling-delay-passive = <20>;
480 polling-delay = <1000>;
481 sustainable-power = <1000>;
482
483 thermal-sensors = <&tsadc 0>;
484
485 trips {
486 threshold: trip-point0 {
487 temperature = <70000>;
488 hysteresis = <2000>;
489 type = "passive";
490 };
491 target: trip-point1 {
492 temperature = <85000>;
493 hysteresis = <2000>;
494 type = "passive";
495 };
496 soc_crit: soc-crit {
497 temperature = <95000>;
498 hysteresis = <2000>;
499 type = "critical";
500 };
501 };
502
503 cooling-maps {
504 map0 {
505 trip = <&target>;
506 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
507 contribution = <4096>;
508 };
509 };
510 };
511
512 };
513
Rocky Hao20590de2017-08-04 16:06:14 +0800[diff] [blame]514 tsadc: tsadc@ff250000 {
515 compatible = "rockchip,rk3328-tsadc";
516 reg = <0x0 0xff250000 0x0 0x100>;
Heiko Stuebner3fa8c492017-12-04 18:36:10 +0100[diff] [blame]517 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
Rocky Hao20590de2017-08-04 16:06:14 +0800[diff] [blame]518 assigned-clocks = <&cru SCLK_TSADC>;
519 assigned-clock-rates = <50000>;
520 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
521 clock-names = "tsadc", "apb_pclk";
522 pinctrl-names = "init", "default", "sleep";
523 pinctrl-0 = <&otp_gpio>;
524 pinctrl-1 = <&otp_out>;
525 pinctrl-2 = <&otp_gpio>;
526 resets = <&cru SRST_TSADC>;
527 reset-names = "tsadc-apb";
528 rockchip,grf = <&grf>;
529 rockchip,hw-tshut-temp = <100000>;
530 #thermal-sensor-cells = <1>;
531 status = "disabled";
532 };
533
Finley Xiao13bc2c02017-08-04 11:33:38 +0800[diff] [blame]534 efuse: efuse@ff260000 {
535 compatible = "rockchip,rk3328-efuse";
536 reg = <0x0 0xff260000 0x0 0x50>;
537 #address-cells = <1>;
538 #size-cells = <1>;
539 clocks = <&cru SCLK_EFUSE>;
540 clock-names = "pclk_efuse";
541 rockchip,efuse-size = <0x20>;
542
543 /* Data cells */
544 efuse_id: id@7 {
545 reg = <0x07 0x10>;
546 };
547 cpu_leakage: cpu-leakage@17 {
548 reg = <0x17 0x1>;
549 };
550 logic_leakage: logic-leakage@19 {
551 reg = <0x19 0x1>;
552 };
553 efuse_cpu_version: cpu-version@1a {
554 reg = <0x1a 0x1>;
555 bits = <3 3>;
556 };
557 };
558
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]559 saradc: adc@ff280000 {
560 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
561 reg = <0x0 0xff280000 0x0 0x100>;
562 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
563 #io-channel-cells = <1>;
564 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
565 clock-names = "saradc", "apb_pclk";
566 resets = <&cru SRST_SARADC_P>;
567 reset-names = "saradc-apb";
568 status = "disabled";
569 };
570
Heiko Stuebner752fbc02017-12-08 22:46:45 +0100[diff] [blame]571 gpu: gpu@ff300000 {
572 compatible = "rockchip,rk3328-mali", "arm,mali-450";
573 reg = <0x0 0xff300000 0x0 0x40000>;
574 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "gp",
582 "gpmmu",
583 "pp",
584 "pp0",
585 "ppmmu0",
586 "pp1",
587 "ppmmu1";
588 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
589 clock-names = "bus", "core";
590 resets = <&cru SRST_GPU_A>;
591 };
592
Simon Xue49c82f22017-07-24 10:32:07 +0800[diff] [blame]593 h265e_mmu: iommu@ff330200 {
594 compatible = "rockchip,iommu";
595 reg = <0x0 0xff330200 0 0x100>;
596 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
597 interrupt-names = "h265e_mmu";
598 #iommu-cells = <0>;
599 status = "disabled";
600 };
601
602 vepu_mmu: iommu@ff340800 {
603 compatible = "rockchip,iommu";
604 reg = <0x0 0xff340800 0x0 0x40>;
605 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-names = "vepu_mmu";
607 #iommu-cells = <0>;
608 status = "disabled";
609 };
610
611 vpu_mmu: iommu@ff350800 {
612 compatible = "rockchip,iommu";
613 reg = <0x0 0xff350800 0x0 0x40>;
614 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "vpu_mmu";
616 #iommu-cells = <0>;
617 status = "disabled";
618 };
619
620 rkvdec_mmu: iommu@ff360480 {
621 compatible = "rockchip,iommu";
622 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
623 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
624 interrupt-names = "rkvdec_mmu";
625 #iommu-cells = <0>;
626 status = "disabled";
627 };
628
629 vop_mmu: iommu@ff373f00 {
630 compatible = "rockchip,iommu";
631 reg = <0x0 0xff373f00 0x0 0x100>;
Arnd Bergmannb5211022017-10-10 10:56:01 +0200[diff] [blame]632 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
Simon Xue49c82f22017-07-24 10:32:07 +0800[diff] [blame]633 interrupt-names = "vop_mmu";
634 #iommu-cells = <0>;
635 status = "disabled";
636 };
637
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]638 cru: clock-controller@ff440000 {
639 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
640 reg = <0x0 0xff440000 0x0 0x1000>;
641 rockchip,grf = <&grf>;
642 #clock-cells = <1>;
643 #reset-cells = <1>;
644 assigned-clocks =
645 /*
646 * CPLL should run at 1200, but that is to high for
647 * the initial dividers of most of its children.
648 * We need set cpll child clk div first,
649 * and then set the cpll frequency.
650 */
651 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
652 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
653 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
654 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
655 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
656 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
657 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
658 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
659 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
660 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
661 <&cru SCLK_WIFI>, <&cru ARMCLK>,
662 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
663 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
664 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
665 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
666 <&cru SCLK_RTC32K>;
667 assigned-clock-parents =
668 <&cru HDMIPHY>, <&cru PLL_APLL>,
669 <&cru PLL_GPLL>, <&xin24m>,
670 <&xin24m>, <&xin24m>;
671 assigned-clock-rates =
672 <0>, <61440000>,
673 <0>, <24000000>,
674 <24000000>, <24000000>,
675 <15000000>, <15000000>,
676 <100000000>, <100000000>,
677 <100000000>, <100000000>,
678 <50000000>, <100000000>,
679 <100000000>, <100000000>,
680 <50000000>, <50000000>,
681 <50000000>, <50000000>,
682 <24000000>, <600000000>,
683 <491520000>, <1200000000>,
684 <150000000>, <75000000>,
685 <75000000>, <150000000>,
686 <75000000>, <75000000>,
687 <32768>;
688 };
689
William Wuc60c0372017-06-16 18:34:14 +0800[diff] [blame]690 usb2phy_grf: syscon@ff450000 {
691 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
692 "simple-mfd";
693 reg = <0x0 0xff450000 0x0 0x10000>;
694 #address-cells = <1>;
695 #size-cells = <1>;
696
697 u2phy: usb2-phy@100 {
698 compatible = "rockchip,rk3328-usb2phy";
699 reg = <0x100 0x10>;
700 clocks = <&xin24m>;
701 clock-names = "phyclk";
702 clock-output-names = "usb480m_phy";
703 #clock-cells = <0>;
704 assigned-clocks = <&cru USB480M>;
705 assigned-clock-parents = <&u2phy>;
706 status = "disabled";
707
708 u2phy_otg: otg-port {
709 #phy-cells = <0>;
710 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
713 interrupt-names = "otg-bvalid", "otg-id",
714 "linestate";
715 status = "disabled";
716 };
717
718 u2phy_host: host-port {
719 #phy-cells = <0>;
720 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
721 interrupt-names = "linestate";
722 status = "disabled";
723 };
724 };
725 };
726
Shawn Lind717f732017-05-24 08:34:49 +0800[diff] [blame]727 sdmmc: dwmmc@ff500000 {
728 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
729 reg = <0x0 0xff500000 0x0 0x4000>;
730 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
732 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
Robin Murphyca9eee92018-02-15 14:05:53 +0000[diff] [blame]733 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Shawn Lind717f732017-05-24 08:34:49 +0800[diff] [blame]734 fifo-depth = <0x100>;
735 status = "disabled";
736 };
737
738 sdio: dwmmc@ff510000 {
739 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
740 reg = <0x0 0xff510000 0x0 0x4000>;
741 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
743 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
Robin Murphyca9eee92018-02-15 14:05:53 +0000[diff] [blame]744 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Shawn Lind717f732017-05-24 08:34:49 +0800[diff] [blame]745 fifo-depth = <0x100>;
746 status = "disabled";
747 };
748
749 emmc: dwmmc@ff520000 {
750 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
751 reg = <0x0 0xff520000 0x0 0x4000>;
752 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
754 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
Robin Murphyca9eee92018-02-15 14:05:53 +0000[diff] [blame]755 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Shawn Lind717f732017-05-24 08:34:49 +0800[diff] [blame]756 fifo-depth = <0x100>;
757 status = "disabled";
758 };
759
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]760 gmac2io: ethernet@ff540000 {
761 compatible = "rockchip,rk3328-gmac";
762 reg = <0x0 0xff540000 0x0 0x10000>;
763 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
764 interrupt-names = "macirq";
765 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
766 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
767 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
768 <&cru PCLK_MAC2IO>;
769 clock-names = "stmmaceth", "mac_clk_rx",
770 "mac_clk_tx", "clk_mac_ref",
771 "clk_mac_refout", "aclk_mac",
772 "pclk_mac";
773 resets = <&cru SRST_GMAC2IO_A>;
774 reset-names = "stmmaceth";
775 rockchip,grf = <&grf>;
776 status = "disabled";
777 };
778
David Wu9c4cc912017-08-10 22:01:41 +0800[diff] [blame]779 gmac2phy: ethernet@ff550000 {
780 compatible = "rockchip,rk3328-gmac";
781 reg = <0x0 0xff550000 0x0 0x10000>;
782 rockchip,grf = <&grf>;
783 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
784 interrupt-names = "macirq";
785 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
786 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
787 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
788 <&cru SCLK_MAC2PHY_OUT>;
789 clock-names = "stmmaceth", "mac_clk_rx",
790 "mac_clk_tx", "clk_mac_ref",
791 "aclk_mac", "pclk_mac",
792 "clk_macphy";
793 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
794 reset-names = "stmmaceth", "mac-phy";
795 phy-mode = "rmii";
796 phy-handle = <&phy>;
797 status = "disabled";
798
799 mdio {
800 compatible = "snps,dwmac-mdio";
801 #address-cells = <1>;
802 #size-cells = <0>;
803
804 phy: phy@0 {
805 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
806 reg = <0>;
807 clocks = <&cru SCLK_MAC2PHY_OUT>;
808 resets = <&cru SRST_MACPHY>;
809 pinctrl-names = "default";
810 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
811 phy-is-integrated;
812 };
813 };
814 };
815
William Wuc60c0372017-06-16 18:34:14 +0800[diff] [blame]816 usb20_otg: usb@ff580000 {
817 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
818 "snps,dwc2";
819 reg = <0x0 0xff580000 0x0 0x40000>;
820 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cru HCLK_OTG>;
822 clock-names = "otg";
823 dr_mode = "otg";
824 g-np-tx-fifo-size = <16>;
825 g-rx-fifo-size = <280>;
826 g-tx-fifo-size = <256 128 128 64 32 16>;
827 g-use-dma;
828 phys = <&u2phy_otg>;
829 phy-names = "usb2-phy";
830 status = "disabled";
831 };
832
833 usb_host0_ehci: usb@ff5c0000 {
834 compatible = "generic-ehci";
835 reg = <0x0 0xff5c0000 0x0 0x10000>;
836 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&cru HCLK_HOST0>, <&u2phy>;
838 clock-names = "usbhost", "utmi";
839 phys = <&u2phy_host>;
840 phy-names = "usb";
841 status = "disabled";
842 };
843
844 usb_host0_ohci: usb@ff5d0000 {
845 compatible = "generic-ohci";
846 reg = <0x0 0xff5d0000 0x0 0x10000>;
847 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&cru HCLK_HOST0>, <&u2phy>;
849 clock-names = "usbhost", "utmi";
850 phys = <&u2phy_host>;
851 phy-names = "usb";
852 status = "disabled";
853 };
854
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]855 gic: interrupt-controller@ff811000 {
856 compatible = "arm,gic-400";
857 #interrupt-cells = <3>;
858 #address-cells = <0>;
859 interrupt-controller;
860 reg = <0x0 0xff811000 0 0x1000>,
861 <0x0 0xff812000 0 0x2000>,
862 <0x0 0xff814000 0 0x2000>,
863 <0x0 0xff816000 0 0x2000>;
864 interrupts = <GIC_PPI 9
865 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
866 };
867
868 pinctrl: pinctrl {
869 compatible = "rockchip,rk3328-pinctrl";
870 rockchip,grf = <&grf>;
871 #address-cells = <2>;
872 #size-cells = <2>;
873 ranges;
874
875 gpio0: gpio0@ff210000 {
876 compatible = "rockchip,gpio-bank";
877 reg = <0x0 0xff210000 0x0 0x100>;
878 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&cru PCLK_GPIO0>;
880
881 gpio-controller;
882 #gpio-cells = <2>;
883
884 interrupt-controller;
885 #interrupt-cells = <2>;
886 };
887
888 gpio1: gpio1@ff220000 {
889 compatible = "rockchip,gpio-bank";
890 reg = <0x0 0xff220000 0x0 0x100>;
891 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&cru PCLK_GPIO1>;
893
894 gpio-controller;
895 #gpio-cells = <2>;
896
897 interrupt-controller;
898 #interrupt-cells = <2>;
899 };
900
901 gpio2: gpio2@ff230000 {
902 compatible = "rockchip,gpio-bank";
903 reg = <0x0 0xff230000 0x0 0x100>;
904 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&cru PCLK_GPIO2>;
906
907 gpio-controller;
908 #gpio-cells = <2>;
909
910 interrupt-controller;
911 #interrupt-cells = <2>;
912 };
913
914 gpio3: gpio3@ff240000 {
915 compatible = "rockchip,gpio-bank";
916 reg = <0x0 0xff240000 0x0 0x100>;
917 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&cru PCLK_GPIO3>;
919
920 gpio-controller;
921 #gpio-cells = <2>;
922
923 interrupt-controller;
924 #interrupt-cells = <2>;
925 };
926
927 pcfg_pull_up: pcfg-pull-up {
928 bias-pull-up;
929 };
930
931 pcfg_pull_down: pcfg-pull-down {
932 bias-pull-down;
933 };
934
935 pcfg_pull_none: pcfg-pull-none {
936 bias-disable;
937 };
938
939 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
940 bias-disable;
941 drive-strength = <2>;
942 };
943
944 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
945 bias-pull-up;
946 drive-strength = <2>;
947 };
948
949 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
950 bias-pull-up;
951 drive-strength = <4>;
952 };
953
954 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
955 bias-disable;
956 drive-strength = <4>;
957 };
958
959 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
960 bias-pull-down;
961 drive-strength = <4>;
962 };
963
964 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
965 bias-disable;
966 drive-strength = <8>;
967 };
968
969 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
970 bias-pull-up;
971 drive-strength = <8>;
972 };
973
974 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
975 bias-disable;
976 drive-strength = <12>;
977 };
978
979 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
980 bias-pull-up;
981 drive-strength = <12>;
982 };
983
984 pcfg_output_high: pcfg-output-high {
985 output-high;
986 };
987
988 pcfg_output_low: pcfg-output-low {
989 output-low;
990 };
991
992 pcfg_input_high: pcfg-input-high {
993 bias-pull-up;
994 input-enable;
995 };
996
997 pcfg_input: pcfg-input {
998 input-enable;
999 };
1000
1001 i2c0 {
1002 i2c0_xfer: i2c0-xfer {
1003 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1004 <2 RK_PD1 1 &pcfg_pull_none>;
1005 };
1006 };
1007
1008 i2c1 {
1009 i2c1_xfer: i2c1-xfer {
1010 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1011 <2 RK_PA5 2 &pcfg_pull_none>;
1012 };
1013 };
1014
1015 i2c2 {
1016 i2c2_xfer: i2c2-xfer {
1017 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1018 <2 RK_PB6 1 &pcfg_pull_none>;
1019 };
1020 };
1021
1022 i2c3 {
1023 i2c3_xfer: i2c3-xfer {
1024 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1025 <0 RK_PA6 2 &pcfg_pull_none>;
1026 };
1027 i2c3_gpio: i2c3-gpio {
1028 rockchip,pins =
1029 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1030 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1031 };
1032 };
1033
1034 hdmi_i2c {
1035 hdmii2c_xfer: hdmii2c-xfer {
1036 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1037 <0 RK_PA6 1 &pcfg_pull_none>;
1038 };
1039 };
1040
Sugar Zhang13ed1502017-08-21 16:25:06 +0800[diff] [blame]1041 pdm-0 {
1042 pdmm0_clk: pdmm0-clk {
1043 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1044 };
1045
1046 pdmm0_fsync: pdmm0-fsync {
1047 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1048 };
1049
1050 pdmm0_sdi0: pdmm0-sdi0 {
1051 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1052 };
1053
1054 pdmm0_sdi1: pdmm0-sdi1 {
1055 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1056 };
1057
1058 pdmm0_sdi2: pdmm0-sdi2 {
1059 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1060 };
1061
1062 pdmm0_sdi3: pdmm0-sdi3 {
1063 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1064 };
1065
1066 pdmm0_clk_sleep: pdmm0-clk-sleep {
1067 rockchip,pins =
1068 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1069 };
1070
1071 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1072 rockchip,pins =
1073 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1074 };
1075
1076 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1077 rockchip,pins =
1078 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1079 };
1080
1081 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1082 rockchip,pins =
1083 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1084 };
1085
1086 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1087 rockchip,pins =
1088 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1089 };
1090
1091 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1092 rockchip,pins =
1093 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1094 };
1095 };
1096
Liang Chen52e02d32017-03-27 17:40:48 +0800[diff] [blame]1097 tsadc {
1098 otp_gpio: otp-gpio {
1099 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1100 };
1101
1102 otp_out: otp-out {
1103 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1104 };
1105 };
1106
1107 uart0 {
1108 uart0_xfer: uart0-xfer {
1109 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1110 <1 RK_PB0 1 &pcfg_pull_none>;
1111 };
1112
1113 uart0_cts: uart0-cts {
1114 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1115 };
1116
1117 uart0_rts: uart0-rts {
1118 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1119 };
1120
1121 uart0_rts_gpio: uart0-rts-gpio {
1122 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1123 };
1124 };
1125
1126 uart1 {
1127 uart1_xfer: uart1-xfer {
1128 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1129 <3 RK_PA6 4 &pcfg_pull_none>;
1130 };
1131
1132 uart1_cts: uart1-cts {
1133 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1134 };
1135
1136 uart1_rts: uart1-rts {
1137 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1138 };
1139
1140 uart1_rts_gpio: uart1-rts-gpio {
1141 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1142 };
1143 };
1144
1145 uart2-0 {
1146 uart2m0_xfer: uart2m0-xfer {
1147 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1148 <1 RK_PA1 2 &pcfg_pull_none>;
1149 };
1150 };
1151
1152 uart2-1 {
1153 uart2m1_xfer: uart2m1-xfer {
1154 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1155 <2 RK_PA1 1 &pcfg_pull_none>;
1156 };
1157 };
1158
1159 spi0-0 {
1160 spi0m0_clk: spi0m0-clk {
1161 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1162 };
1163
1164 spi0m0_cs0: spi0m0-cs0 {
1165 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1166 };
1167
1168 spi0m0_tx: spi0m0-tx {
1169 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1170 };
1171
1172 spi0m0_rx: spi0m0-rx {
1173 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1174 };
1175
1176 spi0m0_cs1: spi0m0-cs1 {
1177 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1178 };
1179 };
1180
1181 spi0-1 {
1182 spi0m1_clk: spi0m1-clk {
1183 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1184 };
1185
1186 spi0m1_cs0: spi0m1-cs0 {
1187 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1188 };
1189
1190 spi0m1_tx: spi0m1-tx {
1191 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1192 };
1193
1194 spi0m1_rx: spi0m1-rx {
1195 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1196 };
1197
1198 spi0m1_cs1: spi0m1-cs1 {
1199 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1200 };
1201 };
1202
1203 spi0-2 {
1204 spi0m2_clk: spi0m2-clk {
1205 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1206 };
1207
1208 spi0m2_cs0: spi0m2-cs0 {
1209 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1210 };
1211
1212 spi0m2_tx: spi0m2-tx {
1213 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1214 };
1215
1216 spi0m2_rx: spi0m2-rx {
1217 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1218 };
1219 };
1220
1221 i2s1 {
1222 i2s1_mclk: i2s1-mclk {
1223 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1224 };
1225
1226 i2s1_sclk: i2s1-sclk {
1227 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1228 };
1229
1230 i2s1_lrckrx: i2s1-lrckrx {
1231 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1232 };
1233
1234 i2s1_lrcktx: i2s1-lrcktx {
1235 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1236 };
1237
1238 i2s1_sdi: i2s1-sdi {
1239 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1240 };
1241
1242 i2s1_sdo: i2s1-sdo {
1243 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1244 };
1245
1246 i2s1_sdio1: i2s1-sdio1 {
1247 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1248 };
1249
1250 i2s1_sdio2: i2s1-sdio2 {
1251 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1252 };
1253
1254 i2s1_sdio3: i2s1-sdio3 {
1255 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1256 };
1257
1258 i2s1_sleep: i2s1-sleep {
1259 rockchip,pins =
1260 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1261 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1262 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1263 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1264 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1265 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1266 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1267 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1268 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1269 };
1270 };
1271
1272 i2s2-0 {
1273 i2s2m0_mclk: i2s2m0-mclk {
1274 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1275 };
1276
1277 i2s2m0_sclk: i2s2m0-sclk {
1278 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1279 };
1280
1281 i2s2m0_lrckrx: i2s2m0-lrckrx {
1282 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1283 };
1284
1285 i2s2m0_lrcktx: i2s2m0-lrcktx {
1286 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1287 };
1288
1289 i2s2m0_sdi: i2s2m0-sdi {
1290 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1291 };
1292
1293 i2s2m0_sdo: i2s2m0-sdo {
1294 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1295 };
1296
1297 i2s2m0_sleep: i2s2m0-sleep {
1298 rockchip,pins =
1299 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1300 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1301 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1302 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1303 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1304 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1305 };
1306 };
1307
1308 i2s2-1 {
1309 i2s2m1_mclk: i2s2m1-mclk {
1310 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1311 };
1312
1313 i2s2m1_sclk: i2s2m1-sclk {
1314 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1315 };
1316
1317 i2s2m1_lrckrx: i2sm1-lrckrx {
1318 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1319 };
1320
1321 i2s2m1_lrcktx: i2s2m1-lrcktx {
1322 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1323 };
1324
1325 i2s2m1_sdi: i2s2m1-sdi {
1326 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1327 };
1328
1329 i2s2m1_sdo: i2s2m1-sdo {
1330 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1331 };
1332
1333 i2s2m1_sleep: i2s2m1-sleep {
1334 rockchip,pins =
1335 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1336 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1337 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1338 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1339 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1340 };
1341 };
1342
1343 spdif-0 {
1344 spdifm0_tx: spdifm0-tx {
1345 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1346 };
1347 };
1348
1349 spdif-1 {
1350 spdifm1_tx: spdifm1-tx {
1351 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1352 };
1353 };
1354
1355 spdif-2 {
1356 spdifm2_tx: spdifm2-tx {
1357 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1358 };
1359 };
1360
1361 sdmmc0-0 {
1362 sdmmc0m0_pwren: sdmmc0m0-pwren {
1363 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1364 };
1365
1366 sdmmc0m0_gpio: sdmmc0m0-gpio {
1367 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1368 };
1369 };
1370
1371 sdmmc0-1 {
1372 sdmmc0m1_pwren: sdmmc0m1-pwren {
1373 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1374 };
1375
1376 sdmmc0m1_gpio: sdmmc0m1-gpio {
1377 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1378 };
1379 };
1380
1381 sdmmc0 {
1382 sdmmc0_clk: sdmmc0-clk {
1383 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
1384 };
1385
1386 sdmmc0_cmd: sdmmc0-cmd {
1387 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
1388 };
1389
1390 sdmmc0_dectn: sdmmc0-dectn {
1391 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1392 };
1393
1394 sdmmc0_wrprt: sdmmc0-wrprt {
1395 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1396 };
1397
1398 sdmmc0_bus1: sdmmc0-bus1 {
1399 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
1400 };
1401
1402 sdmmc0_bus4: sdmmc0-bus4 {
1403 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
1404 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
1405 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
1406 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
1407 };
1408
1409 sdmmc0_gpio: sdmmc0-gpio {
1410 rockchip,pins =
1411 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1412 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1413 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1414 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1415 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1416 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1417 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1418 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1419 };
1420 };
1421
1422 sdmmc0ext {
1423 sdmmc0ext_clk: sdmmc0ext-clk {
1424 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1425 };
1426
1427 sdmmc0ext_cmd: sdmmc0ext-cmd {
1428 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1429 };
1430
1431 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1432 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1433 };
1434
1435 sdmmc0ext_dectn: sdmmc0ext-dectn {
1436 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1437 };
1438
1439 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1440 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1441 };
1442
1443 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1444 rockchip,pins =
1445 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1446 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1447 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1448 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1449 };
1450
1451 sdmmc0ext_gpio: sdmmc0ext-gpio {
1452 rockchip,pins =
1453 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1454 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1455 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1456 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1457 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1458 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1459 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1460 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1461 };
1462 };
1463
1464 sdmmc1 {
1465 sdmmc1_clk: sdmmc1-clk {
1466 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1467 };
1468
1469 sdmmc1_cmd: sdmmc1-cmd {
1470 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1471 };
1472
1473 sdmmc1_pwren: sdmmc1-pwren {
1474 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1475 };
1476
1477 sdmmc1_wrprt: sdmmc1-wrprt {
1478 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1479 };
1480
1481 sdmmc1_dectn: sdmmc1-dectn {
1482 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1483 };
1484
1485 sdmmc1_bus1: sdmmc1-bus1 {
1486 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1487 };
1488
1489 sdmmc1_bus4: sdmmc1-bus4 {
1490 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1491 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1492 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1493 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1494 };
1495
1496 sdmmc1_gpio: sdmmc1-gpio {
1497 rockchip,pins =
1498 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1499 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1500 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1501 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1502 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1503 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1504 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1505 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1506 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1507 };
1508 };
1509
1510 emmc {
1511 emmc_clk: emmc-clk {
1512 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1513 };
1514
1515 emmc_cmd: emmc-cmd {
1516 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1517 };
1518
1519 emmc_pwren: emmc-pwren {
1520 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1521 };
1522
1523 emmc_rstnout: emmc-rstnout {
1524 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1525 };
1526
1527 emmc_bus1: emmc-bus1 {
1528 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1529 };
1530
1531 emmc_bus4: emmc-bus4 {
1532 rockchip,pins =
1533 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1534 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1535 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1536 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1537 };
1538
1539 emmc_bus8: emmc-bus8 {
1540 rockchip,pins =
1541 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1542 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1543 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1544 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1545 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1546 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1547 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1548 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1549 };
1550 };
1551
1552 pwm0 {
1553 pwm0_pin: pwm0-pin {
1554 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1555 };
1556 };
1557
1558 pwm1 {
1559 pwm1_pin: pwm1-pin {
1560 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1561 };
1562 };
1563
1564 pwm2 {
1565 pwm2_pin: pwm2-pin {
1566 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1567 };
1568 };
1569
1570 pwmir {
1571 pwmir_pin: pwmir-pin {
1572 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1573 };
1574 };
1575
1576 gmac-1 {
1577 rgmiim1_pins: rgmiim1-pins {
1578 rockchip,pins =
1579 /* mac_txclk */
1580 <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1581 /* mac_rxclk */
1582 <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1583 /* mac_mdio */
1584 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1585 /* mac_txen */
1586 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1587 /* mac_clk */
1588 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1589 /* mac_rxdv */
1590 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1591 /* mac_mdc */
1592 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1593 /* mac_rxd1 */
1594 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1595 /* mac_rxd0 */
1596 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1597 /* mac_txd1 */
1598 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1599 /* mac_txd0 */
1600 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1601 /* mac_rxd3 */
1602 <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1603 /* mac_rxd2 */
1604 <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1605 /* mac_txd3 */
1606 <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1607 /* mac_txd2 */
1608 <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1609
1610 /* mac_txclk */
1611 <0 RK_PB0 1 &pcfg_pull_none>,
1612 /* mac_txen */
1613 <0 RK_PB4 1 &pcfg_pull_none>,
1614 /* mac_clk */
1615 <0 RK_PD0 1 &pcfg_pull_none>,
1616 /* mac_txd1 */
1617 <0 RK_PC0 1 &pcfg_pull_none>,
1618 /* mac_txd0 */
1619 <0 RK_PC1 1 &pcfg_pull_none>,
1620 /* mac_txd3 */
1621 <0 RK_PC7 1 &pcfg_pull_none>,
1622 /* mac_txd2 */
1623 <0 RK_PC6 1 &pcfg_pull_none>;
1624 };
1625
1626 rmiim1_pins: rmiim1-pins {
1627 rockchip,pins =
1628 /* mac_mdio */
1629 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1630 /* mac_txen */
1631 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1632 /* mac_clk */
1633 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1634 /* mac_rxer */
1635 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1636 /* mac_rxdv */
1637 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1638 /* mac_mdc */
1639 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1640 /* mac_rxd1 */
1641 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1642 /* mac_rxd0 */
1643 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1644 /* mac_txd1 */
1645 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1646 /* mac_txd0 */
1647 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1648
1649 /* mac_mdio */
1650 <0 RK_PB3 1 &pcfg_pull_none>,
1651 /* mac_txen */
1652 <0 RK_PB4 1 &pcfg_pull_none>,
1653 /* mac_clk */
1654 <0 RK_PD0 1 &pcfg_pull_none>,
1655 /* mac_mdc */
1656 <0 RK_PC3 1 &pcfg_pull_none>,
1657 /* mac_txd1 */
1658 <0 RK_PC0 1 &pcfg_pull_none>,
1659 /* mac_txd0 */
1660 <0 RK_PC1 1 &pcfg_pull_none>;
1661 };
1662 };
1663
1664 gmac2phy {
1665 fephyled_speed100: fephyled-speed100 {
1666 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1667 };
1668
1669 fephyled_speed10: fephyled-speed10 {
1670 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1671 };
1672
1673 fephyled_duplex: fephyled-duplex {
1674 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1675 };
1676
1677 fephyled_rxm0: fephyled-rxm0 {
1678 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1679 };
1680
1681 fephyled_txm0: fephyled-txm0 {
1682 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1683 };
1684
1685 fephyled_linkm0: fephyled-linkm0 {
1686 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1687 };
1688
1689 fephyled_rxm1: fephyled-rxm1 {
1690 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1691 };
1692
1693 fephyled_txm1: fephyled-txm1 {
1694 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1695 };
1696
1697 fephyled_linkm1: fephyled-linkm1 {
1698 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1699 };
1700 };
1701
1702 tsadc_pin {
1703 tsadc_int: tsadc-int {
1704 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1705 };
1706 tsadc_gpio: tsadc-gpio {
1707 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1708 };
1709 };
1710
1711 hdmi_pin {
1712 hdmi_cec: hdmi-cec {
1713 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1714 };
1715
1716 hdmi_hpd: hdmi-hpd {
1717 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1718 };
1719 };
1720
1721 cif-0 {
1722 dvp_d2d9_m0:dvp-d2d9-m0 {
1723 rockchip,pins =
1724 /* cif_d0 */
1725 <3 RK_PA4 2 &pcfg_pull_none>,
1726 /* cif_d1 */
1727 <3 RK_PA5 2 &pcfg_pull_none>,
1728 /* cif_d2 */
1729 <3 RK_PA6 2 &pcfg_pull_none>,
1730 /* cif_d3 */
1731 <3 RK_PA7 2 &pcfg_pull_none>,
1732 /* cif_d4 */
1733 <3 RK_PB0 2 &pcfg_pull_none>,
1734 /* cif_d5m0 */
1735 <3 RK_PB1 2 &pcfg_pull_none>,
1736 /* cif_d6m0 */
1737 <3 RK_PB2 2 &pcfg_pull_none>,
1738 /* cif_d7m0 */
1739 <3 RK_PB3 2 &pcfg_pull_none>,
1740 /* cif_href */
1741 <3 RK_PA1 2 &pcfg_pull_none>,
1742 /* cif_vsync */
1743 <3 RK_PA0 2 &pcfg_pull_none>,
1744 /* cif_clkoutm0 */
1745 <3 RK_PA3 2 &pcfg_pull_none>,
1746 /* cif_clkin */
1747 <3 RK_PA2 2 &pcfg_pull_none>;
1748 };
1749 };
1750
1751 cif-1 {
1752 dvp_d2d9_m1:dvp-d2d9-m1 {
1753 rockchip,pins =
1754 /* cif_d0 */
1755 <3 RK_PA4 2 &pcfg_pull_none>,
1756 /* cif_d1 */
1757 <3 RK_PA5 2 &pcfg_pull_none>,
1758 /* cif_d2 */
1759 <3 RK_PA6 2 &pcfg_pull_none>,
1760 /* cif_d3 */
1761 <3 RK_PA7 2 &pcfg_pull_none>,
1762 /* cif_d4 */
1763 <3 RK_PB0 2 &pcfg_pull_none>,
1764 /* cif_d5m1 */
1765 <2 RK_PC0 4 &pcfg_pull_none>,
1766 /* cif_d6m1 */
1767 <2 RK_PC1 4 &pcfg_pull_none>,
1768 /* cif_d7m1 */
1769 <2 RK_PC2 4 &pcfg_pull_none>,
1770 /* cif_href */
1771 <3 RK_PA1 2 &pcfg_pull_none>,
1772 /* cif_vsync */
1773 <3 RK_PA0 2 &pcfg_pull_none>,
1774 /* cif_clkoutm1 */
1775 <2 RK_PB7 4 &pcfg_pull_none>,
1776 /* cif_clkin */
1777 <3 RK_PA2 2 &pcfg_pull_none>;
1778 };
1779 };
1780 };
1781};