blob: 166f56e639a2c9812d9a417a444a25ffe998dc91 [file] [log] [blame]
Klaus Gogerfce152a62017-12-15 12:44:27 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Jeffy Chen9848ebe2015-12-11 09:30:51 +08002
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <dt-bindings/clock/rk3228-cru.h>
Caesar Wang77960312016-02-15 15:33:32 +08008#include <dt-bindings/thermal/thermal.h>
Jeffy Chen9848ebe2015-12-11 09:30:51 +08009
10/ {
Javier Martinez Canillas01932732016-09-09 10:01:03 -040011 #address-cells = <1>;
12 #size-cells = <1>;
13
Jeffy Chen9848ebe2015-12-11 09:30:51 +080014 interrupt-parent = <&gic>;
15
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
Huibin Hongfebdf632017-08-03 10:36:49 +080020 spi0 = &spi0;
Jeffy Chen9848ebe2015-12-11 09:30:51 +080021 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu0: cpu@f00 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0xf00>;
31 resets = <&cru SRST_CORE0>;
Finley Xiao9f12da42017-05-17 18:16:15 +080032 operating-points-v2 = <&cpu0_opp_table>;
Caesar Wang77960312016-02-15 15:33:32 +080033 #cooling-cells = <2>; /* min followed by max */
Jeffy Chen9848ebe2015-12-11 09:30:51 +080034 clock-latency = <40000>;
35 clocks = <&cru ARMCLK>;
Frank Wang0ae92142017-06-22 18:29:56 +080036 enable-method = "psci";
Jeffy Chen9848ebe2015-12-11 09:30:51 +080037 };
38
39 cpu1: cpu@f01 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a7";
42 reg = <0xf01>;
43 resets = <&cru SRST_CORE1>;
Finley Xiao9f12da42017-05-17 18:16:15 +080044 operating-points-v2 = <&cpu0_opp_table>;
Viresh Kumar0bac06d2018-05-25 16:01:50 +053045 #cooling-cells = <2>; /* min followed by max */
Frank Wang0ae92142017-06-22 18:29:56 +080046 enable-method = "psci";
Jeffy Chen9848ebe2015-12-11 09:30:51 +080047 };
48
49 cpu2: cpu@f02 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a7";
52 reg = <0xf02>;
53 resets = <&cru SRST_CORE2>;
Finley Xiao9f12da42017-05-17 18:16:15 +080054 operating-points-v2 = <&cpu0_opp_table>;
Viresh Kumar0bac06d2018-05-25 16:01:50 +053055 #cooling-cells = <2>; /* min followed by max */
Frank Wang0ae92142017-06-22 18:29:56 +080056 enable-method = "psci";
Jeffy Chen9848ebe2015-12-11 09:30:51 +080057 };
58
59 cpu3: cpu@f03 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a7";
62 reg = <0xf03>;
63 resets = <&cru SRST_CORE3>;
Finley Xiao9f12da42017-05-17 18:16:15 +080064 operating-points-v2 = <&cpu0_opp_table>;
Viresh Kumar0bac06d2018-05-25 16:01:50 +053065 #cooling-cells = <2>; /* min followed by max */
Frank Wang0ae92142017-06-22 18:29:56 +080066 enable-method = "psci";
Finley Xiao9f12da42017-05-17 18:16:15 +080067 };
68 };
69
70 cpu0_opp_table: opp_table0 {
71 compatible = "operating-points-v2";
72 opp-shared;
73
74 opp-408000000 {
75 opp-hz = /bits/ 64 <408000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
78 opp-suspend;
79 };
80 opp-600000000 {
81 opp-hz = /bits/ 64 <600000000>;
82 opp-microvolt = <975000>;
83 };
84 opp-816000000 {
85 opp-hz = /bits/ 64 <816000000>;
86 opp-microvolt = <1000000>;
87 };
88 opp-1008000000 {
89 opp-hz = /bits/ 64 <1008000000>;
90 opp-microvolt = <1175000>;
91 };
92 opp-1200000000 {
93 opp-hz = /bits/ 64 <1200000000>;
94 opp-microvolt = <1275000>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +080095 };
96 };
97
98 amba {
Masahiro Yamada2ef7d5f2016-03-09 13:26:45 +090099 compatible = "simple-bus";
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103
104 pdma: pdma@110f0000 {
105 compatible = "arm,pl330", "arm,primecell";
106 reg = <0x110f0000 0x4000>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
109 #dma-cells = <1>;
110 clocks = <&cru ACLK_DMAC>;
111 clock-names = "apb_pclk";
112 };
113 };
114
115 arm-pmu {
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
122 };
123
Frank Wang0ae92142017-06-22 18:29:56 +0800124 psci {
125 compatible = "arm,psci-1.0", "arm,psci-0.2";
126 method = "smc";
127 };
128
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800129 timer {
130 compatible = "arm,armv7-timer";
131 arm,cpu-registers-not-fw-configured;
132 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
136 clock-frequency = <24000000>;
137 };
138
139 xin24m: oscillator {
140 compatible = "fixed-clock";
141 clock-frequency = <24000000>;
142 clock-output-names = "xin24m";
143 #clock-cells = <0>;
144 };
145
Justin Swartz519574e2019-06-13 10:13:04 +0000146 display_subsystem: display-subsystem {
147 compatible = "rockchip,display-subsystem";
148 ports = <&vop_out>;
149 };
150
Xing Zhengccada242016-06-22 11:16:51 +0800151 i2s1: i2s1@100b0000 {
152 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
153 reg = <0x100b0000 0x4000>;
154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 clock-names = "i2s_clk", "i2s_hclk";
158 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
159 dmas = <&pdma 14>, <&pdma 15>;
160 dma-names = "tx", "rx";
161 pinctrl-names = "default";
162 pinctrl-0 = <&i2s1_bus>;
163 status = "disabled";
164 };
165
166 i2s0: i2s0@100c0000 {
167 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
168 reg = <0x100c0000 0x4000>;
169 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 clock-names = "i2s_clk", "i2s_hclk";
173 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
174 dmas = <&pdma 11>, <&pdma 12>;
175 dma-names = "tx", "rx";
176 status = "disabled";
177 };
178
Sugar Zhang4b456d22017-06-09 15:59:33 +0800179 spdif: spdif@100d0000 {
180 compatible = "rockchip,rk3228-spdif";
181 reg = <0x100d0000 0x1000>;
182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
184 clock-names = "mclk", "hclk";
185 dmas = <&pdma 10>;
186 dma-names = "tx";
187 pinctrl-names = "default";
188 pinctrl-0 = <&spdif_tx>;
189 status = "disabled";
190 };
191
Xing Zhengccada242016-06-22 11:16:51 +0800192 i2s2: i2s2@100e0000 {
193 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
194 reg = <0x100e0000 0x4000>;
195 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
196 #address-cells = <1>;
197 #size-cells = <0>;
198 clock-names = "i2s_clk", "i2s_hclk";
199 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
200 dmas = <&pdma 0>, <&pdma 1>;
201 dma-names = "tx", "rx";
202 status = "disabled";
203 };
204
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800205 grf: syscon@11000000 {
Shawn Lin692f4922018-02-07 14:20:02 +0800206 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800207 reg = <0x11000000 0x1000>;
William Wu3880af42017-06-02 15:04:24 +0800208 #address-cells = <1>;
209 #size-cells = <1>;
210
David Wu83086ad2017-06-22 18:32:23 +0800211 io_domains: io-domains {
212 compatible = "rockchip,rk3228-io-voltage-domain";
213 status = "disabled";
214 };
215
William Wu3880af42017-06-02 15:04:24 +0800216 u2phy0: usb2-phy@760 {
217 compatible = "rockchip,rk3228-usb2phy";
218 reg = <0x0760 0x0c>;
219 clocks = <&cru SCLK_OTGPHY0>;
220 clock-names = "phyclk";
221 clock-output-names = "usb480m_phy0";
222 #clock-cells = <0>;
223 status = "disabled";
224
225 u2phy0_otg: otg-port {
226 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-names = "otg-bvalid", "otg-id",
230 "linestate";
231 #phy-cells = <0>;
232 status = "disabled";
233 };
234
235 u2phy0_host: host-port {
236 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-names = "linestate";
238 #phy-cells = <0>;
239 status = "disabled";
240 };
241 };
242
243 u2phy1: usb2-phy@800 {
244 compatible = "rockchip,rk3228-usb2phy";
245 reg = <0x0800 0x0c>;
246 clocks = <&cru SCLK_OTGPHY1>;
247 clock-names = "phyclk";
248 clock-output-names = "usb480m_phy1";
249 #clock-cells = <0>;
250 status = "disabled";
251
252 u2phy1_otg: otg-port {
253 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-names = "linestate";
255 #phy-cells = <0>;
256 status = "disabled";
257 };
258
259 u2phy1_host: host-port {
260 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-names = "linestate";
262 #phy-cells = <0>;
263 status = "disabled";
264 };
265 };
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800266 };
267
268 uart0: serial@11010000 {
269 compatible = "snps,dw-apb-uart";
270 reg = <0x11010000 0x100>;
271 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
272 clock-frequency = <24000000>;
273 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
274 clock-names = "baudclk", "apb_pclk";
275 pinctrl-names = "default";
276 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
277 reg-shift = <2>;
278 reg-io-width = <4>;
279 status = "disabled";
280 };
281
282 uart1: serial@11020000 {
283 compatible = "snps,dw-apb-uart";
284 reg = <0x11020000 0x100>;
285 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
286 clock-frequency = <24000000>;
287 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
288 clock-names = "baudclk", "apb_pclk";
289 pinctrl-names = "default";
290 pinctrl-0 = <&uart1_xfer>;
291 reg-shift = <2>;
292 reg-io-width = <4>;
293 status = "disabled";
294 };
295
296 uart2: serial@11030000 {
297 compatible = "snps,dw-apb-uart";
298 reg = <0x11030000 0x100>;
299 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
300 clock-frequency = <24000000>;
301 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
302 clock-names = "baudclk", "apb_pclk";
303 pinctrl-names = "default";
304 pinctrl-0 = <&uart2_xfer>;
305 reg-shift = <2>;
306 reg-io-width = <4>;
307 status = "disabled";
308 };
309
Finley Xiao9098be62017-06-22 18:32:40 +0800310 efuse: efuse@11040000 {
311 compatible = "rockchip,rk3228-efuse";
312 reg = <0x11040000 0x20>;
313 clocks = <&cru PCLK_EFUSE_256>;
314 clock-names = "pclk_efuse";
315 #address-cells = <1>;
316 #size-cells = <1>;
317
318 /* Data cells */
319 efuse_id: id@7 {
320 reg = <0x7 0x10>;
321 };
322 cpu_leakage: cpu_leakage@17 {
323 reg = <0x17 0x1>;
324 };
325 };
326
Yakir Yangd549df42016-03-14 11:11:42 +0800327 i2c0: i2c@11050000 {
328 compatible = "rockchip,rk3228-i2c";
329 reg = <0x11050000 0x1000>;
330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 clock-names = "i2c";
334 clocks = <&cru PCLK_I2C0>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c0_xfer>;
337 status = "disabled";
338 };
339
340 i2c1: i2c@11060000 {
341 compatible = "rockchip,rk3228-i2c";
342 reg = <0x11060000 0x1000>;
343 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clock-names = "i2c";
347 clocks = <&cru PCLK_I2C1>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c1_xfer>;
350 status = "disabled";
351 };
352
353 i2c2: i2c@11070000 {
354 compatible = "rockchip,rk3228-i2c";
355 reg = <0x11070000 0x1000>;
356 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 clock-names = "i2c";
360 clocks = <&cru PCLK_I2C2>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c2_xfer>;
363 status = "disabled";
364 };
365
366 i2c3: i2c@11080000 {
367 compatible = "rockchip,rk3228-i2c";
368 reg = <0x11080000 0x1000>;
369 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 clock-names = "i2c";
373 clocks = <&cru PCLK_I2C3>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c3_xfer>;
376 status = "disabled";
377 };
378
Huibin Hongfebdf632017-08-03 10:36:49 +0800379 spi0: spi@11090000 {
380 compatible = "rockchip,rk3228-spi";
381 reg = <0x11090000 0x1000>;
382 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
386 clock-names = "spiclk", "apb_pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
389 status = "disabled";
390 };
391
Frank Wangfa206982017-05-17 17:52:26 +0800392 wdt: watchdog@110a0000 {
393 compatible = "snps,dw-wdt";
394 reg = <0x110a0000 0x100>;
395 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru PCLK_CPU>;
397 status = "disabled";
398 };
399
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800400 pwm0: pwm@110b0000 {
401 compatible = "rockchip,rk3288-pwm";
402 reg = <0x110b0000 0x10>;
403 #pwm-cells = <3>;
404 clocks = <&cru PCLK_PWM>;
405 clock-names = "pwm";
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm0_pin>;
408 status = "disabled";
409 };
410
411 pwm1: pwm@110b0010 {
412 compatible = "rockchip,rk3288-pwm";
413 reg = <0x110b0010 0x10>;
414 #pwm-cells = <3>;
415 clocks = <&cru PCLK_PWM>;
416 clock-names = "pwm";
417 pinctrl-names = "default";
418 pinctrl-0 = <&pwm1_pin>;
419 status = "disabled";
420 };
421
422 pwm2: pwm@110b0020 {
423 compatible = "rockchip,rk3288-pwm";
424 reg = <0x110b0020 0x10>;
425 #pwm-cells = <3>;
426 clocks = <&cru PCLK_PWM>;
427 clock-names = "pwm";
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm2_pin>;
430 status = "disabled";
431 };
432
433 pwm3: pwm@110b0030 {
434 compatible = "rockchip,rk3288-pwm";
435 reg = <0x110b0030 0x10>;
436 #pwm-cells = <2>;
437 clocks = <&cru PCLK_PWM>;
438 clock-names = "pwm";
439 pinctrl-names = "default";
440 pinctrl-0 = <&pwm3_pin>;
441 status = "disabled";
442 };
443
444 timer: timer@110c0000 {
Alexander Kochetkovb72af342017-01-31 15:43:13 +0300445 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800446 reg = <0x110c0000 0x20>;
447 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&xin24m>, <&cru PCLK_TIMER>;
449 clock-names = "timer", "pclk";
450 };
451
452 cru: clock-controller@110e0000 {
453 compatible = "rockchip,rk3228-cru";
454 reg = <0x110e0000 0x1000>;
455 rockchip,grf = <&grf>;
456 #clock-cells = <1>;
457 #reset-cells = <1>;
Elaine Zhang30ee5812017-05-17 18:16:14 +0800458 assigned-clocks =
459 <&cru PLL_GPLL>, <&cru ARMCLK>,
460 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
461 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
462 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
463 <&cru PCLK_CPU>;
464 assigned-clock-rates =
465 <594000000>, <816000000>,
466 <500000000>, <150000000>,
467 <150000000>, <75000000>,
468 <150000000>, <150000000>,
469 <75000000>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800470 };
471
Caesar Wang77960312016-02-15 15:33:32 +0800472 thermal-zones {
473 cpu_thermal: cpu-thermal {
474 polling-delay-passive = <100>; /* milliseconds */
475 polling-delay = <5000>; /* milliseconds */
476
477 thermal-sensors = <&tsadc 0>;
478
479 trips {
480 cpu_alert0: cpu_alert0 {
481 temperature = <70000>; /* millicelsius */
482 hysteresis = <2000>; /* millicelsius */
483 type = "passive";
484 };
485 cpu_alert1: cpu_alert1 {
486 temperature = <75000>; /* millicelsius */
487 hysteresis = <2000>; /* millicelsius */
488 type = "passive";
489 };
490 cpu_crit: cpu_crit {
491 temperature = <90000>; /* millicelsius */
492 hysteresis = <2000>; /* millicelsius */
493 type = "critical";
494 };
495 };
496
497 cooling-maps {
498 map0 {
499 trip = <&cpu_alert0>;
500 cooling-device =
Viresh Kumar99935bd2018-11-16 15:31:13 +0530501 <&cpu0 THERMAL_NO_LIMIT 6>,
502 <&cpu1 THERMAL_NO_LIMIT 6>,
503 <&cpu2 THERMAL_NO_LIMIT 6>,
504 <&cpu3 THERMAL_NO_LIMIT 6>;
Caesar Wang77960312016-02-15 15:33:32 +0800505 };
506 map1 {
507 trip = <&cpu_alert1>;
508 cooling-device =
Viresh Kumar99935bd2018-11-16 15:31:13 +0530509 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
510 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
511 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
512 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
Caesar Wang77960312016-02-15 15:33:32 +0800513 };
514 };
515 };
516 };
517
518 tsadc: tsadc@11150000 {
519 compatible = "rockchip,rk3228-tsadc";
520 reg = <0x11150000 0x100>;
521 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
523 clock-names = "tsadc", "apb_pclk";
Rocky Hao2b3f2f32017-05-17 18:16:17 +0800524 assigned-clocks = <&cru SCLK_TSADC>;
525 assigned-clock-rates = <32768>;
Caesar Wang77960312016-02-15 15:33:32 +0800526 resets = <&cru SRST_TSADC>;
527 reset-names = "tsadc-apb";
528 pinctrl-names = "init", "default", "sleep";
529 pinctrl-0 = <&otp_gpio>;
530 pinctrl-1 = <&otp_out>;
531 pinctrl-2 = <&otp_gpio>;
532 #thermal-sensor-cells = <0>;
533 rockchip,hw-tshut-temp = <95000>;
534 status = "disabled";
535 };
536
Justin Swartz519574e2019-06-13 10:13:04 +0000537 hdmi_phy: hdmi-phy@12030000 {
538 compatible = "rockchip,rk3228-hdmi-phy";
539 reg = <0x12030000 0x10000>;
540 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
541 clock-names = "sysclk", "refoclk", "refpclk";
542 #clock-cells = <0>;
543 clock-output-names = "hdmiphy_phy";
544 #phy-cells = <0>;
545 status = "disabled";
546 };
547
Heiko Stuebner451ef432017-07-12 19:07:05 +0200548 gpu: gpu@20000000 {
549 compatible = "rockchip,rk3228-mali", "arm,mali-400";
550 reg = <0x20000000 0x10000>;
551 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "gp",
558 "gpmmu",
559 "pp0",
Heiko Stuebner0133c492017-10-10 11:04:33 +0200560 "ppmmu0",
Heiko Stuebner451ef432017-07-12 19:07:05 +0200561 "pp1",
Heiko Stuebner0133c492017-10-10 11:04:33 +0200562 "ppmmu1";
Heiko Stuebner451ef432017-07-12 19:07:05 +0200563 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
564 clock-names = "core", "bus";
565 resets = <&cru SRST_GPU_A>;
566 status = "disabled";
567 };
568
Simon Xue4e1b2222017-07-24 10:32:08 +0800569 vpu_mmu: iommu@20020800 {
570 compatible = "rockchip,iommu";
571 reg = <0x20020800 0x100>;
572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "vpu_mmu";
Jeffy Chenc78751f2018-03-23 15:38:07 +0800574 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
575 clock-names = "aclk", "iface";
Simon Xue4e1b2222017-07-24 10:32:08 +0800576 iommu-cells = <0>;
577 status = "disabled";
578 };
579
580 vdec_mmu: iommu@20030480 {
581 compatible = "rockchip,iommu";
582 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
583 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-names = "vdec_mmu";
Jeffy Chenc78751f2018-03-23 15:38:07 +0800585 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
586 clock-names = "aclk", "iface";
Simon Xue4e1b2222017-07-24 10:32:08 +0800587 iommu-cells = <0>;
588 status = "disabled";
589 };
590
Justin Swartz519574e2019-06-13 10:13:04 +0000591 vop: vop@20050000 {
592 compatible = "rockchip,rk3228-vop";
593 reg = <0x20050000 0x1ffc>;
594 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
596 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
597 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
598 reset-names = "axi", "ahb", "dclk";
599 iommus = <&vop_mmu>;
600 status = "disabled";
601
602 vop_out: port {
603 #address-cells = <1>;
604 #size-cells = <0>;
605
606 vop_out_hdmi: endpoint@0 {
607 reg = <0>;
608 remote-endpoint = <&hdmi_in_vop>;
609 };
610 };
611 };
612
Simon Xue4e1b2222017-07-24 10:32:08 +0800613 vop_mmu: iommu@20053f00 {
614 compatible = "rockchip,iommu";
615 reg = <0x20053f00 0x100>;
616 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "vop_mmu";
Jeffy Chenc78751f2018-03-23 15:38:07 +0800618 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
619 clock-names = "aclk", "iface";
Justin Swartz836e2ab2019-06-14 11:05:12 +0200620 #iommu-cells = <0>;
Simon Xue4e1b2222017-07-24 10:32:08 +0800621 status = "disabled";
622 };
623
624 iep_mmu: iommu@20070800 {
625 compatible = "rockchip,iommu";
626 reg = <0x20070800 0x100>;
627 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-names = "iep_mmu";
Jeffy Chenc78751f2018-03-23 15:38:07 +0800629 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
630 clock-names = "aclk", "iface";
Simon Xue4e1b2222017-07-24 10:32:08 +0800631 iommu-cells = <0>;
632 status = "disabled";
633 };
634
Justin Swartz519574e2019-06-13 10:13:04 +0000635 hdmi: hdmi@200a0000 {
636 compatible = "rockchip,rk3228-dw-hdmi";
637 reg = <0x200a0000 0x20000>;
638 reg-io-width = <4>;
639 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
640 assigned-clocks = <&cru SCLK_HDMI_PHY>;
641 assigned-clock-parents = <&hdmi_phy>;
642 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
643 clock-names = "isfr", "iahb", "cec";
644 pinctrl-names = "default";
645 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
646 resets = <&cru SRST_HDMI_P>;
647 reset-names = "hdmi";
648 phys = <&hdmi_phy>;
649 phy-names = "hdmi";
650 rockchip,grf = <&grf>;
651 status = "disabled";
652
653 ports {
654 hdmi_in: port {
655 #address-cells = <1>;
656 #size-cells = <0>;
657 hdmi_in_vop: endpoint@0 {
658 reg = <0>;
659 remote-endpoint = <&vop_out_hdmi>;
660 };
661 };
662 };
663 };
664
Johan Jonkerfed1fc52020-01-15 19:52:43 +0100665 sdmmc: mmc@30000000 {
Shawn Line409fc32017-06-22 18:32:04 +0800666 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
667 reg = <0x30000000 0x4000>;
668 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
670 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
Robin Murphye78c6372018-02-15 14:05:54 +0000671 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Shawn Line409fc32017-06-22 18:32:04 +0800672 fifo-depth = <0x100>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
675 status = "disabled";
676 };
677
Johan Jonkerfed1fc52020-01-15 19:52:43 +0100678 sdio: mmc@30010000 {
Shawn Line409fc32017-06-22 18:32:04 +0800679 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
680 reg = <0x30010000 0x4000>;
681 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
683 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
Robin Murphye78c6372018-02-15 14:05:54 +0000684 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Shawn Line409fc32017-06-22 18:32:04 +0800685 fifo-depth = <0x100>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
688 status = "disabled";
689 };
690
Johan Jonkerfed1fc52020-01-15 19:52:43 +0100691 emmc: mmc@30020000 {
Shawn Lin0d6a01f2017-06-22 18:29:59 +0800692 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800693 reg = <0x30020000 0x4000>;
694 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
695 clock-frequency = <37500000>;
Jaehoon Chung6a8883d2016-11-03 15:21:33 +0900696 max-frequency = <37500000>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800697 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
698 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
Robin Murphye78c6372018-02-15 14:05:54 +0000699 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800700 bus-width = <8>;
Johan Jonker8a385eb2020-03-07 14:48:38 +0100701 rockchip,default-sample-phase = <158>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800702 fifo-depth = <0x100>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
Heiko Stuebner2d1f1d42017-03-02 00:50:39 +0100705 resets = <&cru SRST_EMMC>;
706 reset-names = "reset";
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800707 status = "disabled";
708 };
709
William Wu3880af42017-06-02 15:04:24 +0800710 usb_otg: usb@30040000 {
711 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
712 "snps,dwc2";
713 reg = <0x30040000 0x40000>;
714 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&cru HCLK_OTG>;
716 clock-names = "otg";
717 dr_mode = "otg";
718 g-np-tx-fifo-size = <16>;
719 g-rx-fifo-size = <280>;
720 g-tx-fifo-size = <256 128 128 64 32 16>;
William Wu3880af42017-06-02 15:04:24 +0800721 phys = <&u2phy0_otg>;
722 phy-names = "usb2-phy";
723 status = "disabled";
724 };
725
726 usb_host0_ehci: usb@30080000 {
727 compatible = "generic-ehci";
728 reg = <0x30080000 0x20000>;
729 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
731 clock-names = "usbhost", "utmi";
732 phys = <&u2phy0_host>;
733 phy-names = "usb";
734 status = "disabled";
735 };
736
737 usb_host0_ohci: usb@300a0000 {
738 compatible = "generic-ohci";
739 reg = <0x300a0000 0x20000>;
740 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
742 clock-names = "usbhost", "utmi";
743 phys = <&u2phy0_host>;
744 phy-names = "usb";
745 status = "disabled";
746 };
747
748 usb_host1_ehci: usb@300c0000 {
749 compatible = "generic-ehci";
750 reg = <0x300c0000 0x20000>;
751 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
753 clock-names = "usbhost", "utmi";
754 phys = <&u2phy1_otg>;
755 phy-names = "usb";
756 status = "disabled";
757 };
758
759 usb_host1_ohci: usb@300e0000 {
760 compatible = "generic-ohci";
761 reg = <0x300e0000 0x20000>;
762 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
764 clock-names = "usbhost", "utmi";
765 phys = <&u2phy1_otg>;
766 phy-names = "usb";
767 status = "disabled";
768 };
769
770 usb_host2_ehci: usb@30100000 {
771 compatible = "generic-ehci";
772 reg = <0x30100000 0x20000>;
773 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
775 phys = <&u2phy1_host>;
776 phy-names = "usb";
777 clock-names = "usbhost", "utmi";
778 status = "disabled";
779 };
780
781 usb_host2_ohci: usb@30120000 {
782 compatible = "generic-ohci";
783 reg = <0x30120000 0x20000>;
784 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
786 clock-names = "usbhost", "utmi";
787 phys = <&u2phy1_host>;
788 phy-names = "usb";
789 status = "disabled";
790 };
791
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800792 gmac: ethernet@30200000 {
793 compatible = "rockchip,rk3228-gmac";
794 reg = <0x30200000 0x10000>;
795 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
796 interrupt-names = "macirq";
797 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
798 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
799 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
800 <&cru PCLK_GMAC>;
801 clock-names = "stmmaceth", "mac_clk_rx",
802 "mac_clk_tx", "clk_mac_ref",
803 "clk_mac_refout", "aclk_mac",
804 "pclk_mac";
805 resets = <&cru SRST_GMAC>;
806 reset-names = "stmmaceth";
807 rockchip,grf = <&grf>;
808 status = "disabled";
809 };
810
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800811 gic: interrupt-controller@32010000 {
812 compatible = "arm,gic-400";
813 interrupt-controller;
814 #interrupt-cells = <3>;
815 #address-cells = <0>;
816
817 reg = <0x32011000 0x1000>,
Marc Zyngier387720c2017-01-18 09:27:28 +0000818 <0x32012000 0x2000>,
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800819 <0x32014000 0x2000>,
820 <0x32016000 0x2000>;
821 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
822 };
823
824 pinctrl: pinctrl {
825 compatible = "rockchip,rk3228-pinctrl";
826 rockchip,grf = <&grf>;
827 #address-cells = <1>;
828 #size-cells = <1>;
829 ranges;
830
831 gpio0: gpio0@11110000 {
832 compatible = "rockchip,gpio-bank";
833 reg = <0x11110000 0x100>;
834 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&cru PCLK_GPIO0>;
836
837 gpio-controller;
838 #gpio-cells = <2>;
839
840 interrupt-controller;
841 #interrupt-cells = <2>;
842 };
843
844 gpio1: gpio1@11120000 {
845 compatible = "rockchip,gpio-bank";
846 reg = <0x11120000 0x100>;
847 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&cru PCLK_GPIO1>;
849
850 gpio-controller;
851 #gpio-cells = <2>;
852
853 interrupt-controller;
854 #interrupt-cells = <2>;
855 };
856
857 gpio2: gpio2@11130000 {
858 compatible = "rockchip,gpio-bank";
859 reg = <0x11130000 0x100>;
860 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&cru PCLK_GPIO2>;
862
863 gpio-controller;
864 #gpio-cells = <2>;
865
866 interrupt-controller;
867 #interrupt-cells = <2>;
868 };
869
870 gpio3: gpio3@11140000 {
871 compatible = "rockchip,gpio-bank";
872 reg = <0x11140000 0x100>;
873 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&cru PCLK_GPIO3>;
875
876 gpio-controller;
877 #gpio-cells = <2>;
878
879 interrupt-controller;
880 #interrupt-cells = <2>;
881 };
882
883 pcfg_pull_up: pcfg-pull-up {
884 bias-pull-up;
885 };
886
887 pcfg_pull_down: pcfg-pull-down {
888 bias-pull-down;
889 };
890
891 pcfg_pull_none: pcfg-pull-none {
892 bias-disable;
893 };
894
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800895 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
896 drive-strength = <12>;
897 };
898
Shawn Line409fc32017-06-22 18:32:04 +0800899 sdmmc {
900 sdmmc_clk: sdmmc-clk {
901 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
902 };
903
904 sdmmc_cmd: sdmmc-cmd {
905 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
906 };
907
908 sdmmc_bus4: sdmmc-bus4 {
909 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
910 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
911 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
912 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
913 };
914 };
915
916 sdio {
917 sdio_clk: sdio-clk {
918 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
919 };
920
921 sdio_cmd: sdio-cmd {
922 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
923 };
924
925 sdio_bus4: sdio-bus4 {
926 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
927 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
928 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
929 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
930 };
931 };
932
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800933 emmc {
934 emmc_clk: emmc-clk {
Heiko Stuebner07f08d92019-04-02 14:08:57 +0200935 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800936 };
937
938 emmc_cmd: emmc-cmd {
Heiko Stuebner07f08d92019-04-02 14:08:57 +0200939 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800940 };
941
942 emmc_bus8: emmc-bus8 {
Heiko Stuebner07f08d92019-04-02 14:08:57 +0200943 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
944 <1 RK_PD1 2 &pcfg_pull_none>,
945 <1 RK_PD2 2 &pcfg_pull_none>,
946 <1 RK_PD3 2 &pcfg_pull_none>,
947 <1 RK_PD4 2 &pcfg_pull_none>,
948 <1 RK_PD5 2 &pcfg_pull_none>,
949 <1 RK_PD6 2 &pcfg_pull_none>,
950 <1 RK_PD7 2 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +0800951 };
952 };
953
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800954 gmac {
955 rgmii_pins: rgmii-pins {
Heiko Stuebner07f08d92019-04-02 14:08:57 +0200956 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
957 <2 RK_PB4 1 &pcfg_pull_none>,
958 <2 RK_PD1 1 &pcfg_pull_none>,
959 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
960 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
961 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
962 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
963 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
964 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
965 <2 RK_PC1 1 &pcfg_pull_none>,
966 <2 RK_PC0 1 &pcfg_pull_none>,
967 <2 RK_PC5 2 &pcfg_pull_none>,
968 <2 RK_PC4 2 &pcfg_pull_none>,
969 <2 RK_PB3 1 &pcfg_pull_none>,
970 <2 RK_PB0 1 &pcfg_pull_none>;
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800971 };
972
973 rmii_pins: rmii-pins {
Heiko Stuebner07f08d92019-04-02 14:08:57 +0200974 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
975 <2 RK_PB4 1 &pcfg_pull_none>,
976 <2 RK_PD1 1 &pcfg_pull_none>,
977 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
978 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
979 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
980 <2 RK_PC1 1 &pcfg_pull_none>,
981 <2 RK_PC0 1 &pcfg_pull_none>,
982 <2 RK_PB0 1 &pcfg_pull_none>,
983 <2 RK_PB7 1 &pcfg_pull_none>;
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800984 };
985
986 phy_pins: phy-pins {
Heiko Stuebner07f08d92019-04-02 14:08:57 +0200987 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
988 <2 RK_PB0 2 &pcfg_pull_none>;
Xing Zheng5d3d7c72016-06-22 11:16:52 +0800989 };
990 };
991
Justin Swartz519574e2019-06-13 10:13:04 +0000992 hdmi {
993 hdmi_hpd: hdmi-hpd {
994 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
995 };
996
997 hdmii2c_xfer: hdmii2c-xfer {
998 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
999 <0 RK_PA7 2 &pcfg_pull_none>;
1000 };
1001
1002 hdmi_cec: hdmi-cec {
1003 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1004 };
1005 };
1006
Yakir Yangd549df42016-03-14 11:11:42 +08001007 i2c0 {
1008 i2c0_xfer: i2c0-xfer {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001009 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1010 <0 RK_PA1 1 &pcfg_pull_none>;
Yakir Yangd549df42016-03-14 11:11:42 +08001011 };
1012 };
1013
1014 i2c1 {
1015 i2c1_xfer: i2c1-xfer {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001016 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1017 <0 RK_PA3 1 &pcfg_pull_none>;
Yakir Yangd549df42016-03-14 11:11:42 +08001018 };
1019 };
1020
1021 i2c2 {
1022 i2c2_xfer: i2c2-xfer {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001023 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1024 <2 RK_PC5 1 &pcfg_pull_none>;
Yakir Yangd549df42016-03-14 11:11:42 +08001025 };
1026 };
1027
1028 i2c3 {
1029 i2c3_xfer: i2c3-xfer {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001030 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1031 <0 RK_PA7 1 &pcfg_pull_none>;
Yakir Yangd549df42016-03-14 11:11:42 +08001032 };
1033 };
1034
Huibin Hongfebdf632017-08-03 10:36:49 +08001035 spi-0 {
1036 spi0_clk: spi0-clk {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001037 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001038 };
1039 spi0_cs0: spi0-cs0 {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001040 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001041 };
1042 spi0_tx: spi0-tx {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001043 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001044 };
1045 spi0_rx: spi0-rx {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001046 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001047 };
1048 spi0_cs1: spi0-cs1 {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001049 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001050 };
1051 };
1052
1053 spi-1 {
1054 spi1_clk: spi1-clk {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001055 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001056 };
1057 spi1_cs0: spi1-cs0 {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001058 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001059 };
1060 spi1_rx: spi1-rx {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001061 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001062 };
1063 spi1_tx: spi1-tx {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001064 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001065 };
1066 spi1_cs1: spi1-cs1 {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001067 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
Huibin Hongfebdf632017-08-03 10:36:49 +08001068 };
1069 };
1070
Xing Zhengccada242016-06-22 11:16:51 +08001071 i2s1 {
1072 i2s1_bus: i2s1-bus {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001073 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1074 <0 RK_PB1 1 &pcfg_pull_none>,
1075 <0 RK_PB3 1 &pcfg_pull_none>,
1076 <0 RK_PB4 1 &pcfg_pull_none>,
1077 <0 RK_PB5 1 &pcfg_pull_none>,
1078 <0 RK_PB6 1 &pcfg_pull_none>,
1079 <1 RK_PA2 2 &pcfg_pull_none>,
1080 <1 RK_PA4 2 &pcfg_pull_none>,
1081 <1 RK_PA5 2 &pcfg_pull_none>;
Xing Zhengccada242016-06-22 11:16:51 +08001082 };
1083 };
1084
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001085 pwm0 {
1086 pwm0_pin: pwm0-pin {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001087 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001088 };
1089 };
1090
1091 pwm1 {
1092 pwm1_pin: pwm1-pin {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001093 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001094 };
1095 };
1096
1097 pwm2 {
1098 pwm2_pin: pwm2-pin {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001099 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001100 };
1101 };
1102
1103 pwm3 {
1104 pwm3_pin: pwm3-pin {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001105 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001106 };
1107 };
1108
Sugar Zhang4b456d22017-06-09 15:59:33 +08001109 spdif {
1110 spdif_tx: spdif-tx {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001111 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
Sugar Zhang4b456d22017-06-09 15:59:33 +08001112 };
1113 };
1114
Caesar Wang77960312016-02-15 15:33:32 +08001115 tsadc {
1116 otp_gpio: otp-gpio {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001117 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
Caesar Wang77960312016-02-15 15:33:32 +08001118 };
1119
1120 otp_out: otp-out {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001121 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
Caesar Wang77960312016-02-15 15:33:32 +08001122 };
1123 };
1124
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001125 uart0 {
1126 uart0_xfer: uart0-xfer {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001127 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1128 <2 RK_PD3 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001129 };
1130
1131 uart0_cts: uart0-cts {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001132 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001133 };
1134
1135 uart0_rts: uart0-rts {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001136 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001137 };
1138 };
1139
1140 uart1 {
1141 uart1_xfer: uart1-xfer {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001142 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1143 <1 RK_PB2 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001144 };
1145
1146 uart1_cts: uart1-cts {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001147 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001148 };
1149
1150 uart1_rts: uart1-rts {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001151 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001152 };
1153 };
1154
1155 uart2 {
1156 uart2_xfer: uart2-xfer {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001157 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1158 <1 RK_PC3 2 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001159 };
1160
Frank Wang738e4512017-05-17 17:52:25 +08001161 uart21_xfer: uart21-xfer {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001162 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1163 <1 RK_PB1 2 &pcfg_pull_none>;
Frank Wang738e4512017-05-17 17:52:25 +08001164 };
1165
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001166 uart2_cts: uart2-cts {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001167 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001168 };
1169
1170 uart2_rts: uart2-rts {
Heiko Stuebner07f08d92019-04-02 14:08:57 +02001171 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
Jeffy Chen9848ebe2015-12-11 09:30:51 +08001172 };
1173 };
1174 };
1175};