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Andrew Lunna2443fd2019-01-21 19:05:50 +01001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming00db8182005-07-30 19:31:23 -04002/*
3 * drivers/net/phy/davicom.c
4 *
5 * Driver for Davicom PHYs
6 *
7 * Author: Andy Fleming
8 *
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
Andy Fleming00db8182005-07-30 19:31:23 -040010 */
Andy Fleming00db8182005-07-30 19:31:23 -040011#include <linux/kernel.h>
Andy Fleming00db8182005-07-30 19:31:23 -040012#include <linux/string.h>
13#include <linux/errno.h>
14#include <linux/unistd.h>
Andy Fleming00db8182005-07-30 19:31:23 -040015#include <linux/interrupt.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
20#include <linux/skbuff.h>
21#include <linux/spinlock.h>
22#include <linux/mm.h>
23#include <linux/module.h>
Andy Fleming00db8182005-07-30 19:31:23 -040024#include <linux/mii.h>
25#include <linux/ethtool.h>
26#include <linux/phy.h>
27
28#include <asm/io.h>
29#include <asm/irq.h>
Linus Torvalds7c0f6ba2016-12-24 11:46:01 -080030#include <linux/uaccess.h>
Andy Fleming00db8182005-07-30 19:31:23 -040031
32#define MII_DM9161_SCR 0x10
33#define MII_DM9161_SCR_INIT 0x0610
frederic Rodo8b7c1662008-02-27 12:58:37 +010034#define MII_DM9161_SCR_RMII 0x0100
Andy Fleming00db8182005-07-30 19:31:23 -040035
36/* DM9161 Interrupt Register */
37#define MII_DM9161_INTR 0x15
38#define MII_DM9161_INTR_PEND 0x8000
39#define MII_DM9161_INTR_DPLX_MASK 0x0800
40#define MII_DM9161_INTR_SPD_MASK 0x0400
41#define MII_DM9161_INTR_LINK_MASK 0x0200
42#define MII_DM9161_INTR_MASK 0x0100
43#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
44#define MII_DM9161_INTR_SPD_CHANGE 0x0008
45#define MII_DM9161_INTR_LINK_CHANGE 0x0004
46#define MII_DM9161_INTR_INIT 0x0000
47#define MII_DM9161_INTR_STOP \
48(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
49 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
50
51/* DM9161 10BT Configuration/Status */
52#define MII_DM9161_10BTCSR 0x12
53#define MII_DM9161_10BTCSR_INIT 0x7800
54
55MODULE_DESCRIPTION("Davicom PHY driver");
56MODULE_AUTHOR("Andy Fleming");
57MODULE_LICENSE("GPL");
58
59
60#define DM9161_DELAY 1
61static int dm9161_config_intr(struct phy_device *phydev)
62{
63 int temp;
64
65 temp = phy_read(phydev, MII_DM9161_INTR);
66
67 if (temp < 0)
68 return temp;
69
Florian Fainellia60e7e12013-12-17 21:38:06 -080070 if (PHY_INTERRUPT_ENABLED == phydev->interrupts)
Andy Fleming00db8182005-07-30 19:31:23 -040071 temp &= ~(MII_DM9161_INTR_STOP);
72 else
73 temp |= MII_DM9161_INTR_STOP;
74
75 temp = phy_write(phydev, MII_DM9161_INTR, temp);
76
77 return temp;
78}
79
80static int dm9161_config_aneg(struct phy_device *phydev)
81{
82 int err;
83
84 /* Isolate the PHY */
85 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
86
87 if (err < 0)
88 return err;
89
90 /* Configure the new settings */
91 err = genphy_config_aneg(phydev);
92
93 if (err < 0)
94 return err;
95
96 return 0;
97}
98
99static int dm9161_config_init(struct phy_device *phydev)
100{
frederic Rodo8b7c1662008-02-27 12:58:37 +0100101 int err, temp;
Andy Fleming00db8182005-07-30 19:31:23 -0400102
103 /* Isolate the PHY */
104 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
105
106 if (err < 0)
107 return err;
108
frederic Rodo8b7c1662008-02-27 12:58:37 +0100109 switch (phydev->interface) {
110 case PHY_INTERFACE_MODE_MII:
111 temp = MII_DM9161_SCR_INIT;
112 break;
113 case PHY_INTERFACE_MODE_RMII:
114 temp = MII_DM9161_SCR_INIT | MII_DM9161_SCR_RMII;
115 break;
116 default:
117 return -EINVAL;
118 }
Andy Fleming00db8182005-07-30 19:31:23 -0400119
frederic Rodo8b7c1662008-02-27 12:58:37 +0100120 /* Do not bypass the scrambler/descrambler */
121 err = phy_write(phydev, MII_DM9161_SCR, temp);
Andy Fleming00db8182005-07-30 19:31:23 -0400122 if (err < 0)
123 return err;
124
125 /* Clear 10BTCSR to default */
126 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT);
127
128 if (err < 0)
129 return err;
130
131 /* Reconnect the PHY, and enable Autonegotiation */
Srinivas Kandagatla8bc47ec2012-04-02 06:25:11 +0000132 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
Andy Fleming00db8182005-07-30 19:31:23 -0400133}
134
135static int dm9161_ack_interrupt(struct phy_device *phydev)
136{
137 int err = phy_read(phydev, MII_DM9161_INTR);
138
139 return (err < 0) ? err : 0;
140}
141
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000142static struct phy_driver dm91xx_driver[] = {
143{
Andy Fleming00db8182005-07-30 19:31:23 -0400144 .phy_id = 0x0181b880,
145 .name = "Davicom DM9161E",
146 .phy_id_mask = 0x0ffffff0,
Heiner Kallweitdcdecdc2019-04-12 20:47:03 +0200147 /* PHY_BASIC_FEATURES */
Andy Fleming00db8182005-07-30 19:31:23 -0400148 .config_init = dm9161_config_init,
149 .config_aneg = dm9161_config_aneg,
Joachim Eastwood63f71dd2012-11-11 13:56:26 +0000150 .ack_interrupt = dm9161_ack_interrupt,
151 .config_intr = dm9161_config_intr,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000152}, {
Gustavo Zacarias10592612015-06-10 13:48:20 -0300153 .phy_id = 0x0181b8b0,
154 .name = "Davicom DM9161B/C",
155 .phy_id_mask = 0x0ffffff0,
Heiner Kallweitdcdecdc2019-04-12 20:47:03 +0200156 /* PHY_BASIC_FEATURES */
Gustavo Zacarias10592612015-06-10 13:48:20 -0300157 .config_init = dm9161_config_init,
158 .config_aneg = dm9161_config_aneg,
Gustavo Zacarias10592612015-06-10 13:48:20 -0300159 .ack_interrupt = dm9161_ack_interrupt,
160 .config_intr = dm9161_config_intr,
Gustavo Zacarias10592612015-06-10 13:48:20 -0300161}, {
Kim Phillips12414db2007-05-10 15:16:04 -0500162 .phy_id = 0x0181b8a0,
163 .name = "Davicom DM9161A",
164 .phy_id_mask = 0x0ffffff0,
Heiner Kallweitdcdecdc2019-04-12 20:47:03 +0200165 /* PHY_BASIC_FEATURES */
Kim Phillips12414db2007-05-10 15:16:04 -0500166 .config_init = dm9161_config_init,
167 .config_aneg = dm9161_config_aneg,
Joachim Eastwood63f71dd2012-11-11 13:56:26 +0000168 .ack_interrupt = dm9161_ack_interrupt,
169 .config_intr = dm9161_config_intr,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000170}, {
Andy Fleming00db8182005-07-30 19:31:23 -0400171 .phy_id = 0x00181b80,
172 .name = "Davicom DM9131",
173 .phy_id_mask = 0x0ffffff0,
Heiner Kallweitdcdecdc2019-04-12 20:47:03 +0200174 /* PHY_BASIC_FEATURES */
Andy Fleming00db8182005-07-30 19:31:23 -0400175 .ack_interrupt = dm9161_ack_interrupt,
176 .config_intr = dm9161_config_intr,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000177} };
Andy Fleming00db8182005-07-30 19:31:23 -0400178
Johan Hovold50fd7152014-11-11 19:45:59 +0100179module_phy_driver(dm91xx_driver);
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000180
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000181static struct mdio_device_id __maybe_unused davicom_tbl[] = {
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000182 { 0x0181b880, 0x0ffffff0 },
Gustavo Zacarias10592612015-06-10 13:48:20 -0300183 { 0x0181b8b0, 0x0ffffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000184 { 0x0181b8a0, 0x0ffffff0 },
185 { 0x00181b80, 0x0ffffff0 },
186 { }
187};
188
189MODULE_DEVICE_TABLE(mdio, davicom_tbl);