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Alex Elder1ed7d0c2020-03-05 22:28:18 -06001// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2020 Linaro Ltd.
5 */
6
7#include <linux/log2.h>
8
9#include "gsi.h"
10#include "ipa_data.h"
11#include "ipa_endpoint.h"
12#include "ipa_mem.h"
13
14/* Endpoint configuration for the SDM845 SoC. */
15static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
16 [IPA_ENDPOINT_AP_COMMAND_TX] = {
17 .ee_id = GSI_EE_AP,
18 .channel_id = 4,
19 .endpoint_id = 5,
20 .toward_ipa = true,
21 .channel = {
22 .tre_count = 512,
23 .event_count = 256,
24 .tlv_count = 20,
25 },
26 .endpoint = {
27 .seq_type = IPA_SEQ_DMA_ONLY,
28 .config = {
29 .dma_mode = true,
30 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
31 },
32 },
33 },
34 [IPA_ENDPOINT_AP_LAN_RX] = {
35 .ee_id = GSI_EE_AP,
36 .channel_id = 5,
37 .endpoint_id = 9,
38 .toward_ipa = false,
39 .channel = {
40 .tre_count = 256,
41 .event_count = 256,
42 .tlv_count = 8,
43 },
44 .endpoint = {
45 .seq_type = IPA_SEQ_INVALID,
46 .config = {
Alex Elder1ed7d0c2020-03-05 22:28:18 -060047 .aggregation = true,
48 .status_enable = true,
49 .rx = {
50 .pad_align = ilog2(sizeof(u32)),
51 },
52 },
53 },
54 },
55 [IPA_ENDPOINT_AP_MODEM_TX] = {
56 .ee_id = GSI_EE_AP,
57 .channel_id = 3,
58 .endpoint_id = 2,
59 .toward_ipa = true,
60 .channel = {
61 .tre_count = 512,
62 .event_count = 512,
63 .tlv_count = 16,
64 },
65 .endpoint = {
66 .filter_support = true,
67 .seq_type =
68 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
69 .config = {
70 .checksum = true,
71 .qmap = true,
72 .status_enable = true,
73 .tx = {
74 .status_endpoint =
75 IPA_ENDPOINT_MODEM_AP_RX,
Alex Elder1ed7d0c2020-03-05 22:28:18 -060076 },
77 },
78 },
79 },
80 [IPA_ENDPOINT_AP_MODEM_RX] = {
81 .ee_id = GSI_EE_AP,
82 .channel_id = 6,
83 .endpoint_id = 10,
84 .toward_ipa = false,
85 .channel = {
86 .tre_count = 256,
87 .event_count = 256,
88 .tlv_count = 8,
89 },
90 .endpoint = {
91 .seq_type = IPA_SEQ_INVALID,
92 .config = {
93 .checksum = true,
94 .qmap = true,
95 .aggregation = true,
96 .rx = {
97 .aggr_close_eof = true,
98 },
99 },
100 },
101 },
102 [IPA_ENDPOINT_MODEM_COMMAND_TX] = {
103 .ee_id = GSI_EE_MODEM,
104 .channel_id = 1,
105 .endpoint_id = 4,
106 .toward_ipa = true,
107 },
108 [IPA_ENDPOINT_MODEM_LAN_TX] = {
109 .ee_id = GSI_EE_MODEM,
110 .channel_id = 0,
111 .endpoint_id = 3,
112 .toward_ipa = true,
113 .endpoint = {
114 .filter_support = true,
115 },
116 },
117 [IPA_ENDPOINT_MODEM_LAN_RX] = {
118 .ee_id = GSI_EE_MODEM,
119 .channel_id = 3,
120 .endpoint_id = 13,
121 .toward_ipa = false,
122 },
123 [IPA_ENDPOINT_MODEM_AP_TX] = {
124 .ee_id = GSI_EE_MODEM,
125 .channel_id = 4,
126 .endpoint_id = 6,
127 .toward_ipa = true,
128 .endpoint = {
129 .filter_support = true,
130 },
131 },
132 [IPA_ENDPOINT_MODEM_AP_RX] = {
133 .ee_id = GSI_EE_MODEM,
134 .channel_id = 2,
135 .endpoint_id = 12,
136 .toward_ipa = false,
137 },
138};
139
140/* For the SDM845, resource groups are allocated this way:
141 * group 0: LWA_DL
142 * group 1: UL_DL
143 */
144static const struct ipa_resource_src ipa_resource_src[] = {
145 {
146 .type = IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS,
147 .limits[0] = {
148 .min = 1,
149 .max = 63,
150 },
151 .limits[1] = {
152 .min = 1,
153 .max = 63,
154 },
155 },
156 {
157 .type = IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
158 .limits[0] = {
159 .min = 10,
160 .max = 10,
161 },
162 .limits[1] = {
163 .min = 10,
164 .max = 10,
165 },
166 },
167 {
168 .type = IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
169 .limits[0] = {
170 .min = 12,
171 .max = 12,
172 },
173 .limits[1] = {
174 .min = 14,
175 .max = 14,
176 },
177 },
178 {
179 .type = IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
180 .limits[0] = {
181 .min = 0,
182 .max = 63,
183 },
184 .limits[1] = {
185 .min = 0,
186 .max = 63,
187 },
188 },
189 {
190 .type = IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
191 .limits[0] = {
192 .min = 14,
193 .max = 14,
194 },
195 .limits[1] = {
196 .min = 20,
197 .max = 20,
198 },
199 },
200};
201
202static const struct ipa_resource_dst ipa_resource_dst[] = {
203 {
204 .type = IPA_RESOURCE_TYPE_DST_DATA_SECTORS,
205 .limits[0] = {
206 .min = 4,
207 .max = 4,
208 },
209 .limits[1] = {
210 .min = 4,
211 .max = 4,
212 },
213 },
214 {
215 .type = IPA_RESOURCE_TYPE_DST_DPS_DMARS,
216 .limits[0] = {
217 .min = 2,
218 .max = 63,
219 },
220 .limits[1] = {
221 .min = 1,
222 .max = 63,
223 },
224 },
225};
226
227/* Resource configuration for the SDM845 SoC. */
228static const struct ipa_resource_data ipa_resource_data = {
229 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
230 .resource_src = ipa_resource_src,
231 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
232 .resource_dst = ipa_resource_dst,
233};
234
235/* IPA-resident memory region configuration for the SDM845 SoC. */
Alex Elder3128aae2020-05-04 12:58:57 -0500236static const struct ipa_mem ipa_mem_local_data[] = {
Alex Elder1ed7d0c2020-03-05 22:28:18 -0600237 [IPA_MEM_UC_SHARED] = {
238 .offset = 0x0000,
239 .size = 0x0080,
240 .canary_count = 0,
241 },
242 [IPA_MEM_UC_INFO] = {
243 .offset = 0x0080,
244 .size = 0x0200,
245 .canary_count = 0,
246 },
247 [IPA_MEM_V4_FILTER_HASHED] = {
248 .offset = 0x0288,
249 .size = 0x0078,
250 .canary_count = 2,
251 },
252 [IPA_MEM_V4_FILTER] = {
253 .offset = 0x0308,
254 .size = 0x0078,
255 .canary_count = 2,
256 },
257 [IPA_MEM_V6_FILTER_HASHED] = {
258 .offset = 0x0388,
259 .size = 0x0078,
260 .canary_count = 2,
261 },
262 [IPA_MEM_V6_FILTER] = {
263 .offset = 0x0408,
264 .size = 0x0078,
265 .canary_count = 2,
266 },
267 [IPA_MEM_V4_ROUTE_HASHED] = {
268 .offset = 0x0488,
269 .size = 0x0078,
270 .canary_count = 2,
271 },
272 [IPA_MEM_V4_ROUTE] = {
273 .offset = 0x0508,
274 .size = 0x0078,
275 .canary_count = 2,
276 },
277 [IPA_MEM_V6_ROUTE_HASHED] = {
278 .offset = 0x0588,
279 .size = 0x0078,
280 .canary_count = 2,
281 },
282 [IPA_MEM_V6_ROUTE] = {
283 .offset = 0x0608,
284 .size = 0x0078,
285 .canary_count = 2,
286 },
287 [IPA_MEM_MODEM_HEADER] = {
288 .offset = 0x0688,
289 .size = 0x0140,
290 .canary_count = 2,
291 },
292 [IPA_MEM_AP_HEADER] = {
293 .offset = 0x07c8,
294 .size = 0x0000,
295 .canary_count = 0,
296 },
297 [IPA_MEM_MODEM_PROC_CTX] = {
298 .offset = 0x07d0,
299 .size = 0x0200,
300 .canary_count = 2,
301 },
302 [IPA_MEM_AP_PROC_CTX] = {
303 .offset = 0x09d0,
304 .size = 0x0200,
305 .canary_count = 0,
306 },
307 [IPA_MEM_MODEM] = {
308 .offset = 0x0bd8,
309 .size = 0x1024,
310 .canary_count = 0,
311 },
312 [IPA_MEM_UC_EVENT_RING] = {
313 .offset = 0x1c00,
314 .size = 0x0400,
315 .canary_count = 1,
316 },
317};
318
Alex Elder3128aae2020-05-04 12:58:57 -0500319static struct ipa_mem_data ipa_mem_data = {
320 .local_count = ARRAY_SIZE(ipa_mem_local_data),
321 .local = ipa_mem_local_data,
Alex Elder3e313c32020-05-04 12:58:58 -0500322 .imem_addr = 0x146bd000,
323 .imem_size = 0x00002000,
Alex Eldera0036bb2020-05-04 12:58:59 -0500324 .smem_id = 497,
325 .smem_size = 0x00002000,
Alex Elder3128aae2020-05-04 12:58:57 -0500326};
327
Alex Elder1ed7d0c2020-03-05 22:28:18 -0600328/* Configuration data for the SDM845 SoC. */
329const struct ipa_data ipa_data_sdm845 = {
330 .version = IPA_VERSION_3_5_1,
331 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
332 .endpoint_data = ipa_gsi_endpoint_data,
333 .resource_data = &ipa_resource_data,
Alex Elder3128aae2020-05-04 12:58:57 -0500334 .mem_data = &ipa_mem_data,
Alex Elder1ed7d0c2020-03-05 22:28:18 -0600335};