Thomas Gleixner | caab277 | 2019-06-03 07:44:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Catalin Marinas | 272d01b | 2016-11-03 18:34:34 +0000 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm64/include/asm/cpucaps.h |
| 4 | * |
| 5 | * Copyright (C) 2016 ARM Ltd. |
Catalin Marinas | 272d01b | 2016-11-03 18:34:34 +0000 | [diff] [blame] | 6 | */ |
| 7 | #ifndef __ASM_CPUCAPS_H |
| 8 | #define __ASM_CPUCAPS_H |
| 9 | |
| 10 | #define ARM64_WORKAROUND_CLEAN_CACHE 0 |
| 11 | #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 |
| 12 | #define ARM64_WORKAROUND_845719 2 |
| 13 | #define ARM64_HAS_SYSREG_GIC_CPUIF 3 |
| 14 | #define ARM64_HAS_PAN 4 |
| 15 | #define ARM64_HAS_LSE_ATOMICS 5 |
| 16 | #define ARM64_WORKAROUND_CAVIUM_23154 6 |
| 17 | #define ARM64_WORKAROUND_834220 7 |
| 18 | #define ARM64_HAS_NO_HW_PREFETCH 8 |
| 19 | #define ARM64_HAS_UAO 9 |
| 20 | #define ARM64_ALT_PAN_NOT_UAO 10 |
| 21 | #define ARM64_HAS_VIRT_HOST_EXTN 11 |
| 22 | #define ARM64_WORKAROUND_CAVIUM_27456 12 |
Will Deacon | 4fb1564 | 2020-10-27 20:58:29 +0000 | [diff] [blame] | 23 | /* Unreliable: use system_supports_32bit_el0() instead. */ |
| 24 | #define ARM64_HAS_32BIT_EL0_DO_NOT_USE 13 |
Will Deacon | 1be3882 | 2020-11-13 11:38:45 +0000 | [diff] [blame] | 25 | #define ARM64_SPECTRE_V3A 14 |
Will Deacon | 880f7cc | 2018-09-19 11:41:21 +0100 | [diff] [blame] | 26 | #define ARM64_HAS_CNP 15 |
Linus Torvalds | f4000cd9 | 2016-12-13 16:39:21 -0800 | [diff] [blame] | 27 | #define ARM64_HAS_NO_FPSIMD 16 |
Christopher Covington | d9ff80f | 2017-01-31 12:50:19 -0500 | [diff] [blame] | 28 | #define ARM64_WORKAROUND_REPEAT_TLBI 17 |
Christopher Covington | 38fd94b | 2017-02-08 15:08:37 -0500 | [diff] [blame] | 29 | #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 |
Marc Zyngier | eeb1efb | 2017-03-20 17:18:06 +0000 | [diff] [blame] | 30 | #define ARM64_WORKAROUND_858921 19 |
David Daney | 690a341 | 2017-06-09 12:49:48 +0100 | [diff] [blame] | 31 | #define ARM64_WORKAROUND_CAVIUM_30115 20 |
Robin Murphy | d50e071 | 2017-07-25 11:55:42 +0100 | [diff] [blame] | 32 | #define ARM64_HAS_DCPOP 21 |
Dave Martin | 43994d8 | 2017-10-31 15:51:19 +0000 | [diff] [blame] | 33 | #define ARM64_SVE 22 |
Will Deacon | ea1e3de | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 34 | #define ARM64_UNMAP_KERNEL_AT_EL0 23 |
Will Deacon | 688f1e4 | 2020-09-15 23:00:31 +0100 | [diff] [blame] | 35 | #define ARM64_SPECTRE_V2 24 |
Shanker Donthineni | 4bc352f | 2018-04-10 11:36:42 +0100 | [diff] [blame] | 36 | #define ARM64_HAS_RAS_EXTN 25 |
| 37 | #define ARM64_WORKAROUND_843419 26 |
| 38 | #define ARM64_HAS_CACHE_IDC 27 |
| 39 | #define ARM64_HAS_CACHE_DIC 28 |
| 40 | #define ARM64_HW_DBM 29 |
Will Deacon | 9b0955b | 2020-09-15 23:00:31 +0100 | [diff] [blame] | 41 | #define ARM64_SPECTRE_V4 30 |
Suzuki K Poulose | 314d53d | 2018-07-04 23:07:46 +0100 | [diff] [blame] | 42 | #define ARM64_MISMATCHED_CACHE_TYPE 31 |
Paolo Bonzini | 6319893 | 2018-08-22 14:07:56 +0200 | [diff] [blame] | 43 | #define ARM64_HAS_STAGE2_FWB 32 |
Ard Biesheuvel | 86d0dd3 | 2018-08-27 13:02:43 +0200 | [diff] [blame] | 44 | #define ARM64_HAS_CRC32 33 |
Will Deacon | d71be2b | 2018-06-15 11:37:34 +0100 | [diff] [blame] | 45 | #define ARM64_SSBS 34 |
Marc Zyngier | a532508 | 2019-05-23 11:24:50 +0100 | [diff] [blame] | 46 | #define ARM64_WORKAROUND_1418040 35 |
Will Deacon | bd4fb6d | 2018-06-14 11:21:34 +0100 | [diff] [blame] | 47 | #define ARM64_HAS_SB 36 |
Will Deacon | c350717 | 2020-05-28 18:02:51 +0100 | [diff] [blame] | 48 | #define ARM64_WORKAROUND_SPECULATIVE_AT 37 |
Mark Rutland | 6984eb4 | 2018-12-07 18:39:24 +0000 | [diff] [blame] | 49 | #define ARM64_HAS_ADDRESS_AUTH_ARCH 38 |
| 50 | #define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39 |
Will Deacon | a56005d | 2018-12-12 15:52:02 +0000 | [diff] [blame] | 51 | #define ARM64_HAS_GENERIC_AUTH_ARCH 40 |
| 52 | #define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41 |
Julien Thierry | b90d2b2 | 2019-01-31 14:58:42 +0000 | [diff] [blame] | 53 | #define ARM64_HAS_IRQ_PRIO_MASKING 42 |
Andrew Murray | b9585f5 | 2019-04-09 10:52:45 +0100 | [diff] [blame] | 54 | #define ARM64_HAS_DCPODP 43 |
Will Deacon | 969f5ea | 2019-04-29 13:03:57 +0100 | [diff] [blame] | 55 | #define ARM64_WORKAROUND_1463225 44 |
Marc Zyngier | d3ec3a0 | 2019-02-07 16:01:21 +0000 | [diff] [blame] | 56 | #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45 |
Marc Zyngier | 9405447 | 2019-04-09 16:22:24 +0100 | [diff] [blame] | 57 | #define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46 |
Catalin Marinas | 6a036af | 2019-10-28 16:12:40 +0000 | [diff] [blame] | 58 | #define ARM64_WORKAROUND_1542419 47 |
Andrew Scull | 02ab1f5 | 2020-05-04 10:48:58 +0100 | [diff] [blame] | 59 | #define ARM64_HAS_E0PD 48 |
| 60 | #define ARM64_HAS_RNG 49 |
| 61 | #define ARM64_HAS_AMU_EXTN 50 |
| 62 | #define ARM64_HAS_ADDRESS_AUTH 51 |
| 63 | #define ARM64_HAS_GENERIC_AUTH 52 |
Will Deacon | c350717 | 2020-05-28 18:02:51 +0100 | [diff] [blame] | 64 | #define ARM64_HAS_32BIT_EL1 53 |
| 65 | #define ARM64_BTI 54 |
Marc Zyngier | 552ae76 | 2018-12-22 12:00:10 +0000 | [diff] [blame] | 66 | #define ARM64_HAS_ARMv8_4_TTL 55 |
Zhenyu Ye | b620ba5 | 2020-07-15 15:19:43 +0800 | [diff] [blame] | 67 | #define ARM64_HAS_TLB_RANGE 56 |
Vincenzo Frascino | 3b714d2 | 2019-09-06 10:58:01 +0100 | [diff] [blame] | 68 | #define ARM64_MTE 57 |
Rob Herring | 96d389ca | 2020-10-28 13:28:39 -0500 | [diff] [blame] | 69 | #define ARM64_WORKAROUND_1508412 58 |
Will Deacon | 975ebc7 | 2020-06-30 14:02:22 +0100 | [diff] [blame] | 70 | #define ARM64_HAS_LDAPR 59 |
| 71 | #define ARM64_KVM_PROTECTED_MODE 60 |
Suzuki K Poulose | a512242 | 2021-10-19 17:31:41 +0100 | [diff] [blame] | 72 | #define ARM64_WORKAROUND_TSB_FLUSH_FAILURE 61 |
Catalin Marinas | 272d01b | 2016-11-03 18:34:34 +0000 | [diff] [blame] | 73 | |
Mukesh Ojha | a6b8e73 | 2021-04-01 17:55:19 +0530 | [diff] [blame] | 74 | /* kabi: reserve 62 - 76 for future cpu capabilities */ |
| 75 | #define ARM64_NCAPS 76 |
Catalin Marinas | 272d01b | 2016-11-03 18:34:34 +0000 | [diff] [blame] | 76 | |
| 77 | #endif /* __ASM_CPUCAPS_H */ |