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Thomas Gleixnercaab2772019-06-03 07:44:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Catalin Marinas272d01b2016-11-03 18:34:34 +00002/*
3 * arch/arm64/include/asm/cpucaps.h
4 *
5 * Copyright (C) 2016 ARM Ltd.
Catalin Marinas272d01b2016-11-03 18:34:34 +00006 */
7#ifndef __ASM_CPUCAPS_H
8#define __ASM_CPUCAPS_H
9
10#define ARM64_WORKAROUND_CLEAN_CACHE 0
11#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
12#define ARM64_WORKAROUND_845719 2
13#define ARM64_HAS_SYSREG_GIC_CPUIF 3
14#define ARM64_HAS_PAN 4
15#define ARM64_HAS_LSE_ATOMICS 5
16#define ARM64_WORKAROUND_CAVIUM_23154 6
17#define ARM64_WORKAROUND_834220 7
18#define ARM64_HAS_NO_HW_PREFETCH 8
19#define ARM64_HAS_UAO 9
20#define ARM64_ALT_PAN_NOT_UAO 10
21#define ARM64_HAS_VIRT_HOST_EXTN 11
22#define ARM64_WORKAROUND_CAVIUM_27456 12
Will Deacon4fb15642020-10-27 20:58:29 +000023/* Unreliable: use system_supports_32bit_el0() instead. */
24#define ARM64_HAS_32BIT_EL0_DO_NOT_USE 13
Will Deacon1be38822020-11-13 11:38:45 +000025#define ARM64_SPECTRE_V3A 14
Will Deacon880f7cc2018-09-19 11:41:21 +010026#define ARM64_HAS_CNP 15
Linus Torvaldsf4000cd92016-12-13 16:39:21 -080027#define ARM64_HAS_NO_FPSIMD 16
Christopher Covingtond9ff80f2017-01-31 12:50:19 -050028#define ARM64_WORKAROUND_REPEAT_TLBI 17
Christopher Covington38fd94b2017-02-08 15:08:37 -050029#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18
Marc Zyngiereeb1efb2017-03-20 17:18:06 +000030#define ARM64_WORKAROUND_858921 19
David Daney690a3412017-06-09 12:49:48 +010031#define ARM64_WORKAROUND_CAVIUM_30115 20
Robin Murphyd50e0712017-07-25 11:55:42 +010032#define ARM64_HAS_DCPOP 21
Dave Martin43994d82017-10-31 15:51:19 +000033#define ARM64_SVE 22
Will Deaconea1e3de2017-11-14 14:38:19 +000034#define ARM64_UNMAP_KERNEL_AT_EL0 23
Will Deacon688f1e42020-09-15 23:00:31 +010035#define ARM64_SPECTRE_V2 24
Shanker Donthineni4bc352f2018-04-10 11:36:42 +010036#define ARM64_HAS_RAS_EXTN 25
37#define ARM64_WORKAROUND_843419 26
38#define ARM64_HAS_CACHE_IDC 27
39#define ARM64_HAS_CACHE_DIC 28
40#define ARM64_HW_DBM 29
Will Deacon9b0955b2020-09-15 23:00:31 +010041#define ARM64_SPECTRE_V4 30
Suzuki K Poulose314d53d2018-07-04 23:07:46 +010042#define ARM64_MISMATCHED_CACHE_TYPE 31
Paolo Bonzini63198932018-08-22 14:07:56 +020043#define ARM64_HAS_STAGE2_FWB 32
Ard Biesheuvel86d0dd32018-08-27 13:02:43 +020044#define ARM64_HAS_CRC32 33
Will Deacond71be2b2018-06-15 11:37:34 +010045#define ARM64_SSBS 34
Marc Zyngiera5325082019-05-23 11:24:50 +010046#define ARM64_WORKAROUND_1418040 35
Will Deaconbd4fb6d2018-06-14 11:21:34 +010047#define ARM64_HAS_SB 36
Will Deaconc3507172020-05-28 18:02:51 +010048#define ARM64_WORKAROUND_SPECULATIVE_AT 37
Mark Rutland6984eb42018-12-07 18:39:24 +000049#define ARM64_HAS_ADDRESS_AUTH_ARCH 38
50#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39
Will Deacona56005d2018-12-12 15:52:02 +000051#define ARM64_HAS_GENERIC_AUTH_ARCH 40
52#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41
Julien Thierryb90d2b22019-01-31 14:58:42 +000053#define ARM64_HAS_IRQ_PRIO_MASKING 42
Andrew Murrayb9585f52019-04-09 10:52:45 +010054#define ARM64_HAS_DCPODP 43
Will Deacon969f5ea2019-04-29 13:03:57 +010055#define ARM64_WORKAROUND_1463225 44
Marc Zyngierd3ec3a02019-02-07 16:01:21 +000056#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45
Marc Zyngier94054472019-04-09 16:22:24 +010057#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
Catalin Marinas6a036af2019-10-28 16:12:40 +000058#define ARM64_WORKAROUND_1542419 47
Andrew Scull02ab1f52020-05-04 10:48:58 +010059#define ARM64_HAS_E0PD 48
60#define ARM64_HAS_RNG 49
61#define ARM64_HAS_AMU_EXTN 50
62#define ARM64_HAS_ADDRESS_AUTH 51
63#define ARM64_HAS_GENERIC_AUTH 52
Will Deaconc3507172020-05-28 18:02:51 +010064#define ARM64_HAS_32BIT_EL1 53
65#define ARM64_BTI 54
Marc Zyngier552ae762018-12-22 12:00:10 +000066#define ARM64_HAS_ARMv8_4_TTL 55
Zhenyu Yeb620ba52020-07-15 15:19:43 +080067#define ARM64_HAS_TLB_RANGE 56
Vincenzo Frascino3b714d22019-09-06 10:58:01 +010068#define ARM64_MTE 57
Rob Herring96d389ca2020-10-28 13:28:39 -050069#define ARM64_WORKAROUND_1508412 58
Will Deacon975ebc72020-06-30 14:02:22 +010070#define ARM64_HAS_LDAPR 59
71#define ARM64_KVM_PROTECTED_MODE 60
Suzuki K Poulosea5122422021-10-19 17:31:41 +010072#define ARM64_WORKAROUND_TSB_FLUSH_FAILURE 61
Catalin Marinas272d01b2016-11-03 18:34:34 +000073
Mukesh Ojhaa6b8e732021-04-01 17:55:19 +053074/* kabi: reserve 62 - 76 for future cpu capabilities */
75#define ARM64_NCAPS 76
Catalin Marinas272d01b2016-11-03 18:34:34 +000076
77#endif /* __ASM_CPUCAPS_H */