blob: a35c1412e43b90528081e3eecfde86835ddbe973 [file] [log] [blame]
Jani Nikula4e646492013-08-27 15:12:20 +03001/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <drm/drmP.h>
Matt Roperc6f95f22015-01-22 16:50:32 -080027#include <drm/drm_atomic_helper.h>
Jani Nikula4e646492013-08-27 15:12:20 +030028#include <drm/drm_crtc.h>
29#include <drm/drm_edid.h>
30#include <drm/i915_drm.h>
Jani Nikula593e0622015-01-23 15:30:56 +020031#include <drm/drm_panel.h>
Jani Nikula7e9804f2015-01-16 14:27:23 +020032#include <drm/drm_mipi_dsi.h>
Jani Nikula4e646492013-08-27 15:12:20 +030033#include <linux/slab.h>
Shobhit Kumarfc45e822015-06-26 14:32:09 +053034#include <linux/gpio/consumer.h>
Jani Nikula4e646492013-08-27 15:12:20 +030035#include "i915_drv.h"
36#include "intel_drv.h"
37#include "intel_dsi.h"
Jani Nikula4e646492013-08-27 15:12:20 +030038
Jani Nikula593e0622015-01-23 15:30:56 +020039static const struct {
40 u16 panel_id;
41 struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
42} intel_dsi_drivers[] = {
Shobhit Kumar2ab8b452014-05-23 21:35:27 +053043 {
44 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
Jani Nikula593e0622015-01-23 15:30:56 +020045 .init = vbt_panel_init,
Shobhit Kumar2ab8b452014-05-23 21:35:27 +053046 },
Jani Nikula4e646492013-08-27 15:12:20 +030047};
48
Ramalingam C042ab0c2016-04-19 13:48:14 +053049/* return pixels in terms of txbyteclkhs */
50static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
51 u16 burst_mode_ratio)
52{
53 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
54 8 * 100), lane_count);
55}
56
Ramalingam Ccefc4e12016-04-19 13:48:13 +053057/* return pixels equvalent to txbyteclkhs */
58static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
59 u16 burst_mode_ratio)
60{
61 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
62 (bpp * burst_mode_ratio));
63}
64
Ramalingam C43367ec2016-04-07 14:36:06 +053065enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
66{
67 /* It just so happens the VBT matches register contents. */
68 switch (fmt) {
69 case VID_MODE_FORMAT_RGB888:
70 return MIPI_DSI_FMT_RGB888;
71 case VID_MODE_FORMAT_RGB666:
72 return MIPI_DSI_FMT_RGB666;
73 case VID_MODE_FORMAT_RGB666_PACKED:
74 return MIPI_DSI_FMT_RGB666_PACKED;
75 case VID_MODE_FORMAT_RGB565:
76 return MIPI_DSI_FMT_RGB565;
77 default:
78 MISSING_CASE(fmt);
79 return MIPI_DSI_FMT_RGB666;
80 }
81}
82
Jani Nikula7f6a6a42015-01-16 14:27:19 +020083static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
Jani Nikula3b1808b2015-01-16 14:27:18 +020084{
85 struct drm_encoder *encoder = &intel_dsi->base.base;
86 struct drm_device *dev = encoder->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +010087 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikula3b1808b2015-01-16 14:27:18 +020088 u32 mask;
89
90 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
91 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
92
Chris Wilson9b6a2d72016-06-30 15:33:13 +010093 if (intel_wait_for_register(dev_priv,
94 MIPI_GEN_FIFO_STAT(port), mask, mask,
95 100))
Jani Nikula3b1808b2015-01-16 14:27:18 +020096 DRM_ERROR("DPI FIFOs are not empty\n");
97}
98
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020099static void write_data(struct drm_i915_private *dev_priv,
100 i915_reg_t reg,
Jani Nikula7e9804f2015-01-16 14:27:23 +0200101 const u8 *data, u32 len)
102{
103 u32 i, j;
104
105 for (i = 0; i < len; i += 4) {
106 u32 val = 0;
107
108 for (j = 0; j < min_t(u32, len - i, 4); j++)
109 val |= *data++ << 8 * j;
110
111 I915_WRITE(reg, val);
112 }
113}
114
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200115static void read_data(struct drm_i915_private *dev_priv,
116 i915_reg_t reg,
Jani Nikula7e9804f2015-01-16 14:27:23 +0200117 u8 *data, u32 len)
118{
119 u32 i, j;
120
121 for (i = 0; i < len; i += 4) {
122 u32 val = I915_READ(reg);
123
124 for (j = 0; j < min_t(u32, len - i, 4); j++)
125 *data++ = val >> 8 * j;
126 }
127}
128
129static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
130 const struct mipi_dsi_msg *msg)
131{
132 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
133 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100134 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikula7e9804f2015-01-16 14:27:23 +0200135 enum port port = intel_dsi_host->port;
136 struct mipi_dsi_packet packet;
137 ssize_t ret;
138 const u8 *header, *data;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200139 i915_reg_t data_reg, ctrl_reg;
140 u32 data_mask, ctrl_mask;
Jani Nikula7e9804f2015-01-16 14:27:23 +0200141
142 ret = mipi_dsi_create_packet(&packet, msg);
143 if (ret < 0)
144 return ret;
145
146 header = packet.header;
147 data = packet.payload;
148
149 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
150 data_reg = MIPI_LP_GEN_DATA(port);
151 data_mask = LP_DATA_FIFO_FULL;
152 ctrl_reg = MIPI_LP_GEN_CTRL(port);
153 ctrl_mask = LP_CTRL_FIFO_FULL;
154 } else {
155 data_reg = MIPI_HS_GEN_DATA(port);
156 data_mask = HS_DATA_FIFO_FULL;
157 ctrl_reg = MIPI_HS_GEN_CTRL(port);
158 ctrl_mask = HS_CTRL_FIFO_FULL;
159 }
160
161 /* note: this is never true for reads */
162 if (packet.payload_length) {
Chris Wilson8c6cea02016-06-30 15:33:14 +0100163 if (intel_wait_for_register(dev_priv,
164 MIPI_GEN_FIFO_STAT(port),
165 data_mask, 0,
166 50))
Jani Nikula7e9804f2015-01-16 14:27:23 +0200167 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
168
169 write_data(dev_priv, data_reg, packet.payload,
170 packet.payload_length);
171 }
172
173 if (msg->rx_len) {
174 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
175 }
176
Chris Wilson84c2aa92016-06-30 15:33:15 +0100177 if (intel_wait_for_register(dev_priv,
178 MIPI_GEN_FIFO_STAT(port),
179 ctrl_mask, 0,
180 50)) {
Jani Nikula7e9804f2015-01-16 14:27:23 +0200181 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
182 }
183
184 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
185
186 /* ->rx_len is set only for reads */
187 if (msg->rx_len) {
188 data_mask = GEN_READ_DATA_AVAIL;
Chris Wilsone7615b32016-06-30 15:33:16 +0100189 if (intel_wait_for_register(dev_priv,
190 MIPI_INTR_STAT(port),
191 data_mask, data_mask,
192 50))
Jani Nikula7e9804f2015-01-16 14:27:23 +0200193 DRM_ERROR("Timeout waiting for read data.\n");
194
195 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
196 }
197
198 /* XXX: fix for reads and writes */
199 return 4 + packet.payload_length;
200}
201
202static int intel_dsi_host_attach(struct mipi_dsi_host *host,
203 struct mipi_dsi_device *dsi)
204{
205 return 0;
206}
207
208static int intel_dsi_host_detach(struct mipi_dsi_host *host,
209 struct mipi_dsi_device *dsi)
210{
211 return 0;
212}
213
214static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
215 .attach = intel_dsi_host_attach,
216 .detach = intel_dsi_host_detach,
217 .transfer = intel_dsi_host_transfer,
218};
219
220static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
221 enum port port)
222{
223 struct intel_dsi_host *host;
224 struct mipi_dsi_device *device;
225
226 host = kzalloc(sizeof(*host), GFP_KERNEL);
227 if (!host)
228 return NULL;
229
230 host->base.ops = &intel_dsi_host_ops;
231 host->intel_dsi = intel_dsi;
232 host->port = port;
233
234 /*
235 * We should call mipi_dsi_host_register(&host->base) here, but we don't
236 * have a host->dev, and we don't have OF stuff either. So just use the
237 * dsi framework as a library and hope for the best. Create the dsi
238 * devices by ourselves here too. Need to be careful though, because we
239 * don't initialize any of the driver model devices here.
240 */
241 device = kzalloc(sizeof(*device), GFP_KERNEL);
242 if (!device) {
243 kfree(host);
244 return NULL;
245 }
246
247 device->host = &host->base;
248 host->device = device;
249
250 return host;
251}
252
Jani Nikulaa2581a92015-01-16 14:27:26 +0200253/*
254 * send a video mode command
255 *
256 * XXX: commands with data in MIPI_DPI_DATA?
257 */
258static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
259 enum port port)
260{
261 struct drm_encoder *encoder = &intel_dsi->base.base;
262 struct drm_device *dev = encoder->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100263 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikulaa2581a92015-01-16 14:27:26 +0200264 u32 mask;
265
266 /* XXX: pipe, hs */
267 if (hs)
268 cmd &= ~DPI_LP_MODE;
269 else
270 cmd |= DPI_LP_MODE;
271
272 /* clear bit */
273 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
274
275 /* XXX: old code skips write if control unchanged */
276 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
277 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
278
279 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
280
281 mask = SPL_PKT_SENT_INTERRUPT;
Chris Wilson2af05072016-06-30 15:33:17 +0100282 if (intel_wait_for_register(dev_priv,
283 MIPI_INTR_STAT(port), mask, mask,
284 100))
Jani Nikulaa2581a92015-01-16 14:27:26 +0200285 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
286
287 return 0;
288}
289
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530290static void band_gap_reset(struct drm_i915_private *dev_priv)
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +0300291{
Ville Syrjäläa5805162015-05-26 20:42:30 +0300292 mutex_lock(&dev_priv->sb_lock);
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +0300293
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530294 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
295 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
296 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
297 udelay(150);
298 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
299 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +0300300
Ville Syrjäläa5805162015-05-26 20:42:30 +0300301 mutex_unlock(&dev_priv->sb_lock);
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +0300302}
303
Jani Nikula4e646492013-08-27 15:12:20 +0300304static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
305{
Shobhit Kumardfba2e22014-04-14 11:18:24 +0530306 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
Jani Nikula4e646492013-08-27 15:12:20 +0300307}
308
309static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
310{
Shobhit Kumardfba2e22014-04-14 11:18:24 +0530311 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
Jani Nikula4e646492013-08-27 15:12:20 +0300312}
313
Jani Nikula4e646492013-08-27 15:12:20 +0300314static bool intel_dsi_compute_config(struct intel_encoder *encoder,
Maarten Lankhorst0a478c22016-08-09 17:04:05 +0200315 struct intel_crtc_state *pipe_config,
316 struct drm_connector_state *conn_state)
Jani Nikula4e646492013-08-27 15:12:20 +0300317{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100318 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Jani Nikula4e646492013-08-27 15:12:20 +0300319 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
320 base);
321 struct intel_connector *intel_connector = intel_dsi->attached_connector;
Ville Syrjäläf4ee2652016-04-12 22:14:37 +0300322 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
323 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
Jani Nikulaa65347b2015-11-27 12:21:46 +0200324 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Ville Syrjälä47eacba2016-04-12 22:14:35 +0300325 int ret;
Jani Nikula4e646492013-08-27 15:12:20 +0300326
327 DRM_DEBUG_KMS("\n");
328
Ville Syrjäläf4ee2652016-04-12 22:14:37 +0300329 if (fixed_mode) {
Jani Nikula4e646492013-08-27 15:12:20 +0300330 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
331
Ville Syrjäläf4ee2652016-04-12 22:14:37 +0300332 if (HAS_GMCH_DISPLAY(dev_priv))
333 intel_gmch_panel_fitting(crtc, pipe_config,
334 intel_connector->panel.fitting_mode);
335 else
336 intel_pch_panel_fitting(crtc, pipe_config,
337 intel_connector->panel.fitting_mode);
338 }
339
Shobhit Kumarf573de52014-07-30 20:32:37 +0530340 /* DSI uses short packets for sync events, so clear mode flags for DSI */
341 adjusted_mode->flags = 0;
342
Jani Nikula4d1de972016-03-18 17:05:42 +0200343 if (IS_BROXTON(dev_priv)) {
344 /* Dual link goes to DSI transcoder A. */
345 if (intel_dsi->ports == BIT(PORT_C))
346 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
347 else
348 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
349 }
350
Ville Syrjälä47eacba2016-04-12 22:14:35 +0300351 ret = intel_compute_dsi_pll(encoder, pipe_config);
352 if (ret)
353 return false;
354
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +0300355 pipe_config->clock_set = true;
356
Jani Nikula4e646492013-08-27 15:12:20 +0300357 return true;
358}
359
Shashank Sharma37ab0812015-09-01 19:41:42 +0530360static void bxt_dsi_device_ready(struct intel_encoder *encoder)
Gaurav K Singh5505a242014-12-04 10:58:47 +0530361{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100362 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Gaurav K Singh5505a242014-12-04 10:58:47 +0530363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
Gaurav K Singh369602d2014-12-05 14:09:28 +0530364 enum port port;
Shashank Sharma37ab0812015-09-01 19:41:42 +0530365 u32 val;
Gaurav K Singh5505a242014-12-04 10:58:47 +0530366
Shashank Sharma37ab0812015-09-01 19:41:42 +0530367 DRM_DEBUG_KMS("\n");
Gaurav K Singha9da9bc2014-12-05 14:13:41 +0530368
Shashank Sharma37ab0812015-09-01 19:41:42 +0530369 /* Exit Low power state in 4 steps*/
Gaurav K Singh369602d2014-12-05 14:09:28 +0530370 for_each_dsi_port(port, intel_dsi->ports) {
Gaurav K Singh369602d2014-12-05 14:09:28 +0530371
Shashank Sharma37ab0812015-09-01 19:41:42 +0530372 /* 1. Enable MIPI PHY transparent latch */
373 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
374 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
375 usleep_range(2000, 2500);
376
377 /* 2. Enter ULPS */
378 val = I915_READ(MIPI_DEVICE_READY(port));
379 val &= ~ULPS_STATE_MASK;
380 val |= (ULPS_STATE_ENTER | DEVICE_READY);
381 I915_WRITE(MIPI_DEVICE_READY(port), val);
382 usleep_range(2, 3);
383
384 /* 3. Exit ULPS */
385 val = I915_READ(MIPI_DEVICE_READY(port));
386 val &= ~ULPS_STATE_MASK;
387 val |= (ULPS_STATE_EXIT | DEVICE_READY);
388 I915_WRITE(MIPI_DEVICE_READY(port), val);
389 usleep_range(1000, 1500);
390
391 /* Clear ULPS and set device ready */
392 val = I915_READ(MIPI_DEVICE_READY(port));
393 val &= ~ULPS_STATE_MASK;
394 val |= DEVICE_READY;
395 I915_WRITE(MIPI_DEVICE_READY(port), val);
Gaurav K Singh369602d2014-12-05 14:09:28 +0530396 }
Gaurav K Singh5505a242014-12-04 10:58:47 +0530397}
398
Shashank Sharma37ab0812015-09-01 19:41:42 +0530399static void vlv_dsi_device_ready(struct intel_encoder *encoder)
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530400{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100401 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Gaurav K Singh24ee0e62014-12-05 14:24:21 +0530402 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
403 enum port port;
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530404 u32 val;
405
406 DRM_DEBUG_KMS("\n");
407
Ville Syrjäläa5805162015-05-26 20:42:30 +0300408 mutex_lock(&dev_priv->sb_lock);
Shobhit Kumar2095f9f2014-04-09 13:59:30 +0530409 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
410 * needed everytime after power gate */
411 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
Ville Syrjäläa5805162015-05-26 20:42:30 +0300412 mutex_unlock(&dev_priv->sb_lock);
Shobhit Kumar2095f9f2014-04-09 13:59:30 +0530413
414 /* bandgap reset is needed after everytime we do power gate */
415 band_gap_reset(dev_priv);
416
Gaurav K Singh24ee0e62014-12-05 14:24:21 +0530417 for_each_dsi_port(port, intel_dsi->ports) {
Shobhit Kumaraceb3652014-07-03 16:35:41 +0530418
Gaurav K Singh24ee0e62014-12-05 14:24:21 +0530419 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
420 usleep_range(2500, 3000);
Shobhit Kumaraceb3652014-07-03 16:35:41 +0530421
Gaurav K Singhbf344e82014-12-07 16:13:54 +0530422 /* Enable MIPI PHY transparent latch
423 * Common bit for both MIPI Port A & MIPI Port C
424 * No similar bit in MIPI Port C reg
425 */
Shobhit Kumar4ba7d932015-02-05 17:08:45 +0530426 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
Gaurav K Singhbf344e82014-12-07 16:13:54 +0530427 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
Gaurav K Singh24ee0e62014-12-05 14:24:21 +0530428 usleep_range(1000, 1500);
Shobhit Kumaraceb3652014-07-03 16:35:41 +0530429
Gaurav K Singh24ee0e62014-12-05 14:24:21 +0530430 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
431 usleep_range(2500, 3000);
432
433 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
434 usleep_range(2500, 3000);
435 }
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530436}
Jani Nikula4e646492013-08-27 15:12:20 +0300437
Shashank Sharma37ab0812015-09-01 19:41:42 +0530438static void intel_dsi_device_ready(struct intel_encoder *encoder)
439{
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100440 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Shashank Sharma37ab0812015-09-01 19:41:42 +0530441
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100442 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Shashank Sharma37ab0812015-09-01 19:41:42 +0530443 vlv_dsi_device_ready(encoder);
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100444 else if (IS_BROXTON(dev_priv))
Shashank Sharma37ab0812015-09-01 19:41:42 +0530445 bxt_dsi_device_ready(encoder);
446}
447
448static void intel_dsi_port_enable(struct intel_encoder *encoder)
449{
450 struct drm_device *dev = encoder->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100451 struct drm_i915_private *dev_priv = to_i915(dev);
Shashank Sharma37ab0812015-09-01 19:41:42 +0530452 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
453 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
454 enum port port;
Shashank Sharma37ab0812015-09-01 19:41:42 +0530455
456 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200457 u32 temp;
458
Shashank Sharma37ab0812015-09-01 19:41:42 +0530459 temp = I915_READ(VLV_CHICKEN_3);
460 temp &= ~PIXEL_OVERLAP_CNT_MASK |
461 intel_dsi->pixel_overlap <<
462 PIXEL_OVERLAP_CNT_SHIFT;
463 I915_WRITE(VLV_CHICKEN_3, temp);
464 }
465
466 for_each_dsi_port(port, intel_dsi->ports) {
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100467 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200468 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
469 u32 temp;
Shashank Sharma37ab0812015-09-01 19:41:42 +0530470
471 temp = I915_READ(port_ctrl);
472
473 temp &= ~LANE_CONFIGURATION_MASK;
474 temp &= ~DUAL_LINK_MODE_MASK;
475
Jani Nikula701d25b2016-03-18 17:05:43 +0200476 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
Shashank Sharma37ab0812015-09-01 19:41:42 +0530477 temp |= (intel_dsi->dual_link - 1)
478 << DUAL_LINK_MODE_SHIFT;
Bob Paauwe812b1d22016-11-21 14:24:06 -0800479 if (IS_BROXTON(dev_priv))
480 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
481 else
482 temp |= intel_crtc->pipe ?
Shashank Sharma37ab0812015-09-01 19:41:42 +0530483 LANE_CONFIGURATION_DUAL_LINK_B :
484 LANE_CONFIGURATION_DUAL_LINK_A;
485 }
486 /* assert ip_tg_enable signal */
487 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
488 POSTING_READ(port_ctrl);
489 }
490}
491
492static void intel_dsi_port_disable(struct intel_encoder *encoder)
493{
494 struct drm_device *dev = encoder->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100495 struct drm_i915_private *dev_priv = to_i915(dev);
Shashank Sharma37ab0812015-09-01 19:41:42 +0530496 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
497 enum port port;
Shashank Sharma37ab0812015-09-01 19:41:42 +0530498
499 for_each_dsi_port(port, intel_dsi->ports) {
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100500 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200501 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
502 u32 temp;
503
Shashank Sharma37ab0812015-09-01 19:41:42 +0530504 /* de-assert ip_tg_enable signal */
Shashank Sharmab389a452015-09-01 19:41:44 +0530505 temp = I915_READ(port_ctrl);
506 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
507 POSTING_READ(port_ctrl);
Shashank Sharma37ab0812015-09-01 19:41:42 +0530508 }
509}
510
Jani Nikula4e646492013-08-27 15:12:20 +0300511static void intel_dsi_enable(struct intel_encoder *encoder)
512{
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530513 struct drm_device *dev = encoder->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100514 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikula4e646492013-08-27 15:12:20 +0300515 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
Jani Nikula4934b652015-01-22 15:01:35 +0200516 enum port port;
Jani Nikula4e646492013-08-27 15:12:20 +0300517
518 DRM_DEBUG_KMS("\n");
519
Jani Nikula4934b652015-01-22 15:01:35 +0200520 if (is_cmd_mode(intel_dsi)) {
521 for_each_dsi_port(port, intel_dsi->ports)
522 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
523 } else {
Jani Nikula4e646492013-08-27 15:12:20 +0300524 msleep(20); /* XXX */
Jani Nikulaf03e4172015-01-16 14:27:16 +0200525 for_each_dsi_port(port, intel_dsi->ports)
Jani Nikulaa2581a92015-01-16 14:27:26 +0200526 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
Jani Nikula4e646492013-08-27 15:12:20 +0300527 msleep(100);
528
Jani Nikula593e0622015-01-23 15:30:56 +0200529 drm_panel_enable(intel_dsi->panel);
Shobhit Kumar2634fd72014-04-09 13:59:31 +0530530
Jani Nikula7f6a6a42015-01-16 14:27:19 +0200531 for_each_dsi_port(port, intel_dsi->ports)
532 wait_for_dsi_fifo_empty(intel_dsi, port);
Shobhit Kumar13813082014-07-12 17:17:22 +0530533
Gaurav K Singh5505a242014-12-04 10:58:47 +0530534 intel_dsi_port_enable(encoder);
Jani Nikula4e646492013-08-27 15:12:20 +0300535 }
Shobhit Kumarb029e662015-06-26 14:32:10 +0530536
537 intel_panel_enable_backlight(intel_dsi->attached_connector);
Shobhit Kumar2634fd72014-04-09 13:59:31 +0530538}
Jani Nikula4e646492013-08-27 15:12:20 +0300539
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +0200540static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
541 struct intel_crtc_state *pipe_config);
Jani Nikulae3488e72015-11-27 12:21:44 +0200542
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +0200543static void intel_dsi_pre_enable(struct intel_encoder *encoder,
544 struct intel_crtc_state *pipe_config,
545 struct drm_connector_state *conn_state)
Shobhit Kumar2634fd72014-04-09 13:59:31 +0530546{
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +0200547 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Shobhit Kumar2634fd72014-04-09 13:59:31 +0530548 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
Jani Nikula7f6a6a42015-01-16 14:27:19 +0200549 enum port port;
Shobhit Kumar2634fd72014-04-09 13:59:31 +0530550
551 DRM_DEBUG_KMS("\n");
552
Ville Syrjäläf00b5682016-03-15 16:40:03 +0200553 /*
554 * The BIOS may leave the PLL in a wonky state where it doesn't
555 * lock. It needs to be fully powered down to fix it.
556 */
557 intel_disable_dsi_pll(encoder);
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +0200558 intel_enable_dsi_pll(encoder, pipe_config);
Ville Syrjäläf00b5682016-03-15 16:40:03 +0200559
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +0200560 intel_dsi_prepare(encoder, pipe_config);
Jani Nikulae3488e72015-11-27 12:21:44 +0200561
Shobhit Kumarfc45e822015-06-26 14:32:09 +0530562 /* Panel Enable over CRC PMIC */
563 if (intel_dsi->gpio_panel)
564 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
565
566 msleep(intel_dsi->panel_on_delay);
567
Ville Syrjäläd1877c02016-04-18 19:18:25 +0300568 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
569 u32 val;
570
Ville Syrjäläcd2d34d2016-04-12 22:14:34 +0300571 /* Disable DPOunit clock gating, can stall pipe */
Ville Syrjäläd1877c02016-04-18 19:18:25 +0300572 val = I915_READ(DSPCLK_GATE_D);
573 val |= DPOUNIT_CLOCK_GATE_DISABLE;
574 I915_WRITE(DSPCLK_GATE_D, val);
Shashank Sharma37ab0812015-09-01 19:41:42 +0530575 }
Shobhit Kumar2634fd72014-04-09 13:59:31 +0530576
577 /* put device in ready state */
578 intel_dsi_device_ready(encoder);
579
Jani Nikula593e0622015-01-23 15:30:56 +0200580 drm_panel_prepare(intel_dsi->panel);
Shobhit Kumar20e5bf62014-04-09 13:59:32 +0530581
Jani Nikula7f6a6a42015-01-16 14:27:19 +0200582 for_each_dsi_port(port, intel_dsi->ports)
583 wait_for_dsi_fifo_empty(intel_dsi, port);
Shobhit Kumar13813082014-07-12 17:17:22 +0530584
Shobhit Kumar2634fd72014-04-09 13:59:31 +0530585 /* Enable port in pre-enable phase itself because as per hw team
586 * recommendation, port should be enabled befor plane & pipe */
587 intel_dsi_enable(encoder);
588}
589
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +0200590static void intel_dsi_enable_nop(struct intel_encoder *encoder,
591 struct intel_crtc_state *pipe_config,
592 struct drm_connector_state *conn_state)
Shobhit Kumar2634fd72014-04-09 13:59:31 +0530593{
594 DRM_DEBUG_KMS("\n");
595
596 /* for DSI port enable has to be done before pipe
597 * and plane enable, so port enable is done in
598 * pre_enable phase itself unlike other encoders
599 */
Jani Nikula4e646492013-08-27 15:12:20 +0300600}
601
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +0200602static void intel_dsi_pre_disable(struct intel_encoder *encoder,
603 struct intel_crtc_state *old_crtc_state,
604 struct drm_connector_state *old_conn_state)
Imre Deakc315faf2014-05-27 19:00:09 +0300605{
606 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
Jani Nikulaf03e4172015-01-16 14:27:16 +0200607 enum port port;
Imre Deakc315faf2014-05-27 19:00:09 +0300608
609 DRM_DEBUG_KMS("\n");
610
Shobhit Kumarb029e662015-06-26 14:32:10 +0530611 intel_panel_disable_backlight(intel_dsi->attached_connector);
612
Imre Deakc315faf2014-05-27 19:00:09 +0300613 if (is_vid_mode(intel_dsi)) {
614 /* Send Shutdown command to the panel in LP mode */
Jani Nikulaf03e4172015-01-16 14:27:16 +0200615 for_each_dsi_port(port, intel_dsi->ports)
Jani Nikulaa2581a92015-01-16 14:27:26 +0200616 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
Imre Deakc315faf2014-05-27 19:00:09 +0300617 msleep(10);
618 }
619}
620
Jani Nikula4e646492013-08-27 15:12:20 +0300621static void intel_dsi_disable(struct intel_encoder *encoder)
622{
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530623 struct drm_device *dev = encoder->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100624 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikula4e646492013-08-27 15:12:20 +0300625 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530626 enum port port;
Jani Nikula4e646492013-08-27 15:12:20 +0300627 u32 temp;
628
629 DRM_DEBUG_KMS("\n");
630
Jani Nikula4e646492013-08-27 15:12:20 +0300631 if (is_vid_mode(intel_dsi)) {
Jani Nikula7f6a6a42015-01-16 14:27:19 +0200632 for_each_dsi_port(port, intel_dsi->ports)
633 wait_for_dsi_fifo_empty(intel_dsi, port);
Shobhit Kumar13813082014-07-12 17:17:22 +0530634
Gaurav K Singh5505a242014-12-04 10:58:47 +0530635 intel_dsi_port_disable(encoder);
Jani Nikula4e646492013-08-27 15:12:20 +0300636 msleep(2);
637 }
638
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530639 for_each_dsi_port(port, intel_dsi->ports) {
640 /* Panel commands can be sent when clock is in LP11 */
641 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
Shobhit Kumar339023e2014-04-09 13:59:34 +0530642
Shashank Sharmab389a452015-09-01 19:41:44 +0530643 intel_dsi_reset_clocks(encoder, port);
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530644 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
Shobhit Kumar339023e2014-04-09 13:59:34 +0530645
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530646 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
647 temp &= ~VID_MODE_FORMAT_MASK;
648 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
Shobhit Kumar339023e2014-04-09 13:59:34 +0530649
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530650 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
651 }
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530652 /* if disable packets are sent before sending shutdown packet then in
653 * some next enable sequence send turn on packet error is observed */
Jani Nikula593e0622015-01-23 15:30:56 +0200654 drm_panel_disable(intel_dsi->panel);
Shobhit Kumar13813082014-07-12 17:17:22 +0530655
Jani Nikula7f6a6a42015-01-16 14:27:19 +0200656 for_each_dsi_port(port, intel_dsi->ports)
657 wait_for_dsi_fifo_empty(intel_dsi, port);
Jani Nikula4e646492013-08-27 15:12:20 +0300658}
659
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530660static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
Jani Nikula4e646492013-08-27 15:12:20 +0300661{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100662 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530663 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
664 enum port port;
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530665
Jani Nikula4e646492013-08-27 15:12:20 +0300666 DRM_DEBUG_KMS("\n");
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530667 for_each_dsi_port(port, intel_dsi->ports) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200668 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100669 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200670 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
671 u32 val;
ymohanmabe4fc042013-08-27 23:40:56 +0300672
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530673 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
674 ULPS_STATE_ENTER);
675 usleep_range(2000, 2500);
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530676
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530677 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
678 ULPS_STATE_EXIT);
679 usleep_range(2000, 2500);
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530680
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530681 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
682 ULPS_STATE_ENTER);
683 usleep_range(2000, 2500);
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530684
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530685 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
686 * only. MIPI Port C has no similar bit for checking
687 */
Chris Wilson0698cf62016-06-30 15:33:18 +0100688 if (intel_wait_for_register(dev_priv,
689 port_ctrl, AFE_LATCHOUT, 0,
690 30))
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530691 DRM_ERROR("DSI LP not going Low\n");
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530692
Shashank Sharmab389a452015-09-01 19:41:44 +0530693 /* Disable MIPI PHY transparent latch */
694 val = I915_READ(port_ctrl);
695 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530696 usleep_range(1000, 1500);
Shobhit Kumaraceb3652014-07-03 16:35:41 +0530697
Gaurav K Singh384f02a2014-12-05 14:22:44 +0530698 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
699 usleep_range(2000, 2500);
700 }
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530701
Shashank Sharmafe88fc62015-09-01 19:41:39 +0530702 intel_disable_dsi_pll(encoder);
Jani Nikula4e646492013-08-27 15:12:20 +0300703}
Shobhit Kumar20e5bf62014-04-09 13:59:32 +0530704
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +0200705static void intel_dsi_post_disable(struct intel_encoder *encoder,
706 struct intel_crtc_state *pipe_config,
707 struct drm_connector_state *conn_state)
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530708{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530710 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
711
712 DRM_DEBUG_KMS("\n");
713
Imre Deakc315faf2014-05-27 19:00:09 +0300714 intel_dsi_disable(encoder);
715
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530716 intel_dsi_clear_device_ready(encoder);
717
Ville Syrjäläd1877c02016-04-18 19:18:25 +0300718 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Uma Shankard6e3af52016-02-18 13:49:26 +0200719 u32 val;
720
721 val = I915_READ(DSPCLK_GATE_D);
722 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
723 I915_WRITE(DSPCLK_GATE_D, val);
724 }
Shobhit Kumar20e5bf62014-04-09 13:59:32 +0530725
Jani Nikula593e0622015-01-23 15:30:56 +0200726 drm_panel_unprepare(intel_dsi->panel);
Shobhit Kumardf38e652014-04-14 11:18:26 +0530727
728 msleep(intel_dsi->panel_off_delay);
Shobhit Kumarfc45e822015-06-26 14:32:09 +0530729
730 /* Panel Disable over CRC PMIC */
731 if (intel_dsi->gpio_panel)
732 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
Ville Syrjälä1d5c65e2016-04-18 19:17:51 +0300733
734 /*
735 * FIXME As we do with eDP, just make a note of the time here
736 * and perform the wait before the next panel power on.
737 */
738 msleep(intel_dsi->panel_pwr_cycle_delay);
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530739}
Jani Nikula4e646492013-08-27 15:12:20 +0300740
741static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
742 enum pipe *pipe)
743{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100744 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Gaurav K Singhc0beefd2014-12-09 10:59:20 +0530745 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
Imre Deak6d129be2014-03-05 16:20:54 +0200746 enum intel_display_power_domain power_domain;
Jani Nikulae7d7cad2014-11-14 16:54:21 +0200747 enum port port;
Jani Nikula1dcec2f2016-03-15 21:51:11 +0200748 bool active = false;
Jani Nikula4e646492013-08-27 15:12:20 +0300749
750 DRM_DEBUG_KMS("\n");
751
Imre Deak6d129be2014-03-05 16:20:54 +0200752 power_domain = intel_display_port_power_domain(encoder);
Imre Deak3f3f42b2016-02-12 18:55:19 +0200753 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
Imre Deak6d129be2014-03-05 16:20:54 +0200754 return false;
755
Imre Deakdb18b6a2016-03-24 12:41:40 +0200756 /*
757 * On Broxton the PLL needs to be enabled with a valid divider
758 * configuration, otherwise accessing DSI registers will hang the
759 * machine. See BSpec North Display Engine registers/MIPI[BXT].
760 */
761 if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
762 goto out_put_power;
763
Jani Nikula4e646492013-08-27 15:12:20 +0300764 /* XXX: this only works for one DSI output */
Gaurav K Singhc0beefd2014-12-09 10:59:20 +0530765 for_each_dsi_port(port, intel_dsi->ports) {
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100766 i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200767 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
Jani Nikula1dcec2f2016-03-15 21:51:11 +0200768 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
Jani Nikula4e646492013-08-27 15:12:20 +0300769
Jani Nikulae6f57782016-04-15 15:47:31 +0300770 /*
771 * Due to some hardware limitations on VLV/CHV, the DPI enable
772 * bit in port C control register does not get set. As a
773 * workaround, check pipe B conf instead.
Gaurav K Singhc0beefd2014-12-09 10:59:20 +0530774 */
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100775 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
776 port == PORT_C)
Jani Nikula1dcec2f2016-03-15 21:51:11 +0200777 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
Gaurav K Singhc0beefd2014-12-09 10:59:20 +0530778
Jani Nikula1dcec2f2016-03-15 21:51:11 +0200779 /* Try command mode if video mode not enabled */
780 if (!enabled) {
781 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
782 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
Jani Nikula4e646492013-08-27 15:12:20 +0300783 }
Jani Nikula1dcec2f2016-03-15 21:51:11 +0200784
785 if (!enabled)
786 continue;
787
788 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
789 continue;
790
Jani Nikula6b93e9c2016-03-15 21:51:12 +0200791 if (IS_BROXTON(dev_priv)) {
792 u32 tmp = I915_READ(MIPI_CTRL(port));
793 tmp &= BXT_PIPE_SELECT_MASK;
794 tmp >>= BXT_PIPE_SELECT_SHIFT;
795
796 if (WARN_ON(tmp > PIPE_C))
797 continue;
798
799 *pipe = tmp;
800 } else {
801 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
802 }
803
Jani Nikula1dcec2f2016-03-15 21:51:11 +0200804 active = true;
805 break;
Jani Nikula4e646492013-08-27 15:12:20 +0300806 }
Jani Nikula1dcec2f2016-03-15 21:51:11 +0200807
Imre Deakdb18b6a2016-03-24 12:41:40 +0200808out_put_power:
Imre Deak3f3f42b2016-02-12 18:55:19 +0200809 intel_display_power_put(dev_priv, power_domain);
Jani Nikula4e646492013-08-27 15:12:20 +0300810
Jani Nikula1dcec2f2016-03-15 21:51:11 +0200811 return active;
Jani Nikula4e646492013-08-27 15:12:20 +0300812}
813
Ramalingam C6f0e7532016-04-07 14:36:07 +0530814static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
815 struct intel_crtc_state *pipe_config)
816{
817 struct drm_device *dev = encoder->base.dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +0100818 struct drm_i915_private *dev_priv = to_i915(dev);
Ramalingam C6f0e7532016-04-07 14:36:07 +0530819 struct drm_display_mode *adjusted_mode =
820 &pipe_config->base.adjusted_mode;
Ramalingam C042ab0c2016-04-19 13:48:14 +0530821 struct drm_display_mode *adjusted_mode_sw;
822 struct intel_crtc *intel_crtc;
Ramalingam C6f0e7532016-04-07 14:36:07 +0530823 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
Ramalingam Ccefc4e12016-04-19 13:48:13 +0530824 unsigned int lane_count = intel_dsi->lane_count;
Ramalingam C6f0e7532016-04-07 14:36:07 +0530825 unsigned int bpp, fmt;
826 enum port port;
Ramalingam Ccefc4e12016-04-19 13:48:13 +0530827 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
Ramalingam C042ab0c2016-04-19 13:48:14 +0530828 u16 hfp_sw, hsync_sw, hbp_sw;
829 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
830 crtc_hblank_start_sw, crtc_hblank_end_sw;
831
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +0200832 /* FIXME: hw readout should not depend on SW state */
Ramalingam C042ab0c2016-04-19 13:48:14 +0530833 intel_crtc = to_intel_crtc(encoder->base.crtc);
834 adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode;
Ramalingam C6f0e7532016-04-07 14:36:07 +0530835
836 /*
837 * Atleast one port is active as encoder->get_config called only if
838 * encoder->get_hw_state() returns true.
839 */
840 for_each_dsi_port(port, intel_dsi->ports) {
841 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
842 break;
843 }
844
845 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
846 pipe_config->pipe_bpp =
847 mipi_dsi_pixel_format_to_bpp(
848 pixel_format_from_register_bits(fmt));
849 bpp = pipe_config->pipe_bpp;
850
851 /* In terms of pixels */
852 adjusted_mode->crtc_hdisplay =
853 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
854 adjusted_mode->crtc_vdisplay =
855 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
856 adjusted_mode->crtc_vtotal =
857 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
858
Ramalingam Ccefc4e12016-04-19 13:48:13 +0530859 hactive = adjusted_mode->crtc_hdisplay;
860 hfp = I915_READ(MIPI_HFP_COUNT(port));
861
Ramalingam C6f0e7532016-04-07 14:36:07 +0530862 /*
Ramalingam Ccefc4e12016-04-19 13:48:13 +0530863 * Meaningful for video mode non-burst sync pulse mode only,
864 * can be zero for non-burst sync events and burst modes
Ramalingam C6f0e7532016-04-07 14:36:07 +0530865 */
Ramalingam Ccefc4e12016-04-19 13:48:13 +0530866 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
867 hbp = I915_READ(MIPI_HBP_COUNT(port));
868
869 /* harizontal values are in terms of high speed byte clock */
870 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
871 intel_dsi->burst_mode_ratio);
872 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
873 intel_dsi->burst_mode_ratio);
874 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
875 intel_dsi->burst_mode_ratio);
876
877 if (intel_dsi->dual_link) {
878 hfp *= 2;
879 hsync *= 2;
880 hbp *= 2;
881 }
Ramalingam C6f0e7532016-04-07 14:36:07 +0530882
883 /* vertical values are in terms of lines */
884 vfp = I915_READ(MIPI_VFP_COUNT(port));
885 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
886 vbp = I915_READ(MIPI_VBP_COUNT(port));
887
Ramalingam Ccefc4e12016-04-19 13:48:13 +0530888 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
889 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
890 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
Ramalingam C6f0e7532016-04-07 14:36:07 +0530891 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
Ramalingam Ccefc4e12016-04-19 13:48:13 +0530892 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
Ramalingam C6f0e7532016-04-07 14:36:07 +0530893
Ramalingam Ccefc4e12016-04-19 13:48:13 +0530894 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
895 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
Ramalingam C6f0e7532016-04-07 14:36:07 +0530896 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
897 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
Ramalingam C6f0e7532016-04-07 14:36:07 +0530898
Ramalingam C042ab0c2016-04-19 13:48:14 +0530899 /*
900 * In BXT DSI there is no regs programmed with few horizontal timings
901 * in Pixels but txbyteclkhs.. So retrieval process adds some
902 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
903 * Actually here for the given adjusted_mode, we are calculating the
904 * value programmed to the port and then back to the horizontal timing
905 * param in pixels. This is the expected value, including roundup errors
906 * And if that is same as retrieved value from port, then
907 * (HW state) adjusted_mode's horizontal timings are corrected to
908 * match with SW state to nullify the errors.
909 */
910 /* Calculating the value programmed to the Port register */
911 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
912 adjusted_mode_sw->crtc_hdisplay;
913 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
914 adjusted_mode_sw->crtc_hsync_start;
915 hbp_sw = adjusted_mode_sw->crtc_htotal -
916 adjusted_mode_sw->crtc_hsync_end;
917
918 if (intel_dsi->dual_link) {
919 hfp_sw /= 2;
920 hsync_sw /= 2;
921 hbp_sw /= 2;
922 }
923
924 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
925 intel_dsi->burst_mode_ratio);
926 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
927 intel_dsi->burst_mode_ratio);
928 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
929 intel_dsi->burst_mode_ratio);
930
931 /* Reverse calculating the adjusted mode parameters from port reg vals*/
932 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
933 intel_dsi->burst_mode_ratio);
934 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
935 intel_dsi->burst_mode_ratio);
936 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
937 intel_dsi->burst_mode_ratio);
938
939 if (intel_dsi->dual_link) {
940 hfp_sw *= 2;
941 hsync_sw *= 2;
942 hbp_sw *= 2;
943 }
944
945 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
946 hsync_sw + hbp_sw;
947 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
948 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
949 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
950 crtc_hblank_end_sw = crtc_htotal_sw;
951
952 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
953 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
954
955 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
956 adjusted_mode->crtc_hsync_start =
957 adjusted_mode_sw->crtc_hsync_start;
958
959 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
960 adjusted_mode->crtc_hsync_end =
961 adjusted_mode_sw->crtc_hsync_end;
962
963 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
964 adjusted_mode->crtc_hblank_start =
965 adjusted_mode_sw->crtc_hblank_start;
966
967 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
968 adjusted_mode->crtc_hblank_end =
969 adjusted_mode_sw->crtc_hblank_end;
970}
Ramalingam C6f0e7532016-04-07 14:36:07 +0530971
Jani Nikula4e646492013-08-27 15:12:20 +0300972static void intel_dsi_get_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200973 struct intel_crtc_state *pipe_config)
Jani Nikula4e646492013-08-27 15:12:20 +0300974{
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Jani Nikulad7d85d82016-01-08 12:45:39 +0200976 u32 pclk;
Jani Nikula4e646492013-08-27 15:12:20 +0300977 DRM_DEBUG_KMS("\n");
978
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +0100979 if (IS_BROXTON(dev_priv))
Ramalingam C6f0e7532016-04-07 14:36:07 +0530980 bxt_dsi_get_pipe_config(encoder, pipe_config);
981
Ville Syrjälä47eacba2016-04-12 22:14:35 +0300982 pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
983 pipe_config);
Shobhit Kumarf573de52014-07-30 20:32:37 +0530984 if (!pclk)
985 return;
986
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +0200987 pipe_config->base.adjusted_mode.crtc_clock = pclk;
Shobhit Kumarf573de52014-07-30 20:32:37 +0530988 pipe_config->port_clock = pclk;
Jani Nikula4e646492013-08-27 15:12:20 +0300989}
990
Damien Lespiauc19de8e2013-11-28 15:29:18 +0000991static enum drm_mode_status
992intel_dsi_mode_valid(struct drm_connector *connector,
993 struct drm_display_mode *mode)
Jani Nikula4e646492013-08-27 15:12:20 +0300994{
995 struct intel_connector *intel_connector = to_intel_connector(connector);
Ville Syrjäläf4ee2652016-04-12 22:14:37 +0300996 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
Mika Kahola759a1e92015-08-18 14:37:01 +0300997 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
Jani Nikula4e646492013-08-27 15:12:20 +0300998
999 DRM_DEBUG_KMS("\n");
1000
1001 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
1002 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
1003 return MODE_NO_DBLESCAN;
1004 }
1005
1006 if (fixed_mode) {
1007 if (mode->hdisplay > fixed_mode->hdisplay)
1008 return MODE_PANEL;
1009 if (mode->vdisplay > fixed_mode->vdisplay)
1010 return MODE_PANEL;
Mika Kahola759a1e92015-08-18 14:37:01 +03001011 if (fixed_mode->clock > max_dotclk)
1012 return MODE_CLOCK_HIGH;
Jani Nikula4e646492013-08-27 15:12:20 +03001013 }
1014
Jani Nikula36d21f42015-01-16 14:27:20 +02001015 return MODE_OK;
Jani Nikula4e646492013-08-27 15:12:20 +03001016}
1017
1018/* return txclkesc cycles in terms of divider and duration in us */
1019static u16 txclkesc(u32 divider, unsigned int us)
1020{
1021 switch (divider) {
1022 case ESCAPE_CLOCK_DIVIDER_1:
1023 default:
1024 return 20 * us;
1025 case ESCAPE_CLOCK_DIVIDER_2:
1026 return 10 * us;
1027 case ESCAPE_CLOCK_DIVIDER_4:
1028 return 5 * us;
1029 }
1030}
1031
Jani Nikula4e646492013-08-27 15:12:20 +03001032static void set_dsi_timings(struct drm_encoder *encoder,
Ville Syrjälä5e7234c2015-09-25 16:37:43 +03001033 const struct drm_display_mode *adjusted_mode)
Jani Nikula4e646492013-08-27 15:12:20 +03001034{
1035 struct drm_device *dev = encoder->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001036 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikula4e646492013-08-27 15:12:20 +03001037 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
Gaurav K Singhaa102d22014-12-04 10:58:54 +05301038 enum port port;
Jani Nikula1e78aa02016-03-16 12:21:40 +02001039 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
Jani Nikula4e646492013-08-27 15:12:20 +03001040 unsigned int lane_count = intel_dsi->lane_count;
1041
1042 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1043
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001044 hactive = adjusted_mode->crtc_hdisplay;
1045 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1046 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1047 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
Jani Nikula4e646492013-08-27 15:12:20 +03001048
Gaurav K Singhaa102d22014-12-04 10:58:54 +05301049 if (intel_dsi->dual_link) {
1050 hactive /= 2;
1051 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1052 hactive += intel_dsi->pixel_overlap;
1053 hfp /= 2;
1054 hsync /= 2;
1055 hbp /= 2;
1056 }
1057
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001058 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1059 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1060 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
Jani Nikula4e646492013-08-27 15:12:20 +03001061
1062 /* horizontal values are in terms of high speed byte clock */
Shobhit Kumar7f0c8602014-07-30 20:34:57 +05301063 hactive = txbyteclkhs(hactive, bpp, lane_count,
Daniel Vetter7f3de832014-07-30 22:34:27 +02001064 intel_dsi->burst_mode_ratio);
Shobhit Kumar7f0c8602014-07-30 20:34:57 +05301065 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1066 hsync = txbyteclkhs(hsync, bpp, lane_count,
Daniel Vetter7f3de832014-07-30 22:34:27 +02001067 intel_dsi->burst_mode_ratio);
Shobhit Kumar7f0c8602014-07-30 20:34:57 +05301068 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
Jani Nikula4e646492013-08-27 15:12:20 +03001069
Gaurav K Singhaa102d22014-12-04 10:58:54 +05301070 for_each_dsi_port(port, intel_dsi->ports) {
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +01001071 if (IS_BROXTON(dev_priv)) {
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301072 /*
1073 * Program hdisplay and vdisplay on MIPI transcoder.
1074 * This is different from calculated hactive and
1075 * vactive, as they are calculated per channel basis,
1076 * whereas these values should be based on resolution.
1077 */
1078 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001079 adjusted_mode->crtc_hdisplay);
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301080 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001081 adjusted_mode->crtc_vdisplay);
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301082 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001083 adjusted_mode->crtc_vtotal);
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301084 }
1085
Gaurav K Singhaa102d22014-12-04 10:58:54 +05301086 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1087 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
Jani Nikula4e646492013-08-27 15:12:20 +03001088
Gaurav K Singhaa102d22014-12-04 10:58:54 +05301089 /* meaningful for video mode non-burst sync pulse mode only,
1090 * can be zero for non-burst sync events and burst modes */
1091 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1092 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
Jani Nikula4e646492013-08-27 15:12:20 +03001093
Gaurav K Singhaa102d22014-12-04 10:58:54 +05301094 /* vertical values are in terms of lines */
1095 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1096 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1097 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1098 }
Jani Nikula4e646492013-08-27 15:12:20 +03001099}
1100
Jani Nikula1e78aa02016-03-16 12:21:40 +02001101static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1102{
1103 switch (fmt) {
1104 case MIPI_DSI_FMT_RGB888:
1105 return VID_MODE_FORMAT_RGB888;
1106 case MIPI_DSI_FMT_RGB666:
1107 return VID_MODE_FORMAT_RGB666;
1108 case MIPI_DSI_FMT_RGB666_PACKED:
1109 return VID_MODE_FORMAT_RGB666_PACKED;
1110 case MIPI_DSI_FMT_RGB565:
1111 return VID_MODE_FORMAT_RGB565;
1112 default:
1113 MISSING_CASE(fmt);
1114 return VID_MODE_FORMAT_RGB666;
1115 }
1116}
1117
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +02001118static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1119 struct intel_crtc_state *pipe_config)
Jani Nikula4e646492013-08-27 15:12:20 +03001120{
1121 struct drm_encoder *encoder = &intel_encoder->base;
1122 struct drm_device *dev = encoder->dev;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001123 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +02001124 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
Jani Nikula4e646492013-08-27 15:12:20 +03001125 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +02001126 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301127 enum port port;
Jani Nikula1e78aa02016-03-16 12:21:40 +02001128 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
Jani Nikula4e646492013-08-27 15:12:20 +03001129 u32 val, tmp;
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301130 u16 mode_hdisplay;
Jani Nikula4e646492013-08-27 15:12:20 +03001131
Jani Nikulae7d7cad2014-11-14 16:54:21 +02001132 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
Jani Nikula4e646492013-08-27 15:12:20 +03001133
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001134 mode_hdisplay = adjusted_mode->crtc_hdisplay;
Jani Nikula4e646492013-08-27 15:12:20 +03001135
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301136 if (intel_dsi->dual_link) {
1137 mode_hdisplay /= 2;
1138 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1139 mode_hdisplay += intel_dsi->pixel_overlap;
1140 }
Jani Nikula4e646492013-08-27 15:12:20 +03001141
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301142 for_each_dsi_port(port, intel_dsi->ports) {
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +01001143 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301144 /*
1145 * escape clock divider, 20MHz, shared for A and C.
1146 * device ready must be off when doing this! txclkesc?
1147 */
1148 tmp = I915_READ(MIPI_CTRL(PORT_A));
1149 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1150 I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1151 ESCAPE_CLOCK_DIVIDER_1);
Jani Nikula4e646492013-08-27 15:12:20 +03001152
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301153 /* read request priority is per pipe */
1154 tmp = I915_READ(MIPI_CTRL(port));
1155 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1156 I915_WRITE(MIPI_CTRL(port), tmp |
1157 READ_REQUEST_PRIORITY_HIGH);
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +01001158 } else if (IS_BROXTON(dev_priv)) {
Deepak M56c48972015-12-09 20:14:04 +05301159 enum pipe pipe = intel_crtc->pipe;
1160
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301161 tmp = I915_READ(MIPI_CTRL(port));
1162 tmp &= ~BXT_PIPE_SELECT_MASK;
1163
Deepak M56c48972015-12-09 20:14:04 +05301164 tmp |= BXT_PIPE_SELECT(pipe);
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301165 I915_WRITE(MIPI_CTRL(port), tmp);
1166 }
Jani Nikula4e646492013-08-27 15:12:20 +03001167
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301168 /* XXX: why here, why like this? handling in irq handler?! */
1169 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1170 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1171
1172 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1173
1174 I915_WRITE(MIPI_DPI_RESOLUTION(port),
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001175 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301176 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1177 }
Jani Nikula4e646492013-08-27 15:12:20 +03001178
1179 set_dsi_timings(encoder, adjusted_mode);
1180
1181 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1182 if (is_cmd_mode(intel_dsi)) {
1183 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1184 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1185 } else {
1186 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
Jani Nikula1e78aa02016-03-16 12:21:40 +02001187 val |= pixel_format_to_reg(intel_dsi->pixel_format);
Jani Nikula4e646492013-08-27 15:12:20 +03001188 }
Jani Nikula4e646492013-08-27 15:12:20 +03001189
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301190 tmp = 0;
Shobhit Kumarf1c79f12014-04-09 13:59:33 +05301191 if (intel_dsi->eotp_pkt == 0)
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301192 tmp |= EOT_DISABLE;
Shobhit Kumarf1c79f12014-04-09 13:59:33 +05301193 if (intel_dsi->clock_stop)
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301194 tmp |= CLOCKSTOP;
Jani Nikula4e646492013-08-27 15:12:20 +03001195
Jani Nikulaf90e8c32016-06-03 17:57:05 +03001196 if (IS_BROXTON(dev_priv)) {
1197 tmp |= BXT_DPHY_DEFEATURE_EN;
1198 if (!is_cmd_mode(intel_dsi))
1199 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1200 }
1201
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301202 for_each_dsi_port(port, intel_dsi->ports) {
1203 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
Jani Nikula4e646492013-08-27 15:12:20 +03001204
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301205 /* timeouts for recovery. one frame IIUC. if counter expires,
1206 * EOT and stop state. */
Shobhit Kumarcf4dbd22014-04-14 11:18:25 +05301207
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301208 /*
1209 * In burst mode, value greater than one DPI line Time in byte
1210 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1211 * said value is recommended.
1212 *
1213 * In non-burst mode, Value greater than one DPI frame time in
1214 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1215 * said value is recommended.
1216 *
1217 * In DBI only mode, value greater than one DBI frame time in
1218 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1219 * said value is recommended.
1220 */
Jani Nikula4e646492013-08-27 15:12:20 +03001221
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301222 if (is_vid_mode(intel_dsi) &&
1223 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1224 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001225 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
Ville Syrjälä124abe02015-09-08 13:40:45 +03001226 intel_dsi->lane_count,
1227 intel_dsi->burst_mode_ratio) + 1);
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301228 } else {
1229 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
Ville Syrjäläaad941d2015-09-25 16:38:56 +03001230 txbyteclkhs(adjusted_mode->crtc_vtotal *
1231 adjusted_mode->crtc_htotal,
Ville Syrjälä124abe02015-09-08 13:40:45 +03001232 bpp, intel_dsi->lane_count,
1233 intel_dsi->burst_mode_ratio) + 1);
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301234 }
1235 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1236 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1237 intel_dsi->turn_arnd_val);
1238 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1239 intel_dsi->rst_timer_val);
Jani Nikula4e646492013-08-27 15:12:20 +03001240
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301241 /* dphy stuff */
Jani Nikula4e646492013-08-27 15:12:20 +03001242
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301243 /* in terms of low power clock */
1244 I915_WRITE(MIPI_INIT_COUNT(port),
1245 txclkesc(intel_dsi->escape_clk_div, 100));
Jani Nikula4e646492013-08-27 15:12:20 +03001246
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +01001247 if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
Shashank Sharmad2e08c02015-09-01 19:41:40 +05301248 /*
1249 * BXT spec says write MIPI_INIT_COUNT for
1250 * both the ports, even if only one is
1251 * getting used. So write the other port
1252 * if not in dual link mode.
1253 */
1254 I915_WRITE(MIPI_INIT_COUNT(port ==
1255 PORT_A ? PORT_C : PORT_A),
1256 intel_dsi->init_count);
1257 }
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301258
1259 /* recovery disables */
Shobhit Kumar87c54d02015-02-03 12:17:35 +05301260 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
Gaurav K Singh24ee0e62014-12-05 14:24:21 +05301261
1262 /* in terms of low power clock */
1263 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1264
1265 /* in terms of txbyteclkhs. actual high to low switch +
1266 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1267 *
1268 * XXX: write MIPI_STOP_STATE_STALL?
1269 */
1270 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1271 intel_dsi->hs_to_lp_count);
1272
1273 /* XXX: low power clock equivalence in terms of byte clock.
1274 * the number of byte clocks occupied in one low power clock.
1275 * based on txbyteclkhs and txclkesc.
1276 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1277 * ) / 105.???
1278 */
1279 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1280
1281 /* the bw essential for transmitting 16 long packets containing
1282 * 252 bytes meant for dcs write memory command is programmed in
1283 * this register in terms of byte clocks. based on dsi transfer
1284 * rate and the number of lanes configured the time taken to
1285 * transmit 16 long packets in a dsi stream varies. */
1286 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1287
1288 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1289 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1290 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1291
1292 if (is_vid_mode(intel_dsi))
1293 /* Some panels might have resolution which is not a
1294 * multiple of 64 like 1366 x 768. Enable RANDOM
1295 * resolution support for such panels by default */
1296 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1297 intel_dsi->video_frmt_cfg_bits |
1298 intel_dsi->video_mode_format |
1299 IP_TG_CONFIG |
1300 RANDOM_DPI_DISPLAY_RESOLUTION);
1301 }
Jani Nikula4e646492013-08-27 15:12:20 +03001302}
1303
1304static enum drm_connector_status
1305intel_dsi_detect(struct drm_connector *connector, bool force)
1306{
Jani Nikula36d21f42015-01-16 14:27:20 +02001307 return connector_status_connected;
Jani Nikula4e646492013-08-27 15:12:20 +03001308}
1309
1310static int intel_dsi_get_modes(struct drm_connector *connector)
1311{
1312 struct intel_connector *intel_connector = to_intel_connector(connector);
1313 struct drm_display_mode *mode;
1314
1315 DRM_DEBUG_KMS("\n");
1316
1317 if (!intel_connector->panel.fixed_mode) {
1318 DRM_DEBUG_KMS("no fixed mode\n");
1319 return 0;
1320 }
1321
1322 mode = drm_mode_duplicate(connector->dev,
1323 intel_connector->panel.fixed_mode);
1324 if (!mode) {
1325 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1326 return 0;
1327 }
1328
1329 drm_mode_probed_add(connector, mode);
1330 return 1;
1331}
1332
Ville Syrjäläf4ee2652016-04-12 22:14:37 +03001333static int intel_dsi_set_property(struct drm_connector *connector,
1334 struct drm_property *property,
1335 uint64_t val)
1336{
1337 struct drm_device *dev = connector->dev;
1338 struct intel_connector *intel_connector = to_intel_connector(connector);
1339 struct drm_crtc *crtc;
1340 int ret;
1341
1342 ret = drm_object_property_set_value(&connector->base, property, val);
1343 if (ret)
1344 return ret;
1345
1346 if (property == dev->mode_config.scaling_mode_property) {
1347 if (val == DRM_MODE_SCALE_NONE) {
1348 DRM_DEBUG_KMS("no scaling not supported\n");
1349 return -EINVAL;
1350 }
Tvrtko Ursulin49cff962016-10-13 11:02:54 +01001351 if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
Ville Syrjälä234126c2016-04-12 22:14:38 +03001352 val == DRM_MODE_SCALE_CENTER) {
1353 DRM_DEBUG_KMS("centering not supported\n");
1354 return -EINVAL;
1355 }
Ville Syrjäläf4ee2652016-04-12 22:14:37 +03001356
1357 if (intel_connector->panel.fitting_mode == val)
1358 return 0;
1359
1360 intel_connector->panel.fitting_mode = val;
1361 }
1362
Maarten Lankhorst5eff0ed2016-08-09 17:04:09 +02001363 crtc = connector->state->crtc;
Ville Syrjäläf4ee2652016-04-12 22:14:37 +03001364 if (crtc && crtc->state->enable) {
1365 /*
1366 * If the CRTC is enabled, the display will be changed
1367 * according to the new panel fitting mode.
1368 */
1369 intel_crtc_restore_mode(crtc);
1370 }
1371
1372 return 0;
1373}
1374
Jani Nikula593e0622015-01-23 15:30:56 +02001375static void intel_dsi_connector_destroy(struct drm_connector *connector)
Jani Nikula4e646492013-08-27 15:12:20 +03001376{
1377 struct intel_connector *intel_connector = to_intel_connector(connector);
1378
1379 DRM_DEBUG_KMS("\n");
1380 intel_panel_fini(&intel_connector->panel);
Jani Nikula4e646492013-08-27 15:12:20 +03001381 drm_connector_cleanup(connector);
1382 kfree(connector);
1383}
1384
Jani Nikula593e0622015-01-23 15:30:56 +02001385static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1386{
1387 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1388
1389 if (intel_dsi->panel) {
1390 drm_panel_detach(intel_dsi->panel);
1391 /* XXX: Logically this call belongs in the panel driver. */
1392 drm_panel_remove(intel_dsi->panel);
1393 }
Shobhit Kumarfc45e822015-06-26 14:32:09 +05301394
1395 /* dispose of the gpios */
1396 if (intel_dsi->gpio_panel)
1397 gpiod_put(intel_dsi->gpio_panel);
1398
Jani Nikula593e0622015-01-23 15:30:56 +02001399 intel_encoder_destroy(encoder);
1400}
1401
Jani Nikula4e646492013-08-27 15:12:20 +03001402static const struct drm_encoder_funcs intel_dsi_funcs = {
Jani Nikula593e0622015-01-23 15:30:56 +02001403 .destroy = intel_dsi_encoder_destroy,
Jani Nikula4e646492013-08-27 15:12:20 +03001404};
1405
1406static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1407 .get_modes = intel_dsi_get_modes,
1408 .mode_valid = intel_dsi_mode_valid,
Jani Nikula4e646492013-08-27 15:12:20 +03001409};
1410
1411static const struct drm_connector_funcs intel_dsi_connector_funcs = {
Maarten Lankhorst4d688a22015-08-05 12:37:06 +02001412 .dpms = drm_atomic_helper_connector_dpms,
Jani Nikula4e646492013-08-27 15:12:20 +03001413 .detect = intel_dsi_detect,
Chris Wilson1ebaa0b2016-06-24 14:00:15 +01001414 .late_register = intel_connector_register,
Chris Wilsonc191eca2016-06-17 11:40:33 +01001415 .early_unregister = intel_connector_unregister,
Jani Nikula593e0622015-01-23 15:30:56 +02001416 .destroy = intel_dsi_connector_destroy,
Jani Nikula4e646492013-08-27 15:12:20 +03001417 .fill_modes = drm_helper_probe_single_connector_modes,
Ville Syrjäläf4ee2652016-04-12 22:14:37 +03001418 .set_property = intel_dsi_set_property,
Matt Roper2545e4a2015-01-22 16:51:27 -08001419 .atomic_get_property = intel_connector_atomic_get_property,
Matt Roperc6f95f22015-01-22 16:50:32 -08001420 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
Ander Conselvan de Oliveira98969722015-03-20 16:18:06 +02001421 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
Jani Nikula4e646492013-08-27 15:12:20 +03001422};
1423
Ville Syrjäläf4ee2652016-04-12 22:14:37 +03001424static void intel_dsi_add_properties(struct intel_connector *connector)
1425{
1426 struct drm_device *dev = connector->base.dev;
1427
1428 if (connector->panel.fixed_mode) {
1429 drm_mode_create_scaling_mode_property(dev);
1430 drm_object_attach_property(&connector->base.base,
1431 dev->mode_config.scaling_mode_property,
1432 DRM_MODE_SCALE_ASPECT);
1433 connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1434 }
1435}
1436
Damien Lespiau4328633d2014-05-28 12:30:56 +01001437void intel_dsi_init(struct drm_device *dev)
Jani Nikula4e646492013-08-27 15:12:20 +03001438{
1439 struct intel_dsi *intel_dsi;
1440 struct intel_encoder *intel_encoder;
1441 struct drm_encoder *encoder;
1442 struct intel_connector *intel_connector;
1443 struct drm_connector *connector;
Jani Nikula593e0622015-01-23 15:30:56 +02001444 struct drm_display_mode *scan, *fixed_mode = NULL;
Chris Wilsonfac5e232016-07-04 11:34:36 +01001445 struct drm_i915_private *dev_priv = to_i915(dev);
Jani Nikula7e9804f2015-01-16 14:27:23 +02001446 enum port port;
Jani Nikula4e646492013-08-27 15:12:20 +03001447 unsigned int i;
1448
1449 DRM_DEBUG_KMS("\n");
1450
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301451 /* There is no detection method for MIPI so rely on VBT */
Jani Nikula7137aec2016-03-16 12:43:32 +02001452 if (!intel_bios_is_dsi_present(dev_priv, &port))
Damien Lespiau4328633d2014-05-28 12:30:56 +01001453 return;
Jani Nikula4e646492013-08-27 15:12:20 +03001454
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +01001455 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301456 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
Tvrtko Ursuline2d214a2016-10-13 11:03:04 +01001457 } else if (IS_BROXTON(dev_priv)) {
Shashank Sharmac6c794a2016-03-22 12:01:50 +02001458 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301459 } else {
1460 DRM_ERROR("Unsupported Mipi device to reg base");
Christoph Jaeger868d6652014-06-13 21:51:22 +02001461 return;
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301462 }
1463
Jani Nikula4e646492013-08-27 15:12:20 +03001464 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1465 if (!intel_dsi)
Damien Lespiau4328633d2014-05-28 12:30:56 +01001466 return;
Jani Nikula4e646492013-08-27 15:12:20 +03001467
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03001468 intel_connector = intel_connector_alloc();
Jani Nikula4e646492013-08-27 15:12:20 +03001469 if (!intel_connector) {
1470 kfree(intel_dsi);
Damien Lespiau4328633d2014-05-28 12:30:56 +01001471 return;
Jani Nikula4e646492013-08-27 15:12:20 +03001472 }
1473
1474 intel_encoder = &intel_dsi->base;
1475 encoder = &intel_encoder->base;
1476 intel_dsi->attached_connector = intel_connector;
1477
Jani Nikula4e646492013-08-27 15:12:20 +03001478 connector = &intel_connector->base;
1479
Ville Syrjälä13a3d912015-12-09 16:20:18 +02001480 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
Ville Syrjälä580d8ed2016-05-27 20:59:24 +03001481 "DSI %c", port_name(port));
Jani Nikula4e646492013-08-27 15:12:20 +03001482
Jani Nikula4e646492013-08-27 15:12:20 +03001483 intel_encoder->compute_config = intel_dsi_compute_config;
Jani Nikula4e646492013-08-27 15:12:20 +03001484 intel_encoder->pre_enable = intel_dsi_pre_enable;
Shobhit Kumar2634fd72014-04-09 13:59:31 +05301485 intel_encoder->enable = intel_dsi_enable_nop;
Imre Deakc315faf2014-05-27 19:00:09 +03001486 intel_encoder->disable = intel_dsi_pre_disable;
Jani Nikula4e646492013-08-27 15:12:20 +03001487 intel_encoder->post_disable = intel_dsi_post_disable;
1488 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1489 intel_encoder->get_config = intel_dsi_get_config;
1490
1491 intel_connector->get_hw_state = intel_connector_get_hw_state;
1492
Pandiyan, Dhinakaran03cdc1d2016-09-19 18:24:38 -07001493 intel_encoder->port = port;
Jani Nikula2e85ab42016-03-18 17:05:44 +02001494 /*
1495 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1496 * port C. BXT isn't limited like this.
1497 */
1498 if (IS_BROXTON(dev_priv))
1499 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1500 else if (port == PORT_A)
Jani Nikula701d25b2016-03-18 17:05:43 +02001501 intel_encoder->crtc_mask = BIT(PIPE_A);
Jani Nikula7137aec2016-03-16 12:43:32 +02001502 else
Jani Nikula701d25b2016-03-18 17:05:43 +02001503 intel_encoder->crtc_mask = BIT(PIPE_B);
Jani Nikulae7d7cad2014-11-14 16:54:21 +02001504
Jani Nikula90198352016-04-26 16:14:25 +03001505 if (dev_priv->vbt.dsi.config->dual_link) {
Jani Nikula701d25b2016-03-18 17:05:43 +02001506 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
Jani Nikula90198352016-04-26 16:14:25 +03001507
1508 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
1509 case DL_DCS_PORT_A:
1510 intel_dsi->dcs_backlight_ports = BIT(PORT_A);
1511 break;
1512 case DL_DCS_PORT_C:
1513 intel_dsi->dcs_backlight_ports = BIT(PORT_C);
1514 break;
1515 default:
1516 case DL_DCS_PORT_A_AND_C:
1517 intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C);
1518 break;
1519 }
Deepak M1ecc1c62016-04-26 16:14:26 +03001520
1521 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
1522 case DL_DCS_PORT_A:
1523 intel_dsi->dcs_cabc_ports = BIT(PORT_A);
1524 break;
1525 case DL_DCS_PORT_C:
1526 intel_dsi->dcs_cabc_ports = BIT(PORT_C);
1527 break;
1528 default:
1529 case DL_DCS_PORT_A_AND_C:
1530 intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
1531 break;
1532 }
Jani Nikula90198352016-04-26 16:14:25 +03001533 } else {
Jani Nikula701d25b2016-03-18 17:05:43 +02001534 intel_dsi->ports = BIT(port);
Jani Nikula90198352016-04-26 16:14:25 +03001535 intel_dsi->dcs_backlight_ports = BIT(port);
Deepak M1ecc1c62016-04-26 16:14:26 +03001536 intel_dsi->dcs_cabc_ports = BIT(port);
Jani Nikula90198352016-04-26 16:14:25 +03001537 }
Gaurav K Singh82425782015-08-03 15:45:32 +05301538
Deepak M1ecc1c62016-04-26 16:14:26 +03001539 if (!dev_priv->vbt.dsi.config->cabc_supported)
1540 intel_dsi->dcs_cabc_ports = 0;
1541
Jani Nikula7e9804f2015-01-16 14:27:23 +02001542 /* Create a DSI host (and a device) for each port. */
1543 for_each_dsi_port(port, intel_dsi->ports) {
1544 struct intel_dsi_host *host;
1545
1546 host = intel_dsi_host_init(intel_dsi, port);
1547 if (!host)
1548 goto err;
1549
1550 intel_dsi->dsi_hosts[port] = host;
1551 }
1552
Jani Nikula593e0622015-01-23 15:30:56 +02001553 for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1554 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1555 intel_dsi_drivers[i].panel_id);
1556 if (intel_dsi->panel)
Jani Nikula4e646492013-08-27 15:12:20 +03001557 break;
1558 }
1559
Jani Nikula593e0622015-01-23 15:30:56 +02001560 if (!intel_dsi->panel) {
Jani Nikula4e646492013-08-27 15:12:20 +03001561 DRM_DEBUG_KMS("no device found\n");
1562 goto err;
1563 }
1564
Shobhit Kumarfc45e822015-06-26 14:32:09 +05301565 /*
1566 * In case of BYT with CRC PMIC, we need to use GPIO for
1567 * Panel control.
1568 */
1569 if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1570 intel_dsi->gpio_panel =
1571 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1572
1573 if (IS_ERR(intel_dsi->gpio_panel)) {
1574 DRM_ERROR("Failed to own gpio for panel control\n");
1575 intel_dsi->gpio_panel = NULL;
1576 }
1577 }
1578
Jani Nikula4e646492013-08-27 15:12:20 +03001579 intel_encoder->type = INTEL_OUTPUT_DSI;
Ville Syrjäläbc079e82014-03-03 16:15:28 +02001580 intel_encoder->cloneable = 0;
Jani Nikula4e646492013-08-27 15:12:20 +03001581 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1582 DRM_MODE_CONNECTOR_DSI);
1583
1584 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1585
1586 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1587 connector->interlace_allowed = false;
1588 connector->doublescan_allowed = false;
1589
1590 intel_connector_attach_encoder(intel_connector, intel_encoder);
1591
Jani Nikula593e0622015-01-23 15:30:56 +02001592 drm_panel_attach(intel_dsi->panel, connector);
1593
1594 mutex_lock(&dev->mode_config.mutex);
1595 drm_panel_get_modes(intel_dsi->panel);
1596 list_for_each_entry(scan, &connector->probed_modes, head) {
1597 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1598 fixed_mode = drm_mode_duplicate(dev, scan);
1599 break;
1600 }
1601 }
1602 mutex_unlock(&dev->mode_config.mutex);
1603
Jani Nikula4e646492013-08-27 15:12:20 +03001604 if (!fixed_mode) {
1605 DRM_DEBUG_KMS("no fixed mode\n");
1606 goto err;
1607 }
1608
Ville Syrjälädf457242016-05-31 12:08:34 +03001609 connector->display_info.width_mm = fixed_mode->width_mm;
1610 connector->display_info.height_mm = fixed_mode->height_mm;
1611
Vandana Kannan4b6ed682014-02-11 14:26:36 +05301612 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
Chris Wilsonfda9ee92016-06-24 14:00:13 +01001613 intel_panel_setup_backlight(connector, INVALID_PIPE);
Ville Syrjäläf4ee2652016-04-12 22:14:37 +03001614
1615 intel_dsi_add_properties(intel_connector);
1616
Damien Lespiau4328633d2014-05-28 12:30:56 +01001617 return;
Jani Nikula4e646492013-08-27 15:12:20 +03001618
1619err:
1620 drm_encoder_cleanup(&intel_encoder->base);
1621 kfree(intel_dsi);
1622 kfree(intel_connector);
Jani Nikula4e646492013-08-27 15:12:20 +03001623}