Gregory CLEMENT | 34456c7 | 2018-03-15 12:04:17 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
Chris Packham | 5cb1309 | 2017-01-30 12:20:35 +1300 | [diff] [blame] | 2 | /* |
| 3 | * Device Tree file for DB-XC3-24G4XG board |
| 4 | * |
| 5 | * Copyright (C) 2016 Allied Telesis Labs |
| 6 | * |
| 7 | * Based on armada-xp-db.dts |
| 8 | * |
Chris Packham | 5cb1309 | 2017-01-30 12:20:35 +1300 | [diff] [blame] | 9 | * Note: this Device Tree assumes that the bootloader has remapped the |
| 10 | * internal registers to 0xf1000000 (instead of the default |
| 11 | * 0xd0000000). The 0xf1000000 is the default used by the recent, |
| 12 | * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier |
| 13 | * boards were delivered with an older version of the bootloader that |
| 14 | * left internal registers mapped at 0xd0000000. If you are in this |
| 15 | * situation, you should either update your bootloader (preferred |
| 16 | * solution) or the below Device Tree should be adjusted. |
| 17 | */ |
| 18 | |
| 19 | /dts-v1/; |
| 20 | #include "armada-xp-98dx3336.dtsi" |
| 21 | |
| 22 | / { |
| 23 | model = "DB-XC3-24G4XG"; |
Chris Packham | 43e28ba | 2017-02-16 21:50:37 +1300 | [diff] [blame] | 24 | compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp"; |
Chris Packham | 5cb1309 | 2017-01-30 12:20:35 +1300 | [diff] [blame] | 25 | |
| 26 | chosen { |
| 27 | bootargs = "console=ttyS0,115200 earlyprintk"; |
| 28 | }; |
| 29 | |
| 30 | memory { |
| 31 | device_type = "memory"; |
| 32 | reg = <0 0x00000000 0 0x40000000>; /* 1 GB */ |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | &devbus_bootcs { |
| 37 | status = "okay"; |
| 38 | |
| 39 | /* Device Bus parameters are required */ |
| 40 | |
| 41 | /* Read parameters */ |
| 42 | devbus,bus-width = <16>; |
| 43 | devbus,turn-off-ps = <60000>; |
| 44 | devbus,badr-skew-ps = <0>; |
| 45 | devbus,acc-first-ps = <124000>; |
| 46 | devbus,acc-next-ps = <248000>; |
| 47 | devbus,rd-setup-ps = <0>; |
| 48 | devbus,rd-hold-ps = <0>; |
| 49 | |
| 50 | /* Write parameters */ |
| 51 | devbus,sync-enable = <0>; |
| 52 | devbus,wr-high-ps = <60000>; |
| 53 | devbus,wr-low-ps = <60000>; |
| 54 | devbus,ale-wr-ps = <60000>; |
| 55 | }; |
| 56 | |
| 57 | &uart0 { |
| 58 | status = "okay"; |
| 59 | }; |
| 60 | |
| 61 | &uart1 { |
| 62 | status = "okay"; |
| 63 | }; |
| 64 | |
| 65 | &i2c0 { |
| 66 | clock-frequency = <100000>; |
| 67 | status = "okay"; |
| 68 | }; |
| 69 | |
Chris Packham | 3e1ad82 | 2018-07-26 16:02:54 +1200 | [diff] [blame] | 70 | &nand_controller { |
Chris Packham | 5cb1309 | 2017-01-30 12:20:35 +1300 | [diff] [blame] | 71 | status = "okay"; |
Chris Packham | 9c1061195 | 2018-07-26 16:02:56 +1200 | [diff] [blame] | 72 | |
| 73 | nand@0 { |
| 74 | reg = <0>; |
| 75 | label = "pxa3xx_nand-0"; |
| 76 | nand-rb = <0>; |
| 77 | marvell,nand-keep-config; |
| 78 | nand-on-flash-bbt; |
| 79 | nand-ecc-strength = <4>; |
| 80 | nand-ecc-step-size = <512>; |
| 81 | }; |
Chris Packham | 5cb1309 | 2017-01-30 12:20:35 +1300 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | &spi0 { |
| 85 | status = "okay"; |
| 86 | |
| 87 | spi-flash@0 { |
| 88 | #address-cells = <1>; |
| 89 | #size-cells = <1>; |
| 90 | compatible = "m25p64"; |
| 91 | reg = <0>; /* Chip select 0 */ |
| 92 | spi-max-frequency = <20000000>; |
| 93 | m25p,fast-read; |
| 94 | |
| 95 | partition@u-boot { |
| 96 | reg = <0x00000000 0x00100000>; |
| 97 | label = "u-boot"; |
| 98 | }; |
| 99 | partition@u-boot-env { |
| 100 | reg = <0x00100000 0x00040000>; |
| 101 | label = "u-boot-env"; |
| 102 | }; |
| 103 | partition@unused { |
| 104 | reg = <0x00140000 0x00ec0000>; |
| 105 | label = "unused"; |
| 106 | }; |
| 107 | |
| 108 | }; |
| 109 | }; |