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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 7f2dc5c4bcbff035b0d03f7aa78a182664b21e47 / . / drivers / net / wireless / rtlwifi / rtl8723ae / phy.h
blob: 007ebdbbe108623f88c163e77d3e548eabc00eec [file] [log] [blame]
Larry Fingerc592e632012-10-25 13:46:32 -0500[diff] [blame]1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_PHY_H__
31#define __RTL92C_PHY_H__
32
33#define MAX_PRECMD_CNT 16
34#define MAX_RFDEPENDCMD_CNT 16
35#define MAX_POSTCMD_CNT 16
36
37#define MAX_DOZE_WAITING_TIMES_9x 64
38
39#define RT_CANNOT_IO(hw) false
40#define HIGHPOWER_RADIOA_ARRAYLEN 22
41
42#define MAX_TOLERANCE 5
43#define IQK_DELAY_TIME 1
44
45#define APK_BB_REG_NUM 5
46#define APK_AFE_REG_NUM 16
47#define APK_CURVE_REG_NUM 4
48#define PATH_NUM 2
49
50#define LOOP_LIMIT 5
51#define MAX_STALL_TIME 50
52#define AntennaDiversityValue 0x80
53#define MAX_TXPWR_IDX_NMODE_92S 63
54#define Reset_Cnt_Limit 3
55
56#define IQK_MAC_REG_NUM 4
57
58#define RF6052_MAX_PATH 2
59
60#define CT_OFFSET_MAC_ADDR 0X16
61
62#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
63#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
64#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
65#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
66#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
67
68#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
69#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
70
71#define CT_OFFSET_CHANNEL_PLAH 0x75
72#define CT_OFFSET_THERMAL_METER 0x78
73#define CT_OFFSET_RF_OPTION 0x79
74#define CT_OFFSET_VERSION 0x7E
75#define CT_OFFSET_CUSTOMER_ID 0x7F
76
77#define RTL92C_MAX_PATH_NUM 2
78
79enum swchnlcmd_id {
80 CMDID_END,
81 CMDID_SET_TXPOWEROWER_LEVEL,
82 CMDID_BBREGWRITE10,
83 CMDID_WRITEPORT_ULONG,
84 CMDID_WRITEPORT_USHORT,
85 CMDID_WRITEPORT_UCHAR,
86 CMDID_RF_WRITEREG,
87};
88
89struct swchnlcmd {
90 enum swchnlcmd_id cmdid;
91 u32 para1;
92 u32 para2;
93 u32 msdelay;
94};
95
96enum hw90_block_e {
97 HW90_BLOCK_MAC = 0,
98 HW90_BLOCK_PHY0 = 1,
99 HW90_BLOCK_PHY1 = 2,
100 HW90_BLOCK_RF = 3,
101 HW90_BLOCK_MAXIMUM = 4,
102};
103
104enum baseband_config_type {
105 BASEBAND_CONFIG_PHY_REG = 0,
106 BASEBAND_CONFIG_AGC_TAB = 1,
107};
108
109enum ra_offset_area {
110 RA_OFFSET_LEGACY_OFDM1,
111 RA_OFFSET_LEGACY_OFDM2,
112 RA_OFFSET_HT_OFDM1,
113 RA_OFFSET_HT_OFDM2,
114 RA_OFFSET_HT_OFDM3,
115 RA_OFFSET_HT_OFDM4,
116 RA_OFFSET_HT_CCK,
117};
118
119enum antenna_path {
120 ANTENNA_NONE,
121 ANTENNA_D,
122 ANTENNA_C,
123 ANTENNA_CD,
124 ANTENNA_B,
125 ANTENNA_BD,
126 ANTENNA_BC,
127 ANTENNA_BCD,
128 ANTENNA_A,
129 ANTENNA_AD,
130 ANTENNA_AC,
131 ANTENNA_ACD,
132 ANTENNA_AB,
133 ANTENNA_ABD,
134 ANTENNA_ABC,
135 ANTENNA_ABCD
136};
137
138struct r_antenna_select_ofdm {
139 u32 r_tx_antenna:4;
140 u32 r_ant_l:4;
141 u32 r_ant_non_ht:4;
142 u32 r_ant_ht1:4;
143 u32 r_ant_ht2:4;
144 u32 r_ant_ht_s1:4;
145 u32 r_ant_non_ht_s1:4;
146 u32 ofdm_txsc:2;
147 u32 reserved:2;
148};
149
150struct r_antenna_select_cck {
151 u8 r_cckrx_enable_2:2;
152 u8 r_cckrx_enable:2;
153 u8 r_ccktx_enable:4;
154};
155
156struct efuse_contents {
157 u8 mac_addr[ETH_ALEN];
158 u8 cck_tx_power_idx[6];
159 u8 ht40_1s_tx_power_idx[6];
160 u8 ht40_2s_tx_power_idx_diff[3];
161 u8 ht20_tx_power_idx_diff[3];
162 u8 ofdm_tx_power_idx_diff[3];
163 u8 ht40_max_power_offset[3];
164 u8 ht20_max_power_offset[3];
165 u8 channel_plan;
166 u8 thermal_meter;
167 u8 rf_option[5];
168 u8 version;
169 u8 oem_id;
170 u8 regulatory;
171};
172
173struct tx_power_struct {
174 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
175 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
176 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
177 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
178 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
179 u8 legacy_ht_txpowerdiff;
180 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
181 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
182 u8 pwrgroup_cnt;
183 u32 mcs_original_offset[4][16];
184};
185
David S. Miller7009dea2013-10-07 15:40:44 -0400[diff] [blame]186u32 rtl8723ae_phy_query_bb_reg(struct ieee80211_hw *hw,
187 u32 regaddr, u32 bitmask);
188void rtl8723ae_phy_set_bb_reg(struct ieee80211_hw *hw,
189 u32 regaddr, u32 bitmask, u32 data);
Joe Perchesa958df52013-09-23 11:37:59 -0700[diff] [blame]190u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
191 enum radio_path rfpath, u32 regaddr,
192 u32 bitmask);
193void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw,
David S. Miller7009dea2013-10-07 15:40:44 -0400[diff] [blame]194 enum radio_path rfpath, u32 regaddr,
195 u32 bitmask, u32 data);
Joe Perchesa958df52013-09-23 11:37:59 -0700[diff] [blame]196bool rtl8723ae_phy_mac_config(struct ieee80211_hw *hw);
197bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw);
198bool rtl8723ae_phy_rf_config(struct ieee80211_hw *hw);
199bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
200 enum radio_path rfpath);
201void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
David S. Miller7009dea2013-10-07 15:40:44 -0400[diff] [blame]202void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw,
203 long *powerlevel);
204void rtl8723ae_phy_set_txpower_level(struct ieee80211_hw *hw,
205 u8 channel);
Joe Perchesa958df52013-09-23 11:37:59 -0700[diff] [blame]206bool rtl8723ae_phy_update_txpower_dbm(struct ieee80211_hw *hw,
207 long power_indbm);
Joe Perchesa958df52013-09-23 11:37:59 -0700[diff] [blame]208void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
209void rtl8723ae_phy_set_bw_mode(struct ieee80211_hw *hw,
210 enum nl80211_channel_type ch_type);
211void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
212u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw);
213void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery);
Larry Fingerc592e632012-10-25 13:46:32 -0500[diff] [blame]214void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw);
215void rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
216bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
217 enum radio_path rfpath);
218bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
Joe Perchesa958df52013-09-23 11:37:59 -0700[diff] [blame]219bool rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
220 enum rf_pwrstate rfpwr_state);
Larry Fingerc592e632012-10-25 13:46:32 -0500[diff] [blame]221
222#endif