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Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +00001// SPDX-License-Identifier: GPL-2.0
2// Copyright (C) STMicroelectronics 2019
3// Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
4// Pascal Paillet <p.paillet@st.com>.
5
6#include <linux/io.h>
7#include <linux/iopoll.h>
8#include <linux/module.h>
9#include <linux/of_address.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12#include <linux/regulator/driver.h>
13#include <linux/regulator/of_regulator.h>
14
15/*
16 * Registers description
17 */
18#define REG_PWR_CR3 0x0C
19
20#define USB_3_3_EN BIT(24)
21#define USB_3_3_RDY BIT(26)
22#define REG_1_8_EN BIT(28)
23#define REG_1_8_RDY BIT(29)
24#define REG_1_1_EN BIT(30)
25#define REG_1_1_RDY BIT(31)
26
27/* list of supported regulators */
28enum {
29 PWR_REG11,
30 PWR_REG18,
31 PWR_USB33,
32 STM32PWR_REG_NUM_REGS
33};
34
kbuild test robot82f26182019-04-16 00:52:38 +080035static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +000036 [PWR_REG11] = REG_1_1_RDY,
37 [PWR_REG18] = REG_1_8_RDY,
38 [PWR_USB33] = USB_3_3_RDY,
39};
40
41struct stm32_pwr_reg {
42 void __iomem *base;
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +000043 u32 ready_mask;
44};
45
kbuild test robot82f26182019-04-16 00:52:38 +080046static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +000047{
48 struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
49 u32 val;
50
51 val = readl_relaxed(priv->base + REG_PWR_CR3);
52
53 return (val & priv->ready_mask);
54}
55
kbuild test robot82f26182019-04-16 00:52:38 +080056static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +000057{
58 struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
59 u32 val;
60
61 val = readl_relaxed(priv->base + REG_PWR_CR3);
62
Axel Lin7bcbdbe2019-04-30 19:13:45 +080063 return (val & rdev->desc->enable_mask);
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +000064}
65
66static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
67{
68 struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
69 int ret;
70 u32 val;
71
72 val = readl_relaxed(priv->base + REG_PWR_CR3);
Axel Lin7bcbdbe2019-04-30 19:13:45 +080073 val |= rdev->desc->enable_mask;
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +000074 writel_relaxed(val, priv->base + REG_PWR_CR3);
75
76 /* use an arbitrary timeout of 20ms */
77 ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
78 100, 20 * 1000);
79 if (ret)
80 dev_err(&rdev->dev, "regulator enable timed out!\n");
81
82 return ret;
83}
84
85static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
86{
87 struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
88 int ret;
89 u32 val;
90
91 val = readl_relaxed(priv->base + REG_PWR_CR3);
Axel Lin7bcbdbe2019-04-30 19:13:45 +080092 val &= ~rdev->desc->enable_mask;
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +000093 writel_relaxed(val, priv->base + REG_PWR_CR3);
94
95 /* use an arbitrary timeout of 20ms */
96 ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val,
97 100, 20 * 1000);
98 if (ret)
99 dev_err(&rdev->dev, "regulator disable timed out!\n");
100
101 return ret;
102}
103
104static const struct regulator_ops stm32_pwr_reg_ops = {
105 .list_voltage = regulator_list_voltage_linear,
106 .enable = stm32_pwr_reg_enable,
107 .disable = stm32_pwr_reg_disable,
108 .is_enabled = stm32_pwr_reg_is_enabled,
109};
110
111#define PWR_REG(_id, _name, _volt, _en, _supply) \
112 [_id] = { \
113 .id = _id, \
114 .name = _name, \
115 .of_match = of_match_ptr(_name), \
116 .n_voltages = 1, \
117 .type = REGULATOR_VOLTAGE, \
118 .min_uV = _volt, \
119 .fixed_uV = _volt, \
120 .ops = &stm32_pwr_reg_ops, \
121 .enable_mask = _en, \
122 .owner = THIS_MODULE, \
123 .supply_name = _supply, \
124 } \
125
126static const struct regulator_desc stm32_pwr_desc[] = {
127 PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
128 PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
129 PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
130};
131
132static int stm32_pwr_regulator_probe(struct platform_device *pdev)
133{
134 struct device_node *np = pdev->dev.of_node;
135 struct stm32_pwr_reg *priv;
136 void __iomem *base;
137 struct regulator_dev *rdev;
138 struct regulator_config config = { };
139 int i, ret = 0;
140
141 base = of_iomap(np, 0);
Wei Yongjundc62f952019-04-17 02:30:59 +0000142 if (!base) {
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +0000143 dev_err(&pdev->dev, "Unable to map IO memory\n");
Wei Yongjundc62f952019-04-17 02:30:59 +0000144 return -ENOMEM;
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +0000145 }
146
147 config.dev = &pdev->dev;
148
149 for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
150 priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
151 GFP_KERNEL);
152 if (!priv)
153 return -ENOMEM;
154 priv->base = base;
Pascal PAILLET-LME6cdae812019-04-15 09:17:38 +0000155 priv->ready_mask = ready_mask_table[i];
156 config.driver_data = priv;
157
158 rdev = devm_regulator_register(&pdev->dev,
159 &stm32_pwr_desc[i],
160 &config);
161 if (IS_ERR(rdev)) {
162 ret = PTR_ERR(rdev);
163 dev_err(&pdev->dev,
164 "Failed to register regulator: %d\n", ret);
165 break;
166 }
167 }
168 return ret;
169}
170
171static const struct of_device_id stm32_pwr_of_match[] = {
172 { .compatible = "st,stm32mp1,pwr-reg", },
173 {},
174};
175MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);
176
177static struct platform_driver stm32_pwr_driver = {
178 .probe = stm32_pwr_regulator_probe,
179 .driver = {
180 .name = "stm32-pwr-regulator",
181 .of_match_table = of_match_ptr(stm32_pwr_of_match),
182 },
183};
184module_platform_driver(stm32_pwr_driver);
185
186MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
187MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
188MODULE_LICENSE("GPL v2");