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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 72365164cbefe3afa7a146d27d502ed688bf7323 / . / sound / soc / codecs / rt1308.c
blob: d673506c7c3944fd8bb354555d476c72d6d706b9 [file] [log] [blame]
Derek Fang2b9def82019-06-28 20:51:43 +0800[diff] [blame]1/*
2 * rt1308.c -- RT1308 ALSA SoC amplifier component driver
3 *
4 * Copyright 2019 Realtek Semiconductor Corp.
5 * Author: Derek Fang <derek.fang@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/gpio.h>
18#include <linux/i2c.h>
19#include <linux/regmap.h>
20#include <linux/of_gpio.h>
21#include <linux/acpi.h>
22#include <linux/platform_device.h>
23#include <linux/firmware.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include "rl6231.h"
33#include "rt1308.h"
34
35static const struct reg_sequence init_list[] = {
36
37 { RT1308_I2C_I2S_SDW_SET, 0x01014005 },
38 { RT1308_CLASS_D_SET_2, 0x227f5501 },
39 { RT1308_PADS_1, 0x50150505 },
40 { RT1308_VREF, 0x18100000 },
41 { RT1308_IV_SENSE, 0x87010000 },
42 { RT1308_DUMMY_REG, 0x00000200 },
43 { RT1308_SIL_DET, 0x61c30000 },
44 { RT1308_DC_CAL_2, 0x00ffff00 },
45 { RT1308_CLK_DET, 0x01000000 },
46 { RT1308_POWER_STATUS, 0x00800000 },
47 { RT1308_DAC_SET, 0xafaf0700 },
48
49};
50#define RT1308_INIT_REG_LEN ARRAY_SIZE(init_list)
51
52struct rt1308_priv {
53 struct snd_soc_component *component;
54 struct regmap *regmap;
55
56 int sysclk;
57 int sysclk_src;
58 int lrck;
59 int bclk;
60 int master;
61
62 int pll_src;
63 int pll_in;
64 int pll_out;
65};
66
67static const struct reg_default rt1308_reg[] = {
68
69 { 0x01, 0x1f3f5f00 },
70 { 0x02, 0x07000000 },
71 { 0x03, 0x80003e00 },
72 { 0x04, 0x80800600 },
73 { 0x05, 0x0aaa1a0a },
74 { 0x06, 0x52000000 },
75 { 0x07, 0x00000000 },
76 { 0x08, 0x00600000 },
77 { 0x09, 0xe1030000 },
78 { 0x0a, 0x00000000 },
79 { 0x0b, 0x30000000 },
80 { 0x0c, 0x7fff7000 },
81 { 0x10, 0xffff0700 },
82 { 0x11, 0x0a000000 },
83 { 0x12, 0x60040000 },
84 { 0x13, 0x00000000 },
85 { 0x14, 0x0f300000 },
86 { 0x15, 0x00000022 },
87 { 0x16, 0x02000000 },
88 { 0x17, 0x01004045 },
89 { 0x18, 0x00000000 },
90 { 0x19, 0x00000000 },
91 { 0x1a, 0x80000000 },
92 { 0x1b, 0x10325476 },
93 { 0x1c, 0x1d1d0000 },
94 { 0x20, 0xd2101300 },
95 { 0x21, 0xf3ffff00 },
96 { 0x22, 0x00000000 },
97 { 0x23, 0x00000000 },
98 { 0x24, 0x00000000 },
99 { 0x25, 0x00000000 },
100 { 0x26, 0x00000000 },
101 { 0x27, 0x00000000 },
102 { 0x28, 0x00000000 },
103 { 0x29, 0x00000000 },
104 { 0x2a, 0x00000000 },
105 { 0x2b, 0x00000000 },
106 { 0x2c, 0x00000000 },
107 { 0x2d, 0x00000000 },
108 { 0x2e, 0x00000000 },
109 { 0x2f, 0x00000000 },
110 { 0x30, 0x01000000 },
111 { 0x31, 0x20025501 },
112 { 0x32, 0x00000000 },
113 { 0x33, 0x105a0000 },
114 { 0x34, 0x10100000 },
115 { 0x35, 0x2aaa52aa },
116 { 0x36, 0x00c00000 },
117 { 0x37, 0x20046100 },
118 { 0x50, 0x10022f00 },
119 { 0x51, 0x003c0000 },
120 { 0x54, 0x04000000 },
121 { 0x55, 0x01000000 },
122 { 0x56, 0x02000000 },
123 { 0x57, 0x02000000 },
124 { 0x58, 0x02000000 },
125 { 0x59, 0x02000000 },
126 { 0x5b, 0x02000000 },
127 { 0x5c, 0x00000000 },
128 { 0x5d, 0x00000000 },
129 { 0x5e, 0x00000000 },
130 { 0x5f, 0x00000000 },
131 { 0x60, 0x02000000 },
132 { 0x61, 0x00000000 },
133 { 0x62, 0x00000000 },
134 { 0x63, 0x00000000 },
135 { 0x64, 0x00000000 },
136 { 0x65, 0x02000000 },
137 { 0x66, 0x00000000 },
138 { 0x67, 0x00000000 },
139 { 0x68, 0x00000000 },
140 { 0x69, 0x00000000 },
141 { 0x6a, 0x02000000 },
142 { 0x6c, 0x00000000 },
143 { 0x6d, 0x00000000 },
144 { 0x6e, 0x00000000 },
145 { 0x70, 0x10EC1308 },
146 { 0x71, 0x00000000 },
147 { 0x72, 0x00000000 },
148 { 0x73, 0x00000000 },
149 { 0x74, 0x00000000 },
150 { 0x75, 0x00000000 },
151 { 0x76, 0x00000000 },
152 { 0x77, 0x00000000 },
153 { 0x78, 0x00000000 },
154 { 0x79, 0x00000000 },
155 { 0x7a, 0x00000000 },
156 { 0x7b, 0x00000000 },
157 { 0x7c, 0x00000000 },
158 { 0x7d, 0x00000000 },
159 { 0x7e, 0x00000000 },
160 { 0x7f, 0x00020f00 },
161 { 0x80, 0x00000000 },
162 { 0x81, 0x00000000 },
163 { 0x82, 0x00000000 },
164 { 0x83, 0x00000000 },
165 { 0x84, 0x00000000 },
166 { 0x85, 0x00000000 },
167 { 0x86, 0x00000000 },
168 { 0x87, 0x00000000 },
169 { 0x88, 0x00000000 },
170 { 0x89, 0x00000000 },
171 { 0x8a, 0x00000000 },
172 { 0x8b, 0x00000000 },
173 { 0x8c, 0x00000000 },
174 { 0x8d, 0x00000000 },
175 { 0x8e, 0x00000000 },
176 { 0x90, 0x50250905 },
177 { 0x91, 0x15050000 },
178 { 0xa0, 0x00000000 },
179 { 0xa1, 0x00000000 },
180 { 0xa2, 0x00000000 },
181 { 0xa3, 0x00000000 },
182 { 0xa4, 0x00000000 },
183 { 0xb0, 0x00000000 },
184 { 0xb1, 0x00000000 },
185 { 0xb2, 0x00000000 },
186 { 0xb3, 0x00000000 },
187 { 0xb4, 0x00000000 },
188 { 0xb5, 0x00000000 },
189 { 0xb6, 0x00000000 },
190 { 0xb7, 0x00000000 },
191 { 0xb8, 0x00000000 },
192 { 0xb9, 0x00000000 },
193 { 0xba, 0x00000000 },
194 { 0xbb, 0x00000000 },
195 { 0xc0, 0x01000000 },
196 { 0xc1, 0x00000000 },
197 { 0xf0, 0x00000000 },
198};
199
200static int rt1308_reg_init(struct snd_soc_component *component)
201{
202 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
203
204 return regmap_multi_reg_write(rt1308->regmap, init_list,
205 RT1308_INIT_REG_LEN);
206}
207
208static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
209{
210 switch (reg) {
211 case RT1308_RESET:
212 case RT1308_RESET_N:
213 case RT1308_CLK_2:
214 case RT1308_SIL_DET:
215 case RT1308_CLK_DET:
216 case RT1308_DC_DET:
217 case RT1308_DAC_SET:
218 case RT1308_DAC_BUF:
219 case RT1308_SDW_REG_RDATA:
220 case RT1308_DC_CAL_1:
221 case RT1308_PVDD_OFFSET_CTL:
222 case RT1308_CAL_OFFSET_DAC_PBTL:
223 case RT1308_CAL_OFFSET_DAC_L:
224 case RT1308_CAL_OFFSET_DAC_R:
225 case RT1308_CAL_OFFSET_PWM_L:
226 case RT1308_CAL_OFFSET_PWM_R:
227 case RT1308_CAL_PWM_VOS_ADC_L:
228 case RT1308_CAL_PWM_VOS_ADC_R:
229 case RT1308_MBIAS:
230 case RT1308_POWER_STATUS:
231 case RT1308_POWER_INT:
232 case RT1308_SINE_TONE_GEN_2:
233 case RT1308_BQ_SET:
234 case RT1308_BQ_PARA_UPDATE:
235 case RT1308_VEN_DEV_ID:
236 case RT1308_VERSION_ID:
237 case RT1308_EFUSE_1:
238 case RT1308_EFUSE_READ_PVDD_L:
239 case RT1308_EFUSE_READ_PVDD_R:
240 case RT1308_EFUSE_READ_PVDD_PTBL:
241 case RT1308_EFUSE_READ_DEV:
242 case RT1308_EFUSE_READ_R0:
243 case RT1308_EFUSE_READ_ADC_L:
244 case RT1308_EFUSE_READ_ADC_R:
245 case RT1308_EFUSE_READ_ADC_PBTL:
246 case RT1308_EFUSE_RESERVE:
247 case RT1308_EFUSE_DATA_0_MSB:
248 case RT1308_EFUSE_DATA_0_LSB:
249 case RT1308_EFUSE_DATA_1_MSB:
250 case RT1308_EFUSE_DATA_1_LSB:
251 case RT1308_EFUSE_DATA_2_MSB:
252 case RT1308_EFUSE_DATA_2_LSB:
253 case RT1308_EFUSE_DATA_3_MSB:
254 case RT1308_EFUSE_DATA_3_LSB:
255 case RT1308_EFUSE_STATUS_1:
256 case RT1308_EFUSE_STATUS_2:
257 case RT1308_DUMMY_REG:
258 return true;
259 default:
260 return false;
261 }
262}
263
264static bool rt1308_readable_register(struct device *dev, unsigned int reg)
265{
266 switch (reg) {
267 case RT1308_RESET:
268 case RT1308_RESET_N:
269 case RT1308_CLK_GATING ... RT1308_DC_DET_THRES:
270 case RT1308_DAC_SET ... RT1308_AD_FILTER_SET:
271 case RT1308_DC_CAL_1 ... RT1308_POWER_INT:
272 case RT1308_SINE_TONE_GEN_1:
273 case RT1308_SINE_TONE_GEN_2:
274 case RT1308_BQ_SET:
275 case RT1308_BQ_PARA_UPDATE:
276 case RT1308_BQ_PRE_VOL_L ... RT1308_BQ_POST_VOL_R:
277 case RT1308_BQ1_L_H0 ... RT1308_BQ2_R_A2:
278 case RT1308_VEN_DEV_ID:
279 case RT1308_VERSION_ID:
280 case RT1308_SPK_BOUND:
281 case RT1308_BQ1_EQ_L_1 ... RT1308_BQ2_EQ_R_3:
282 case RT1308_EFUSE_1 ... RT1308_EFUSE_RESERVE:
283 case RT1308_PADS_1:
284 case RT1308_PADS_2:
285 case RT1308_TEST_MODE:
286 case RT1308_TEST_1:
287 case RT1308_TEST_2:
288 case RT1308_TEST_3:
289 case RT1308_TEST_4:
290 case RT1308_EFUSE_DATA_0_MSB ... RT1308_EFUSE_STATUS_2:
291 case RT1308_TCON_1:
292 case RT1308_TCON_2:
293 case RT1308_DUMMY_REG:
294 case RT1308_MAX_REG:
295 return true;
296 default:
297 return false;
298 }
299}
300
301static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
302 struct snd_kcontrol *kcontrol, int event)
303{
304 struct snd_soc_component *component =
305 snd_soc_dapm_to_component(w->dapm);
306
307 switch (event) {
308 case SND_SOC_DAPM_POST_PMU:
309 msleep(30);
310 snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
311 RT1308_POW_PDB_REG_BIT, RT1308_POW_PDB_REG_BIT);
312 msleep(40);
313 break;
314 case SND_SOC_DAPM_PRE_PMD:
315 snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
316 RT1308_POW_PDB_REG_BIT, 0);
317 usleep_range(150000, 200000);
318 break;
319
320 default:
321 break;
322 }
323
324 return 0;
325}
326
327static const char * const rt1308_rx_data_ch_select[] = {
328 "LR",
329 "LL",
330 "RL",
331 "RR",
332};
333
334static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, RT1308_DATA_PATH, 24,
335 rt1308_rx_data_ch_select);
336
337static const struct snd_kcontrol_new rt1308_snd_controls[] = {
338
339 /* I2S Data Channel Selection */
340 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
341};
342
343static const struct snd_kcontrol_new rt1308_sto_dac_l =
344 SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
345 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
346
347static const struct snd_kcontrol_new rt1308_sto_dac_r =
348 SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
349 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
350
351static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
352 /* Audio Interface */
353 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
354
355 /* Supply Widgets */
356 SND_SOC_DAPM_SUPPLY("MBIAS20U", RT1308_POWER,
357 RT1308_POW_MBIAS20U_BIT, 0, NULL, 0),
358 SND_SOC_DAPM_SUPPLY("ALDO", RT1308_POWER,
359 RT1308_POW_ALDO_BIT, 0, NULL, 0),
360 SND_SOC_DAPM_SUPPLY("DBG", RT1308_POWER,
361 RT1308_POW_DBG_BIT, 0, NULL, 0),
362 SND_SOC_DAPM_SUPPLY("DACL", RT1308_POWER,
363 RT1308_POW_DACL_BIT, 0, NULL, 0),
364 SND_SOC_DAPM_SUPPLY("CLK25M", RT1308_POWER,
365 RT1308_POW_CLK25M_BIT, 0, NULL, 0),
366 SND_SOC_DAPM_SUPPLY("ADC_R", RT1308_POWER,
367 RT1308_POW_ADC_R_BIT, 0, NULL, 0),
368 SND_SOC_DAPM_SUPPLY("ADC_L", RT1308_POWER,
369 RT1308_POW_ADC_L_BIT, 0, NULL, 0),
370 SND_SOC_DAPM_SUPPLY("DLDO", RT1308_POWER,
371 RT1308_POW_DLDO_BIT, 0, NULL, 0),
372 SND_SOC_DAPM_SUPPLY("VREF", RT1308_POWER,
373 RT1308_POW_VREF_BIT, 0, NULL, 0),
374 SND_SOC_DAPM_SUPPLY("MIXER_R", RT1308_POWER,
375 RT1308_POW_MIXER_R_BIT, 0, NULL, 0),
376 SND_SOC_DAPM_SUPPLY("MIXER_L", RT1308_POWER,
377 RT1308_POW_MIXER_L_BIT, 0, NULL, 0),
378 SND_SOC_DAPM_SUPPLY("MBIAS4U", RT1308_POWER,
379 RT1308_POW_MBIAS4U_BIT, 0, NULL, 0),
380 SND_SOC_DAPM_SUPPLY("PLL2_LDO", RT1308_POWER,
381 RT1308_POW_PLL2_LDO_EN_BIT, 0, NULL, 0),
382 SND_SOC_DAPM_SUPPLY("PLL2B", RT1308_POWER,
383 RT1308_POW_PLL2B_EN_BIT, 0, NULL, 0),
384 SND_SOC_DAPM_SUPPLY("PLL2F", RT1308_POWER,
385 RT1308_POW_PLL2F_EN_BIT, 0, NULL, 0),
386 SND_SOC_DAPM_SUPPLY("PLL2F2", RT1308_POWER,
387 RT1308_POW_PLL2F2_EN_BIT, 0, NULL, 0),
388 SND_SOC_DAPM_SUPPLY("PLL2B2", RT1308_POWER,
389 RT1308_POW_PLL2B2_EN_BIT, 0, NULL, 0),
390
391 /* Digital Interface */
392 SND_SOC_DAPM_SUPPLY("DAC Power", RT1308_POWER,
393 RT1308_POW_DAC1_BIT, 0, NULL, 0),
394 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
395 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
396 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
397
398 /* Output Lines */
399 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
400 rt1308_classd_event,
401 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
402 SND_SOC_DAPM_OUTPUT("SPOL"),
403 SND_SOC_DAPM_OUTPUT("SPOR"),
404};
405
406static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
407
408 { "DAC", NULL, "AIF1RX" },
409
410 { "DAC", NULL, "MBIAS20U" },
411 { "DAC", NULL, "ALDO" },
412 { "DAC", NULL, "DBG" },
413 { "DAC", NULL, "DACL" },
414 { "DAC", NULL, "CLK25M" },
415 { "DAC", NULL, "ADC_R" },
416 { "DAC", NULL, "ADC_L" },
417 { "DAC", NULL, "DLDO" },
418 { "DAC", NULL, "VREF" },
419 { "DAC", NULL, "MIXER_R" },
420 { "DAC", NULL, "MIXER_L" },
421 { "DAC", NULL, "MBIAS4U" },
422 { "DAC", NULL, "PLL2_LDO" },
423 { "DAC", NULL, "PLL2B" },
424 { "DAC", NULL, "PLL2F" },
425 { "DAC", NULL, "PLL2F2" },
426 { "DAC", NULL, "PLL2B2" },
427
428 { "DAC L", "Switch", "DAC" },
429 { "DAC R", "Switch", "DAC" },
430 { "DAC L", NULL, "DAC Power" },
431 { "DAC R", NULL, "DAC Power" },
432
433 { "CLASS D", NULL, "DAC L" },
434 { "CLASS D", NULL, "DAC R" },
435 { "SPOL", NULL, "CLASS D" },
436 { "SPOR", NULL, "CLASS D" },
437};
438
439static int rt1308_get_clk_info(int sclk, int rate)
440{
441 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
442
443 if (sclk <= 0 || rate <= 0)
444 return -EINVAL;
445
446 rate = rate << 8;
447 for (i = 0; i < ARRAY_SIZE(pd); i++)
448 if (sclk == rate * pd[i])
449 return i;
450
451 return -EINVAL;
452}
453
454static int rt1308_hw_params(struct snd_pcm_substream *substream,
455 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
456{
457 struct snd_soc_component *component = dai->component;
458 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
459 unsigned int val_len = 0, val_clk, mask_clk;
460 int pre_div, bclk_ms, frame_size;
461
462 rt1308->lrck = params_rate(params);
463 pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck);
464 if (pre_div < 0) {
465 dev_err(component->dev,
466 "Unsupported clock setting %d\n", rt1308->lrck);
467 return -EINVAL;
468 }
469
470 frame_size = snd_soc_params_to_frame_size(params);
471 if (frame_size < 0) {
472 dev_err(component->dev, "Unsupported frame size: %d\n",
473 frame_size);
474 return -EINVAL;
475 }
476
477 bclk_ms = frame_size > 32;
478 rt1308->bclk = rt1308->lrck * (32 << bclk_ms);
479
480 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
481 bclk_ms, pre_div, dai->id);
482
483 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
484 rt1308->lrck, pre_div, dai->id);
485
486 switch (params_width(params)) {
487 case 16:
488 val_len |= RT1308_I2S_DL_SEL_16B;
489 break;
490 case 20:
491 val_len |= RT1308_I2S_DL_SEL_20B;
492 break;
493 case 24:
494 val_len |= RT1308_I2S_DL_SEL_24B;
495 break;
496 case 8:
497 val_len |= RT1308_I2S_DL_SEL_8B;
498 break;
499 default:
500 return -EINVAL;
501 }
502
503 switch (dai->id) {
504 case RT1308_AIF1:
505 mask_clk = RT1308_DIV_FS_SYS_MASK;
506 val_clk = pre_div << RT1308_DIV_FS_SYS_SFT;
507 snd_soc_component_update_bits(component,
508 RT1308_I2S_SET_2, RT1308_I2S_DL_SEL_MASK,
509 val_len);
510 break;
511 default:
512 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
513 return -EINVAL;
514 }
515
516 snd_soc_component_update_bits(component, RT1308_CLK_1,
517 mask_clk, val_clk);
518
519 return 0;
520}
521
522static int rt1308_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
523{
524 struct snd_soc_component *component = dai->component;
525 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
526 unsigned int reg_val = 0, reg1_val = 0;
527
528 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
529 case SND_SOC_DAIFMT_CBS_CFS:
530 rt1308->master = 0;
531 break;
532 default:
533 return -EINVAL;
534 }
535
536 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
537 case SND_SOC_DAIFMT_I2S:
538 break;
539 case SND_SOC_DAIFMT_LEFT_J:
540 reg_val |= RT1308_I2S_DF_SEL_LEFT;
541 break;
542 case SND_SOC_DAIFMT_DSP_A:
543 reg_val |= RT1308_I2S_DF_SEL_PCM_A;
544 break;
545 case SND_SOC_DAIFMT_DSP_B:
546 reg_val |= RT1308_I2S_DF_SEL_PCM_B;
547 break;
548 default:
549 return -EINVAL;
550 }
551
552 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
553 case SND_SOC_DAIFMT_NB_NF:
554 break;
555 case SND_SOC_DAIFMT_IB_NF:
556 reg1_val |= RT1308_I2S_BCLK_INV;
557 break;
558 default:
559 return -EINVAL;
560 }
561
562 switch (dai->id) {
563 case RT1308_AIF1:
564 snd_soc_component_update_bits(component,
565 RT1308_I2S_SET_1, RT1308_I2S_DF_SEL_MASK,
566 reg_val);
567 snd_soc_component_update_bits(component,
568 RT1308_I2S_SET_2, RT1308_I2S_BCLK_MASK,
569 reg1_val);
570 break;
571 default:
572 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
573 return -EINVAL;
574 }
575 return 0;
576}
577
578static int rt1308_set_component_sysclk(struct snd_soc_component *component,
579 int clk_id, int source, unsigned int freq, int dir)
580{
581 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
582 unsigned int reg_val = 0;
583
584 if (freq == rt1308->sysclk && clk_id == rt1308->sysclk_src)
585 return 0;
586
587 switch (clk_id) {
588 case RT1308_FS_SYS_S_MCLK:
589 reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK;
590 snd_soc_component_update_bits(component,
591 RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
592 RT1308_MCLK_DET_EN);
593 break;
594 case RT1308_FS_SYS_S_BCLK:
595 reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK;
596 break;
597 case RT1308_FS_SYS_S_PLL:
598 reg_val |= RT1308_SEL_FS_SYS_SRC_PLL;
599 break;
600 case RT1308_FS_SYS_S_RCCLK:
601 reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK;
602 break;
603 default:
604 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
605 return -EINVAL;
606 }
607 snd_soc_component_update_bits(component, RT1308_CLK_1,
608 RT1308_SEL_FS_SYS_MASK, reg_val);
609 rt1308->sysclk = freq;
610 rt1308->sysclk_src = clk_id;
611
612 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
613 freq, clk_id);
614
615 return 0;
616}
617
618static int rt1308_set_component_pll(struct snd_soc_component *component,
619 int pll_id, int source, unsigned int freq_in,
620 unsigned int freq_out)
621{
622 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
623 struct rl6231_pll_code pll_code;
624 int ret;
625
626 if (source == rt1308->pll_src && freq_in == rt1308->pll_in &&
627 freq_out == rt1308->pll_out)
628 return 0;
629
630 if (!freq_in || !freq_out) {
631 dev_dbg(component->dev, "PLL disabled\n");
632
633 rt1308->pll_in = 0;
634 rt1308->pll_out = 0;
635 snd_soc_component_update_bits(component,
636 RT1308_CLK_1, RT1308_SEL_FS_SYS_MASK,
637 RT1308_SEL_FS_SYS_SRC_MCLK);
638 return 0;
639 }
640
641 switch (source) {
642 case RT1308_PLL_S_MCLK:
643 snd_soc_component_update_bits(component,
644 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
645 RT1308_SEL_PLL_SRC_MCLK);
646 snd_soc_component_update_bits(component,
647 RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
648 RT1308_MCLK_DET_EN);
649 break;
650 case RT1308_PLL_S_BCLK:
651 snd_soc_component_update_bits(component,
652 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
653 RT1308_SEL_PLL_SRC_BCLK);
654 break;
655 case RT1308_PLL_S_RCCLK:
656 snd_soc_component_update_bits(component,
657 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
658 RT1308_SEL_PLL_SRC_RCCLK);
659 freq_in = 25000000;
660 break;
661 default:
662 dev_err(component->dev, "Unknown PLL Source %d\n", source);
663 return -EINVAL;
664 }
665
666 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
667 if (ret < 0) {
668 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
669 return ret;
670 }
671
672 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
673 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
674 pll_code.n_code, pll_code.k_code);
675
676 snd_soc_component_write(component, RT1308_PLL_1,
677 pll_code.k_code << RT1308_PLL1_K_SFT |
678 pll_code.m_bp << RT1308_PLL1_M_BYPASS_SFT |
679 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1308_PLL1_M_SFT |
680 pll_code.n_code << RT1308_PLL1_N_SFT);
681
682 rt1308->pll_in = freq_in;
683 rt1308->pll_out = freq_out;
684 rt1308->pll_src = source;
685
686 return 0;
687}
688
689static int rt1308_probe(struct snd_soc_component *component)
690{
691 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
692
693 rt1308->component = component;
694
695 return rt1308_reg_init(component);
696}
697
698static void rt1308_remove(struct snd_soc_component *component)
699{
700 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
701
702 regmap_write(rt1308->regmap, RT1308_RESET, 0);
703}
704
705#ifdef CONFIG_PM
706static int rt1308_suspend(struct snd_soc_component *component)
707{
708 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
709
710 regcache_cache_only(rt1308->regmap, true);
711 regcache_mark_dirty(rt1308->regmap);
712
713 return 0;
714}
715
716static int rt1308_resume(struct snd_soc_component *component)
717{
718 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
719
720 regcache_cache_only(rt1308->regmap, false);
721 regcache_sync(rt1308->regmap);
722
723 return 0;
724}
725#else
726#define rt1308_suspend NULL
727#define rt1308_resume NULL
728#endif
729
730#define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
731#define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
732 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
733 SNDRV_PCM_FMTBIT_S24_LE)
734
735static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
736 .hw_params = rt1308_hw_params,
737 .set_fmt = rt1308_set_dai_fmt,
738};
739
740static struct snd_soc_dai_driver rt1308_dai[] = {
741 {
742 .name = "rt1308-aif",
743 .playback = {
744 .stream_name = "AIF1 Playback",
745 .channels_min = 1,
746 .channels_max = 2,
747 .rates = RT1308_STEREO_RATES,
748 .formats = RT1308_FORMATS,
749 },
750 .ops = &rt1308_aif_dai_ops,
751 },
752};
753
754static const struct snd_soc_component_driver soc_component_dev_rt1308 = {
755 .probe = rt1308_probe,
756 .remove = rt1308_remove,
757 .suspend = rt1308_suspend,
758 .resume = rt1308_resume,
759 .controls = rt1308_snd_controls,
760 .num_controls = ARRAY_SIZE(rt1308_snd_controls),
761 .dapm_widgets = rt1308_dapm_widgets,
762 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
763 .dapm_routes = rt1308_dapm_routes,
764 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
765 .set_sysclk = rt1308_set_component_sysclk,
766 .set_pll = rt1308_set_component_pll,
767 .use_pmdown_time = 1,
768 .endianness = 1,
769 .non_legacy_dai_naming = 1,
770};
771
772static const struct regmap_config rt1308_regmap = {
773 .reg_bits = 8,
774 .val_bits = 32,
775 .max_register = RT1308_MAX_REG,
776 .volatile_reg = rt1308_volatile_register,
777 .readable_reg = rt1308_readable_register,
778 .cache_type = REGCACHE_RBTREE,
779 .reg_defaults = rt1308_reg,
780 .num_reg_defaults = ARRAY_SIZE(rt1308_reg),
781 .use_single_read = true,
782 .use_single_write = true,
783};
784
785#ifdef CONFIG_OF
786static const struct of_device_id rt1308_of_match[] = {
787 { .compatible = "realtek,rt1308", },
788 { },
789};
790MODULE_DEVICE_TABLE(of, rt1308_of_match);
791#endif
792
793#ifdef CONFIG_ACPI
794static struct acpi_device_id rt1308_acpi_match[] = {
795 { "10EC1308", 0, },
796 { },
797};
798MODULE_DEVICE_TABLE(acpi, rt1308_acpi_match);
799#endif
800
801static const struct i2c_device_id rt1308_i2c_id[] = {
802 { "rt1308", 0 },
803 { }
804};
805MODULE_DEVICE_TABLE(i2c, rt1308_i2c_id);
806
807static void rt1308_efuse(struct rt1308_priv *rt1308)
808{
809 regmap_write(rt1308->regmap, RT1308_RESET, 0);
810
811 regmap_write(rt1308->regmap, RT1308_POWER, 0xff371600);
812 regmap_write(rt1308->regmap, RT1308_CLK_1, 0x52100000);
813 regmap_write(rt1308->regmap, RT1308_I2C_I2S_SDW_SET, 0x01014005);
814 regmap_write(rt1308->regmap, RT1308_CLASS_D_SET_2, 0x227f5501);
815 regmap_write(rt1308->regmap, RT1308_PADS_1, 0x50150505);
816 regmap_write(rt1308->regmap, RT1308_VREF, 0x18100000);
817 regmap_write(rt1308->regmap, RT1308_IV_SENSE, 0x87010000);
818 regmap_write(rt1308->regmap, RT1308_DUMMY_REG, 0x00000200);
819 regmap_write(rt1308->regmap, RT1308_SIL_DET, 0x61c30000);
820 regmap_write(rt1308->regmap, RT1308_CLK_DET, 0x03700000);
821 regmap_write(rt1308->regmap, RT1308_SINE_TONE_GEN_1, 0x50022f00);
822 regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x01800000);
823 regmap_write(rt1308->regmap, RT1308_DC_CAL_2, 0x00ffff00);
824 regmap_write(rt1308->regmap, RT1308_CLASS_D_SET_2, 0x607e5501);
825
826 regmap_write(rt1308->regmap, RT1308_CLK_2, 0x0060e000);
827 regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x04fe0f00);
828 msleep(100);
829 regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x44fe0f00);
830 msleep(20);
831 regmap_write(rt1308->regmap, RT1308_PVDD_OFFSET_CTL, 0x10000000);
832
833 regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x00800000);
834 regmap_write(rt1308->regmap, RT1308_POWER, 0x0);
835 regmap_write(rt1308->regmap, RT1308_CLK_1, 0x52000000);
836 regmap_write(rt1308->regmap, RT1308_CLASS_D_SET_2, 0x227f5501);
837 regmap_write(rt1308->regmap, RT1308_SINE_TONE_GEN_1, 0x10022f00);
838}
839
840static int rt1308_i2c_probe(struct i2c_client *i2c,
841 const struct i2c_device_id *id)
842{
843 struct rt1308_priv *rt1308;
844 int ret;
845 unsigned int val;
846
847 rt1308 = devm_kzalloc(&i2c->dev, sizeof(struct rt1308_priv),
848 GFP_KERNEL);
849 if (rt1308 == NULL)
850 return -ENOMEM;
851
852 i2c_set_clientdata(i2c, rt1308);
853
854 rt1308->regmap = devm_regmap_init_i2c(i2c, &rt1308_regmap);
855 if (IS_ERR(rt1308->regmap)) {
856 ret = PTR_ERR(rt1308->regmap);
857 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
858 ret);
859 return ret;
860 }
861
862 regmap_read(rt1308->regmap, RT1308_VEN_DEV_ID, &val);
863 /* ignore last byte difference */
864 if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) {
865 dev_err(&i2c->dev,
866 "Device with ID register %x is not rt1308\n", val);
867 return -ENODEV;
868 }
869
870 rt1308_efuse(rt1308);
871
872 return devm_snd_soc_register_component(&i2c->dev,
873 &soc_component_dev_rt1308,
874 rt1308_dai, ARRAY_SIZE(rt1308_dai));
875}
876
877static void rt1308_i2c_shutdown(struct i2c_client *client)
878{
879 struct rt1308_priv *rt1308 = i2c_get_clientdata(client);
880
881 regmap_write(rt1308->regmap, RT1308_RESET, 0);
882}
883
884static struct i2c_driver rt1308_i2c_driver = {
885 .driver = {
886 .name = "rt1308",
Derek Fang2b9def82019-06-28 20:51:43 +0800[diff] [blame]887 .of_match_table = of_match_ptr(rt1308_of_match),
888 .acpi_match_table = ACPI_PTR(rt1308_acpi_match),
889 },
890 .probe = rt1308_i2c_probe,
891 .shutdown = rt1308_i2c_shutdown,
892 .id_table = rt1308_i2c_id,
893};
894module_i2c_driver(rt1308_i2c_driver);
895
896MODULE_DESCRIPTION("ASoC RT1308 amplifier driver");
897MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
898MODULE_LICENSE("GPL v2");