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Vinayak Holikattie0eca632013-02-25 21:44:33 +05301/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.h
5 * Copyright (C) 2011-2013 Samsung India Software Operations
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 * See the COPYING file in the top-level directory or visit
16 * <http://www.gnu.org/licenses/gpl-2.0.html>
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * This program is provided "AS IS" and "WITH ALL FAULTS" and
24 * without warranty of any kind. You are solely responsible for
25 * determining the appropriateness of using and distributing
26 * the program and assume all risks associated with your exercise
27 * of rights with respect to the program, including but not limited
28 * to infringement of third party rights, the risks and costs of
29 * program errors, damage to or loss of data, programs or equipment,
30 * and unavailability or interruption of operations. Under no
31 * circumstances will the contributor of this Program be liable for
32 * any damages of any kind arising from your use or distribution of
33 * this program.
34 */
35
36#ifndef _UFSHCD_H
37#define _UFSHCD_H
38
39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/init.h>
42#include <linux/interrupt.h>
43#include <linux/io.h>
44#include <linux/delay.h>
45#include <linux/slab.h>
46#include <linux/spinlock.h>
47#include <linux/workqueue.h>
48#include <linux/errno.h>
49#include <linux/types.h>
50#include <linux/wait.h>
51#include <linux/bitops.h>
52#include <linux/pm_runtime.h>
53#include <linux/clk.h>
Seungwon Jeon6ccf44fe2013-06-26 22:39:29 +053054#include <linux/completion.h>
Sujit Reddy Thummaaa497612014-09-25 15:32:22 +030055#include <linux/regulator/consumer.h>
Vinayak Holikattie0eca632013-02-25 21:44:33 +053056
57#include <asm/irq.h>
58#include <asm/byteorder.h>
59#include <scsi/scsi.h>
60#include <scsi/scsi_cmnd.h>
61#include <scsi/scsi_host.h>
62#include <scsi/scsi_tcq.h>
63#include <scsi/scsi_dbg.h>
64#include <scsi/scsi_eh.h>
65
66#include "ufs.h"
67#include "ufshci.h"
68
69#define UFSHCD "ufshcd"
70#define UFSHCD_DRIVER_VERSION "0.2"
71
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +030072struct ufs_hba;
73
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +053074enum dev_cmd_type {
75 DEV_CMD_TYPE_NOP = 0x0,
Dolev Raviv68078d52013-07-30 00:35:58 +053076 DEV_CMD_TYPE_QUERY = 0x1,
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +053077};
78
Vinayak Holikattie0eca632013-02-25 21:44:33 +053079/**
80 * struct uic_command - UIC command structure
81 * @command: UIC command
82 * @argument1: UIC command argument 1
83 * @argument2: UIC command argument 2
84 * @argument3: UIC command argument 3
85 * @cmd_active: Indicate if UIC command is outstanding
86 * @result: UIC command result
Seungwon Jeon6ccf44fe2013-06-26 22:39:29 +053087 * @done: UIC command completion
Vinayak Holikattie0eca632013-02-25 21:44:33 +053088 */
89struct uic_command {
90 u32 command;
91 u32 argument1;
92 u32 argument2;
93 u32 argument3;
94 int cmd_active;
95 int result;
Seungwon Jeon6ccf44fe2013-06-26 22:39:29 +053096 struct completion done;
Vinayak Holikattie0eca632013-02-25 21:44:33 +053097};
98
Subhash Jadavani57d104c2014-09-25 15:32:30 +030099/* Used to differentiate the power management options */
100enum ufs_pm_op {
101 UFS_RUNTIME_PM,
102 UFS_SYSTEM_PM,
103 UFS_SHUTDOWN_PM,
104};
105
106#define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM)
107#define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM)
108#define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM)
109
110/* Host <-> Device UniPro Link state */
111enum uic_link_state {
112 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
113 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
114 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
115};
116
117#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
118#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
119 UIC_LINK_ACTIVE_STATE)
120#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
121 UIC_LINK_HIBERN8_STATE)
122#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
123#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
124 UIC_LINK_ACTIVE_STATE)
125#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
126 UIC_LINK_HIBERN8_STATE)
127
128/*
129 * UFS Power management levels.
130 * Each level is in increasing order of power savings.
131 */
132enum ufs_pm_level {
133 UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */
134 UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */
135 UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */
136 UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */
137 UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */
138 UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */
139 UFS_PM_LVL_MAX
140};
141
142struct ufs_pm_lvl_states {
143 enum ufs_dev_pwr_mode dev_state;
144 enum uic_link_state link_state;
145};
146
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530147/**
148 * struct ufshcd_lrb - local reference block
149 * @utr_descriptor_ptr: UTRD address of the command
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530150 * @ucd_req_ptr: UCD address of the command
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530151 * @ucd_rsp_ptr: Response UPIU address for this command
152 * @ucd_prdt_ptr: PRDT address of the command
153 * @cmd: pointer to SCSI command
154 * @sense_buffer: pointer to sense buffer address of the SCSI command
155 * @sense_bufflen: Length of the sense buffer
156 * @scsi_status: SCSI status of the command
157 * @command_type: SCSI, UFS, Query.
158 * @task_tag: Task tag of the command
159 * @lun: LUN of the command
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530160 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530161 */
162struct ufshcd_lrb {
163 struct utp_transfer_req_desc *utr_descriptor_ptr;
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530164 struct utp_upiu_req *ucd_req_ptr;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530165 struct utp_upiu_rsp *ucd_rsp_ptr;
166 struct ufshcd_sg_entry *ucd_prdt_ptr;
167
168 struct scsi_cmnd *cmd;
169 u8 *sense_buffer;
170 unsigned int sense_bufflen;
171 int scsi_status;
172
173 int command_type;
174 int task_tag;
Subhash Jadavani0ce147d2014-09-25 15:32:29 +0300175 u8 lun; /* UPIU LUN id field is only 8-bit wide */
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530176 bool intr_cmd;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530177};
178
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530179/**
Dolev Raviv68078d52013-07-30 00:35:58 +0530180 * struct ufs_query - holds relevent data structures for query request
181 * @request: request upiu and function
182 * @descriptor: buffer for sending/receiving descriptor
183 * @response: response upiu and response
184 */
185struct ufs_query {
186 struct ufs_query_req request;
187 u8 *descriptor;
188 struct ufs_query_res response;
189};
190
191/**
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530192 * struct ufs_dev_cmd - all assosiated fields with device management commands
193 * @type: device management command type - Query, NOP OUT
194 * @lock: lock to allow one command at a time
195 * @complete: internal commands completion
196 * @tag_wq: wait queue until free command slot is available
197 */
198struct ufs_dev_cmd {
199 enum dev_cmd_type type;
200 struct mutex lock;
201 struct completion *complete;
202 wait_queue_head_t tag_wq;
Dolev Raviv68078d52013-07-30 00:35:58 +0530203 struct ufs_query query;
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530204};
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530205
Sujit Reddy Thummac6e79da2014-09-25 15:32:23 +0300206/**
207 * struct ufs_clk_info - UFS clock related info
208 * @list: list headed by hba->clk_list_head
209 * @clk: clock node
210 * @name: clock name
211 * @max_freq: maximum frequency supported by the clock
Sahitya Tummala4cff6d992014-09-25 15:32:33 +0300212 * @min_freq: min frequency that can be used for clock scaling
Sahitya Tummala856b3482014-09-25 15:32:34 +0300213 * @curr_freq: indicates the current frequency that it is set to
Sujit Reddy Thummac6e79da2014-09-25 15:32:23 +0300214 * @enabled: variable to check against multiple enable/disable
215 */
216struct ufs_clk_info {
217 struct list_head list;
218 struct clk *clk;
219 const char *name;
220 u32 max_freq;
Sahitya Tummala4cff6d992014-09-25 15:32:33 +0300221 u32 min_freq;
Sahitya Tummala856b3482014-09-25 15:32:34 +0300222 u32 curr_freq;
Sujit Reddy Thummac6e79da2014-09-25 15:32:23 +0300223 bool enabled;
224};
225
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300226#define PRE_CHANGE 0
227#define POST_CHANGE 1
Dolev Raviv7eb584d2014-09-25 15:32:31 +0300228
229struct ufs_pa_layer_attr {
230 u32 gear_rx;
231 u32 gear_tx;
232 u32 lane_rx;
233 u32 lane_tx;
234 u32 pwr_rx;
235 u32 pwr_tx;
236 u32 hs_rate;
237};
238
239struct ufs_pwr_mode_info {
240 bool is_valid;
241 struct ufs_pa_layer_attr info;
242};
243
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300244/**
245 * struct ufs_hba_variant_ops - variant specific callbacks
246 * @name: variant name
247 * @init: called when the driver is initialized
248 * @exit: called to cleanup everything done in init
Yaniv Gardi9949e702015-05-17 18:55:05 +0300249 * @get_ufs_hci_version: called to get UFS HCI version
Sahitya Tummala856b3482014-09-25 15:32:34 +0300250 * @clk_scale_notify: notifies that clks are scaled up/down
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300251 * @setup_clocks: called before touching any of the controller registers
252 * @setup_regulators: called before accessing the host controller
253 * @hce_enable_notify: called before and after HCE enable bit is set to allow
254 * variant specific Uni-Pro initialization.
255 * @link_startup_notify: called before and after Link startup is carried out
256 * to allow variant specific Uni-Pro initialization.
Dolev Raviv7eb584d2014-09-25 15:32:31 +0300257 * @pwr_change_notify: called before and after a power mode change
258 * is carried out to allow vendor spesific capabilities
259 * to be set.
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300260 * @suspend: called during host controller PM callback
261 * @resume: called during host controller PM callback
Yaniv Gardi6e3fd442015-10-28 13:15:50 +0200262 * @dbg_register_dump: used to dump controller debug information
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300263 */
264struct ufs_hba_variant_ops {
265 const char *name;
266 int (*init)(struct ufs_hba *);
267 void (*exit)(struct ufs_hba *);
Yaniv Gardi9949e702015-05-17 18:55:05 +0300268 u32 (*get_ufs_hci_version)(struct ufs_hba *);
Sahitya Tummala856b3482014-09-25 15:32:34 +0300269 void (*clk_scale_notify)(struct ufs_hba *);
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300270 int (*setup_clocks)(struct ufs_hba *, bool);
271 int (*setup_regulators)(struct ufs_hba *, bool);
272 int (*hce_enable_notify)(struct ufs_hba *, bool);
273 int (*link_startup_notify)(struct ufs_hba *, bool);
Dolev Raviv7eb584d2014-09-25 15:32:31 +0300274 int (*pwr_change_notify)(struct ufs_hba *,
275 bool, struct ufs_pa_layer_attr *,
276 struct ufs_pa_layer_attr *);
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300277 int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
278 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
Yaniv Gardi6e3fd442015-10-28 13:15:50 +0200279 void (*dbg_register_dump)(struct ufs_hba *hba);
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300280};
281
Sahitya Tummala1ab27c92014-09-25 15:32:32 +0300282/* clock gating state */
283enum clk_gating_state {
284 CLKS_OFF,
285 CLKS_ON,
286 REQ_CLKS_OFF,
287 REQ_CLKS_ON,
288};
289
290/**
291 * struct ufs_clk_gating - UFS clock gating related info
292 * @gate_work: worker to turn off clocks after some delay as specified in
293 * delay_ms
294 * @ungate_work: worker to turn on clocks that will be used in case of
295 * interrupt context
296 * @state: the current clocks state
297 * @delay_ms: gating delay in ms
298 * @is_suspended: clk gating is suspended when set to 1 which can be used
299 * during suspend/resume
300 * @delay_attr: sysfs attribute to control delay_attr
301 * @active_reqs: number of requests that are pending and should be waited for
302 * completion before gating clocks.
303 */
304struct ufs_clk_gating {
305 struct delayed_work gate_work;
306 struct work_struct ungate_work;
307 enum clk_gating_state state;
308 unsigned long delay_ms;
309 bool is_suspended;
310 struct device_attribute delay_attr;
311 int active_reqs;
312};
313
Sahitya Tummala856b3482014-09-25 15:32:34 +0300314struct ufs_clk_scaling {
315 ktime_t busy_start_t;
316 bool is_busy_started;
317 unsigned long tot_busy_t;
318 unsigned long window_start_t;
319};
320
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530321/**
Yaniv Gardi3a4bf062014-09-25 15:32:27 +0300322 * struct ufs_init_prefetch - contains data that is pre-fetched once during
323 * initialization
324 * @icc_level: icc level which was read during initialization
325 */
326struct ufs_init_prefetch {
327 u32 icc_level;
328};
329
330/**
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530331 * struct ufs_hba - per adapter private structure
332 * @mmio_base: UFSHCI base register address
333 * @ucdl_base_addr: UFS Command Descriptor base address
334 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
335 * @utmrdl_base_addr: UTP Task Management Descriptor base address
336 * @ucdl_dma_addr: UFS Command Descriptor DMA address
337 * @utrdl_dma_addr: UTRDL DMA address
338 * @utmrdl_dma_addr: UTMRDL DMA address
339 * @host: Scsi_Host instance of the driver
340 * @dev: device handle
341 * @lrb: local reference block
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530342 * @lrb_in_use: lrb in use
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530343 * @outstanding_tasks: Bits representing outstanding task requests
344 * @outstanding_reqs: Bits representing outstanding transfer requests
345 * @capabilities: UFS Controller Capabilities
346 * @nutrs: Transfer Request Queue depth supported by controller
347 * @nutmrs: Task Management Queue depth supported by controller
348 * @ufs_version: UFS Version to which controller complies
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300349 * @vops: pointer to variant specific operations
350 * @priv: pointer to variant specific private data
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530351 * @irq: Irq number of the controller
352 * @active_uic_cmd: handle of active UIC command
Seungwon Jeon6ccf44fe2013-06-26 22:39:29 +0530353 * @uic_cmd_mutex: mutex for uic command
Sujit Reddy Thummae2933132014-05-26 10:59:12 +0530354 * @tm_wq: wait queue for task management
355 * @tm_tag_wq: wait queue for free task management slots
356 * @tm_slots_in_use: bit map of task management request slots in use
Seungwon Jeon53b3d9c2013-08-31 21:40:22 +0530357 * @pwr_done: completion for power mode change
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530358 * @tm_condition: condition variable for task management
359 * @ufshcd_state: UFSHCD states
Sujit Reddy Thumma3441da72014-05-26 10:59:14 +0530360 * @eh_flags: Error handling flags
Seungwon Jeon2fbd0092013-06-26 22:39:27 +0530361 * @intr_mask: Interrupt Mask Bits
Sujit Reddy Thumma66ec6d52013-07-30 00:35:59 +0530362 * @ee_ctrl_mask: Exception event control mask
Sujit Reddy Thumma1d337ec2014-09-25 15:32:26 +0300363 * @is_powered: flag to check if HBA is powered
Yaniv Gardi3a4bf062014-09-25 15:32:27 +0300364 * @is_init_prefetch: flag to check if data was pre-fetched in initialization
365 * @init_prefetch_data: data pre-fetched during initialization
Sujit Reddy Thummae8e7f272014-05-26 10:59:15 +0530366 * @eh_work: Worker to handle UFS errors that require s/w attention
Sujit Reddy Thumma66ec6d52013-07-30 00:35:59 +0530367 * @eeh_work: Worker to handle exception events
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530368 * @errors: HBA errors
Sujit Reddy Thummae8e7f272014-05-26 10:59:15 +0530369 * @uic_error: UFS interconnect layer error status
370 * @saved_err: sticky error mask
371 * @saved_uic_err: sticky UIC error mask
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530372 * @dev_cmd: ufs device management command information
Yaniv Gardicad2e032015-03-31 17:37:14 +0300373 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
Sujit Reddy Thumma66ec6d52013-07-30 00:35:59 +0530374 * @auto_bkops_enabled: to track whether bkops is enabled in device
Sujit Reddy Thummaaa497612014-09-25 15:32:22 +0300375 * @vreg_info: UFS device voltage regulator information
Sujit Reddy Thummac6e79da2014-09-25 15:32:23 +0300376 * @clk_list_head: UFS host controller clocks list node head
Dolev Raviv7eb584d2014-09-25 15:32:31 +0300377 * @pwr_info: holds current power mode
378 * @max_pwr_info: keeps the device max valid pwm
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530379 */
380struct ufs_hba {
381 void __iomem *mmio_base;
382
383 /* Virtual memory reference */
384 struct utp_transfer_cmd_desc *ucdl_base_addr;
385 struct utp_transfer_req_desc *utrdl_base_addr;
386 struct utp_task_req_desc *utmrdl_base_addr;
387
388 /* DMA memory reference */
389 dma_addr_t ucdl_dma_addr;
390 dma_addr_t utrdl_dma_addr;
391 dma_addr_t utmrdl_dma_addr;
392
393 struct Scsi_Host *host;
394 struct device *dev;
Subhash Jadavani2a8fa602014-09-25 15:32:28 +0300395 /*
396 * This field is to keep a reference to "scsi_device" corresponding to
397 * "UFS device" W-LU.
398 */
399 struct scsi_device *sdev_ufs_device;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530400
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300401 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
402 enum uic_link_state uic_link_state;
403 /* Desired UFS power management level during runtime PM */
404 enum ufs_pm_level rpm_lvl;
405 /* Desired UFS power management level during system PM */
406 enum ufs_pm_level spm_lvl;
407 int pm_op_in_progress;
408
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530409 struct ufshcd_lrb *lrb;
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530410 unsigned long lrb_in_use;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530411
412 unsigned long outstanding_tasks;
413 unsigned long outstanding_reqs;
414
415 u32 capabilities;
416 int nutrs;
417 int nutmrs;
418 u32 ufs_version;
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300419 struct ufs_hba_variant_ops *vops;
420 void *priv;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530421 unsigned int irq;
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300422 bool is_irq_enabled;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530423
Yaniv Gardib8521902015-05-17 18:54:57 +0300424 /* Interrupt aggregation support is broken */
425 #define UFSHCD_QUIRK_BROKEN_INTR_AGGR UFS_BIT(0)
426
Yaniv Gardicad2e032015-03-31 17:37:14 +0300427 /*
428 * delay before each dme command is required as the unipro
429 * layer has shown instabilities
430 */
Yaniv Gardib8521902015-05-17 18:54:57 +0300431 #define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS UFS_BIT(1)
432
Yaniv Gardi7ca38cf2015-05-17 18:54:59 +0300433 /*
434 * If UFS host controller is having issue in processing LCC (Line
435 * Control Command) coming from device then enable this quirk.
436 * When this quirk is enabled, host controller driver should disable
437 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
438 * attribute of device to 0).
439 */
440 #define UFSHCD_QUIRK_BROKEN_LCC UFS_BIT(2)
Yaniv Gardicad2e032015-03-31 17:37:14 +0300441
Yaniv Gardic3a2f9e2015-05-17 18:55:01 +0300442 /*
443 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
444 * inbound Link supports unterminated line in HS mode. Setting this
445 * attribute to 1 fixes moving to HS gear.
446 */
447 #define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP UFS_BIT(3)
448
Yaniv Gardi874237f2015-05-17 18:55:03 +0300449 /*
450 * This quirk needs to be enabled if the host contoller only allows
451 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
452 * SLOW AUTO).
453 */
454 #define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE UFS_BIT(4)
455
Yaniv Gardi9949e702015-05-17 18:55:05 +0300456 /*
457 * This quirk needs to be enabled if the host contoller doesn't
458 * advertise the correct version in UFS_VER register. If this quirk
459 * is enabled, standard UFS host driver will call the vendor specific
460 * ops (get_ufs_hci_version) to get the correct version.
461 */
462 #define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5)
463
Yaniv Gardicad2e032015-03-31 17:37:14 +0300464 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
Seungwon Jeon6ccf44fe2013-06-26 22:39:29 +0530465
Sujit Reddy Thummae2933132014-05-26 10:59:12 +0530466 wait_queue_head_t tm_wq;
467 wait_queue_head_t tm_tag_wq;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530468 unsigned long tm_condition;
Sujit Reddy Thummae2933132014-05-26 10:59:12 +0530469 unsigned long tm_slots_in_use;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530470
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300471 struct uic_command *active_uic_cmd;
472 struct mutex uic_cmd_mutex;
473 struct completion *uic_async_done;
Seungwon Jeon53b3d9c2013-08-31 21:40:22 +0530474
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530475 u32 ufshcd_state;
Sujit Reddy Thumma3441da72014-05-26 10:59:14 +0530476 u32 eh_flags;
Seungwon Jeon2fbd0092013-06-26 22:39:27 +0530477 u32 intr_mask;
Sujit Reddy Thumma66ec6d52013-07-30 00:35:59 +0530478 u16 ee_ctrl_mask;
Sujit Reddy Thumma1d337ec2014-09-25 15:32:26 +0300479 bool is_powered;
Yaniv Gardi3a4bf062014-09-25 15:32:27 +0300480 bool is_init_prefetch;
481 struct ufs_init_prefetch init_prefetch_data;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530482
483 /* Work Queues */
Sujit Reddy Thummae8e7f272014-05-26 10:59:15 +0530484 struct work_struct eh_work;
Sujit Reddy Thumma66ec6d52013-07-30 00:35:59 +0530485 struct work_struct eeh_work;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530486
487 /* HBA Errors */
488 u32 errors;
Sujit Reddy Thummae8e7f272014-05-26 10:59:15 +0530489 u32 uic_error;
490 u32 saved_err;
491 u32 saved_uic_err;
Sujit Reddy Thumma5a0b0cb2013-07-30 00:35:57 +0530492
493 /* Device management request data */
494 struct ufs_dev_cmd dev_cmd;
Yaniv Gardicad2e032015-03-31 17:37:14 +0300495 ktime_t last_dme_cmd_tstamp;
Sujit Reddy Thumma66ec6d52013-07-30 00:35:59 +0530496
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300497 /* Keeps information of the UFS device connected to this host */
498 struct ufs_dev_info dev_info;
Sujit Reddy Thumma66ec6d52013-07-30 00:35:59 +0530499 bool auto_bkops_enabled;
Sujit Reddy Thummaaa497612014-09-25 15:32:22 +0300500 struct ufs_vreg_info vreg_info;
Sujit Reddy Thummac6e79da2014-09-25 15:32:23 +0300501 struct list_head clk_list_head;
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300502
503 bool wlun_dev_clr_ua;
Dolev Raviv7eb584d2014-09-25 15:32:31 +0300504
505 struct ufs_pa_layer_attr pwr_info;
506 struct ufs_pwr_mode_info max_pwr_info;
Sahitya Tummala1ab27c92014-09-25 15:32:32 +0300507
508 struct ufs_clk_gating clk_gating;
509 /* Control to enable/disable host capabilities */
510 u32 caps;
511 /* Allow dynamic clk gating */
512#define UFSHCD_CAP_CLK_GATING (1 << 0)
513 /* Allow hiberb8 with clk gating */
514#define UFSHCD_CAP_HIBERN8_WITH_CLK_GATING (1 << 1)
Sahitya Tummala856b3482014-09-25 15:32:34 +0300515 /* Allow dynamic clk scaling */
516#define UFSHCD_CAP_CLK_SCALING (1 << 2)
Subhash Jadavani374a2462014-09-25 15:32:35 +0300517 /* Allow auto bkops to enabled during runtime suspend */
518#define UFSHCD_CAP_AUTO_BKOPS_SUSPEND (1 << 3)
Yaniv Gardib8521902015-05-17 18:54:57 +0300519 /*
520 * This capability allows host controller driver to use the UFS HCI's
521 * interrupt aggregation capability.
522 * CAUTION: Enabling this might reduce overall UFS throughput.
523 */
524#define UFSHCD_CAP_INTR_AGGR (1 << 4)
Sahitya Tummala856b3482014-09-25 15:32:34 +0300525
526 struct devfreq *devfreq;
527 struct ufs_clk_scaling clk_scaling;
Dolev Ravive7850602014-09-25 15:32:36 +0300528 bool is_sys_suspended;
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530529};
530
Sahitya Tummala1ab27c92014-09-25 15:32:32 +0300531/* Returns true if clocks can be gated. Otherwise false */
532static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
533{
534 return hba->caps & UFSHCD_CAP_CLK_GATING;
535}
536static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
537{
538 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
539}
Sahitya Tummala856b3482014-09-25 15:32:34 +0300540static inline int ufshcd_is_clkscaling_enabled(struct ufs_hba *hba)
541{
542 return hba->caps & UFSHCD_CAP_CLK_SCALING;
543}
Subhash Jadavani374a2462014-09-25 15:32:35 +0300544static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
545{
546 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
547}
548
Yaniv Gardib8521902015-05-17 18:54:57 +0300549static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
550{
551 if ((hba->caps & UFSHCD_CAP_INTR_AGGR) &&
552 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR))
553 return true;
554 else
555 return false;
556}
557
Seungwon Jeonb873a2752013-06-26 22:39:26 +0530558#define ufshcd_writel(hba, val, reg) \
559 writel((val), (hba)->mmio_base + (reg))
560#define ufshcd_readl(hba, reg) \
561 readl((hba)->mmio_base + (reg))
562
Dolev Ravive7850602014-09-25 15:32:36 +0300563/**
564 * ufshcd_rmwl - read modify write into a register
565 * @hba - per adapter instance
566 * @mask - mask to apply on read value
567 * @val - actual value to write
568 * @reg - register address
569 */
570static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
571{
572 u32 tmp;
573
574 tmp = ufshcd_readl(hba, reg);
575 tmp &= ~mask;
576 tmp |= (val & mask);
577 ufshcd_writel(hba, tmp, reg);
578}
579
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300580int ufshcd_alloc_host(struct device *, struct ufs_hba **);
Yaniv Gardi47555a52015-10-28 13:15:49 +0200581void ufshcd_dealloc_host(struct ufs_hba *);
Sujit Reddy Thumma5c0c28a2014-09-25 15:32:21 +0300582int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int);
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530583void ufshcd_remove(struct ufs_hba *);
584
585/**
586 * ufshcd_hba_stop - Send controller to reset state
587 * @hba: per adapter instance
588 */
589static inline void ufshcd_hba_stop(struct ufs_hba *hba)
590{
Seungwon Jeonb873a2752013-06-26 22:39:26 +0530591 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530592}
593
Dolev Raviv68078d52013-07-30 00:35:58 +0530594static inline void check_upiu_size(void)
595{
596 BUILD_BUG_ON(ALIGNED_UPIU_SIZE <
597 GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE);
598}
599
Yaniv Gardi1ce58982015-10-28 13:15:47 +0200600/**
601 * ufshcd_set_variant - set variant specific data to the hba
602 * @hba - per adapter instance
603 * @variant - pointer to variant specific data
604 */
605static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
606{
607 BUG_ON(!hba);
608 hba->priv = variant;
609}
610
611/**
612 * ufshcd_get_variant - get variant specific data from the hba
613 * @hba - per adapter instance
614 */
615static inline void *ufshcd_get_variant(struct ufs_hba *hba)
616{
617 BUG_ON(!hba);
618 return hba->priv;
619}
620
Sujit Reddy Thumma66ec6d52013-07-30 00:35:59 +0530621extern int ufshcd_runtime_suspend(struct ufs_hba *hba);
622extern int ufshcd_runtime_resume(struct ufs_hba *hba);
623extern int ufshcd_runtime_idle(struct ufs_hba *hba);
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300624extern int ufshcd_system_suspend(struct ufs_hba *hba);
625extern int ufshcd_system_resume(struct ufs_hba *hba);
626extern int ufshcd_shutdown(struct ufs_hba *hba);
Seungwon Jeon12b4fdb2013-08-31 21:40:21 +0530627extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
628 u8 attr_set, u32 mib_val, u8 peer);
629extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
630 u32 *mib_val, u8 peer);
631
632/* UIC command interfaces for DME primitives */
633#define DME_LOCAL 0
634#define DME_PEER 1
635#define ATTR_SET_NOR 0 /* NORMAL */
636#define ATTR_SET_ST 1 /* STATIC */
637
638static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
639 u32 mib_val)
640{
641 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
642 mib_val, DME_LOCAL);
643}
644
645static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
646 u32 mib_val)
647{
648 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
649 mib_val, DME_LOCAL);
650}
651
652static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
653 u32 mib_val)
654{
655 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
656 mib_val, DME_PEER);
657}
658
659static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
660 u32 mib_val)
661{
662 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
663 mib_val, DME_PEER);
664}
665
666static inline int ufshcd_dme_get(struct ufs_hba *hba,
667 u32 attr_sel, u32 *mib_val)
668{
669 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
670}
671
672static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
673 u32 attr_sel, u32 *mib_val)
674{
675 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
676}
677
Sahitya Tummala1ab27c92014-09-25 15:32:32 +0300678int ufshcd_hold(struct ufs_hba *hba, bool async);
679void ufshcd_release(struct ufs_hba *hba);
Yaniv Gardi0263bcd2015-10-28 13:15:48 +0200680
681/* Wrapper functions for safely calling variant operations */
682static inline const char *ufshcd_get_var_name(struct ufs_hba *hba)
683{
684 if (hba->vops)
685 return hba->vops->name;
686 return "";
687}
688
689static inline int ufshcd_vops_init(struct ufs_hba *hba)
690{
691 if (hba->vops && hba->vops->init)
692 return hba->vops->init(hba);
693
694 return 0;
695}
696
697static inline void ufshcd_vops_exit(struct ufs_hba *hba)
698{
699 if (hba->vops && hba->vops->exit)
700 return hba->vops->exit(hba);
701}
702
703static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba)
704{
705 if (hba->vops && hba->vops->get_ufs_hci_version)
706 return hba->vops->get_ufs_hci_version(hba);
707
708 return ufshcd_readl(hba, REG_UFS_VERSION);
709}
710
711static inline void ufshcd_vops_clk_scale_notify(struct ufs_hba *hba)
712{
713 if (hba->vops && hba->vops->clk_scale_notify)
714 return hba->vops->clk_scale_notify(hba);
715}
716
717static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on)
718{
719 if (hba->vops && hba->vops->setup_clocks)
720 return hba->vops->setup_clocks(hba, on);
721
722 return 0;
723}
724
725static inline int ufshcd_vops_setup_regulators(struct ufs_hba *hba, bool status)
726{
727 if (hba->vops && hba->vops->setup_regulators)
728 return hba->vops->setup_regulators(hba, status);
729
730 return 0;
731}
732
733static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba,
734 bool status)
735{
736 if (hba->vops && hba->vops->hce_enable_notify)
737 return hba->vops->hce_enable_notify(hba, status);
738
739 return 0;
740}
741static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba,
742 bool status)
743{
744 if (hba->vops && hba->vops->link_startup_notify)
745 return hba->vops->link_startup_notify(hba, status);
746
747 return 0;
748}
749
750static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba,
751 bool status,
752 struct ufs_pa_layer_attr *dev_max_params,
753 struct ufs_pa_layer_attr *dev_req_params)
754{
755 if (hba->vops && hba->vops->pwr_change_notify)
756 return hba->vops->pwr_change_notify(hba, status,
757 dev_max_params, dev_req_params);
758
759 return -ENOTSUPP;
760}
761
762static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op)
763{
764 if (hba->vops && hba->vops->suspend)
765 return hba->vops->suspend(hba, op);
766
767 return 0;
768}
769
770static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op)
771{
772 if (hba->vops && hba->vops->resume)
773 return hba->vops->resume(hba, op);
774
775 return 0;
776}
777
Yaniv Gardi6e3fd442015-10-28 13:15:50 +0200778static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba)
779{
780 if (hba->vops && hba->vops->dbg_register_dump)
781 hba->vops->dbg_register_dump(hba);
782}
783
Vinayak Holikattie0eca632013-02-25 21:44:33 +0530784#endif /* End of Header */