| Nishad Kamdar | 7603eab | 2019-06-15 08:27:42 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Benjamin Herrenschmidt | 6a794a2 | 2018-06-12 09:55:04 +1000 | [diff] [blame] | 2 | #ifndef __CF_FSI_FW_H |
| 3 | #define __CF_FSI_FW_H |
| 4 | |
| 5 | /* |
| 6 | * uCode file layout |
| 7 | * |
| 8 | * 0000...03ff : m68k exception vectors |
| 9 | * 0400...04ff : Header info & boot config block |
| 10 | * 0500....... : Code & stack |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Header info & boot config area |
| 15 | * |
| 16 | * The Header info is built into the ucode and provide version and |
| 17 | * platform information. |
| 18 | * |
| 19 | * the Boot config needs to be adjusted by the ARM prior to starting |
| 20 | * the ucode if the Command/Status area isn't at 0x320000 in CF space |
| 21 | * (ie. beginning of SRAM). |
| 22 | */ |
| 23 | |
| 24 | #define HDR_OFFSET 0x400 |
| 25 | |
| 26 | /* Info: Signature & version */ |
| 27 | #define HDR_SYS_SIG 0x00 /* 2 bytes system signature */ |
| 28 | #define SYS_SIG_SHARED 0x5348 |
| 29 | #define SYS_SIG_SPLIT 0x5350 |
| 30 | #define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */ |
| 31 | #define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */ |
| 32 | #define API_VERSION_MAJ 2 /* Current version */ |
| 33 | #define API_VERSION_MIN 1 |
| 34 | #define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */ |
| 35 | #define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */ |
| 36 | #define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */ |
| 37 | #define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */ |
| 38 | |
| 39 | /* Boot Config: Address of Command/Status area */ |
| 40 | #define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */ |
| 41 | #define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */ |
| 42 | #define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */ |
| 43 | #define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */ |
| 44 | #define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */ |
| 45 | #define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */ |
| 46 | #define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */ |
| 47 | #define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */ |
| 48 | #define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */ |
| 49 | #define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */ |
| 50 | #define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */ |
| 51 | #define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */ |
| 52 | #define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */ |
| 53 | #define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */ |
| 54 | |
| 55 | /* |
| 56 | * Command/Status area layout: Main part |
| 57 | */ |
| 58 | |
| 59 | /* Command/Status register: |
| 60 | * |
| 61 | * +---------------------------+ |
| 62 | * | STAT | RLEN | CLEN | CMD | |
| 63 | * | 8 | 8 | 8 | 8 | |
| 64 | * +---------------------------+ |
| 65 | * | | | | |
| 66 | * status | | | |
| 67 | * Response len | | |
| 68 | * (in bits) | | |
| 69 | * | | |
| 70 | * Command len | |
| 71 | * (in bits) | |
| 72 | * | |
| 73 | * Command code |
| 74 | * |
| 75 | * Due to the big endian layout, that means that a byte read will |
| 76 | * return the status byte |
| 77 | */ |
| 78 | #define CMD_STAT_REG 0x00 |
| 79 | #define CMD_REG_CMD_MASK 0x000000ff |
| 80 | #define CMD_REG_CMD_SHIFT 0 |
| 81 | #define CMD_NONE 0x00 |
| 82 | #define CMD_COMMAND 0x01 |
| 83 | #define CMD_BREAK 0x02 |
| 84 | #define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */ |
| 85 | #define CMD_INVALID 0xff |
| 86 | #define CMD_REG_CLEN_MASK 0x0000ff00 |
| 87 | #define CMD_REG_CLEN_SHIFT 8 |
| 88 | #define CMD_REG_RLEN_MASK 0x00ff0000 |
| 89 | #define CMD_REG_RLEN_SHIFT 16 |
| 90 | #define CMD_REG_STAT_MASK 0xff000000 |
| 91 | #define CMD_REG_STAT_SHIFT 24 |
| 92 | #define STAT_WORKING 0x00 |
| 93 | #define STAT_COMPLETE 0x01 |
| 94 | #define STAT_ERR_INVAL_CMD 0x80 |
| 95 | #define STAT_ERR_INVAL_IRQ 0x81 |
| 96 | #define STAT_ERR_MTOE 0x82 |
| 97 | |
| 98 | /* Response tag & CRC */ |
| 99 | #define STAT_RTAG 0x04 |
| 100 | |
| 101 | /* Response CRC */ |
| 102 | #define STAT_RCRC 0x05 |
| 103 | |
| 104 | /* Echo and Send delay */ |
| 105 | #define ECHO_DLY_REG 0x08 |
| 106 | #define SEND_DLY_REG 0x09 |
| 107 | |
| 108 | /* Command data area |
| 109 | * |
| 110 | * Last byte of message must be left aligned |
| 111 | */ |
| 112 | #define CMD_DATA 0x10 /* 64 bit of data */ |
| 113 | |
| 114 | /* Response data area, right aligned, unused top bits are 1 */ |
| 115 | #define RSP_DATA 0x20 /* 32 bit of data */ |
| 116 | |
| 117 | /* Misc */ |
| 118 | #define INT_CNT 0x30 /* 32-bit interrupt count */ |
| 119 | #define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */ |
| 120 | #define CF_STARTED 0x38 /* byte, set to -1 when copro started */ |
| 121 | #define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */ |
| 122 | |
| 123 | /* |
| 124 | * SRAM layout: GPIO arbitration part |
| 125 | */ |
| 126 | #define ARB_REG 0x40 |
| 127 | #define ARB_ARM_REQ 0x01 |
| 128 | #define ARB_ARM_ACK 0x02 |
| 129 | |
| 130 | /* Misc2 */ |
| 131 | #define CF_RESET_D0 0x50 |
| 132 | #define CF_RESET_D1 0x54 |
| 133 | #define BAD_INT_S0 0x58 |
| 134 | #define BAD_INT_S1 0x5c |
| 135 | #define STOP_CNT 0x60 |
| 136 | |
| 137 | /* Internal */ |
| 138 | |
| 139 | /* |
| 140 | * SRAM layout: Trace buffer (debug builds only) |
| 141 | */ |
| 142 | #define TRACEBUF 0x100 |
| 143 | #define TR_CLKOBIT0 0xc0 |
| 144 | #define TR_CLKOBIT1 0xc1 |
| 145 | #define TR_CLKOSTART 0x82 |
| 146 | #define TR_OLEN 0x83 /* + len */ |
| 147 | #define TR_CLKZ 0x84 /* + count */ |
| 148 | #define TR_CLKWSTART 0x85 |
| 149 | #define TR_CLKTAG 0x86 /* + tag */ |
| 150 | #define TR_CLKDATA 0x87 /* + len */ |
| 151 | #define TR_CLKCRC 0x88 /* + raw crc */ |
| 152 | #define TR_CLKIBIT0 0x90 |
| 153 | #define TR_CLKIBIT1 0x91 |
| 154 | #define TR_END 0xff |
| 155 | |
| 156 | #endif /* __CF_FSI_FW_H */ |
| 157 | |