Yoshihiro Shimoda | 36239c6 | 2010-07-06 04:32:16 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Renesas R0P7757LC0012RL Support. |
| 3 | * |
| 4 | * Copyright (C) 2009 - 2010 Renesas Solutions Corp. |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file "COPYING" in the main directory of this archive |
| 8 | * for more details. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/platform_device.h> |
| 13 | #include <linux/gpio.h> |
| 14 | #include <linux/irq.h> |
| 15 | #include <linux/spi/spi.h> |
| 16 | #include <linux/spi/flash.h> |
| 17 | #include <linux/io.h> |
Yoshihiro Shimoda | 65f63eab | 2011-02-25 07:40:27 +0000 | [diff] [blame^] | 18 | #include <linux/mmc/host.h> |
| 19 | #include <linux/mmc/sh_mmcif.h> |
| 20 | #include <linux/mfd/sh_mobile_sdhi.h> |
Yoshihiro Shimoda | 36239c6 | 2010-07-06 04:32:16 +0000 | [diff] [blame] | 21 | #include <cpu/sh7757.h> |
| 22 | #include <asm/sh_eth.h> |
| 23 | #include <asm/heartbeat.h> |
| 24 | |
| 25 | static struct resource heartbeat_resource = { |
| 26 | .start = 0xffec005c, /* PUDR */ |
| 27 | .end = 0xffec005c, |
| 28 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, |
| 29 | }; |
| 30 | |
| 31 | static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; |
| 32 | |
| 33 | static struct heartbeat_data heartbeat_data = { |
| 34 | .bit_pos = heartbeat_bit_pos, |
| 35 | .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), |
| 36 | .flags = HEARTBEAT_INVERTED, |
| 37 | }; |
| 38 | |
| 39 | static struct platform_device heartbeat_device = { |
| 40 | .name = "heartbeat", |
| 41 | .id = -1, |
| 42 | .dev = { |
| 43 | .platform_data = &heartbeat_data, |
| 44 | }, |
| 45 | .num_resources = 1, |
| 46 | .resource = &heartbeat_resource, |
| 47 | }; |
| 48 | |
| 49 | /* Fast Ethernet */ |
| 50 | static struct resource sh_eth0_resources[] = { |
| 51 | { |
| 52 | .start = 0xfef00000, |
| 53 | .end = 0xfef001ff, |
| 54 | .flags = IORESOURCE_MEM, |
| 55 | }, { |
| 56 | .start = 84, |
| 57 | .end = 84, |
| 58 | .flags = IORESOURCE_IRQ, |
| 59 | }, |
| 60 | }; |
| 61 | |
| 62 | static struct sh_eth_plat_data sh7757_eth0_pdata = { |
| 63 | .phy = 1, |
| 64 | .edmac_endian = EDMAC_LITTLE_ENDIAN, |
| 65 | }; |
| 66 | |
| 67 | static struct platform_device sh7757_eth0_device = { |
| 68 | .name = "sh-eth", |
| 69 | .resource = sh_eth0_resources, |
| 70 | .id = 0, |
| 71 | .num_resources = ARRAY_SIZE(sh_eth0_resources), |
| 72 | .dev = { |
| 73 | .platform_data = &sh7757_eth0_pdata, |
| 74 | }, |
| 75 | }; |
| 76 | |
| 77 | static struct resource sh_eth1_resources[] = { |
| 78 | { |
| 79 | .start = 0xfef00800, |
| 80 | .end = 0xfef009ff, |
| 81 | .flags = IORESOURCE_MEM, |
| 82 | }, { |
| 83 | .start = 84, |
| 84 | .end = 84, |
| 85 | .flags = IORESOURCE_IRQ, |
| 86 | }, |
| 87 | }; |
| 88 | |
| 89 | static struct sh_eth_plat_data sh7757_eth1_pdata = { |
| 90 | .phy = 1, |
| 91 | .edmac_endian = EDMAC_LITTLE_ENDIAN, |
| 92 | }; |
| 93 | |
| 94 | static struct platform_device sh7757_eth1_device = { |
| 95 | .name = "sh-eth", |
| 96 | .resource = sh_eth1_resources, |
| 97 | .id = 1, |
| 98 | .num_resources = ARRAY_SIZE(sh_eth1_resources), |
| 99 | .dev = { |
| 100 | .platform_data = &sh7757_eth1_pdata, |
| 101 | }, |
| 102 | }; |
| 103 | |
Yoshihiro Shimoda | 65f63eab | 2011-02-25 07:40:27 +0000 | [diff] [blame^] | 104 | /* SH_MMCIF */ |
| 105 | static struct resource sh_mmcif_resources[] = { |
| 106 | [0] = { |
| 107 | .start = 0xffcb0000, |
| 108 | .end = 0xffcb00ff, |
| 109 | .flags = IORESOURCE_MEM, |
| 110 | }, |
| 111 | [1] = { |
| 112 | .start = 211, |
| 113 | .flags = IORESOURCE_IRQ, |
| 114 | }, |
| 115 | [2] = { |
| 116 | .start = 212, |
| 117 | .flags = IORESOURCE_IRQ, |
| 118 | }, |
| 119 | }; |
| 120 | |
| 121 | static struct sh_mmcif_dma sh7757lcr_mmcif_dma = { |
| 122 | .chan_priv_tx = SHDMA_SLAVE_MMCIF_TX, |
| 123 | .chan_priv_rx = SHDMA_SLAVE_MMCIF_RX, |
| 124 | }; |
| 125 | |
| 126 | static struct sh_mmcif_plat_data sh_mmcif_plat = { |
| 127 | .dma = &sh7757lcr_mmcif_dma, |
| 128 | .sup_pclk = 0x0f, |
| 129 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
| 130 | .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, |
| 131 | }; |
| 132 | |
| 133 | static struct platform_device sh_mmcif_device = { |
| 134 | .name = "sh_mmcif", |
| 135 | .id = 0, |
| 136 | .dev = { |
| 137 | .platform_data = &sh_mmcif_plat, |
| 138 | }, |
| 139 | .num_resources = ARRAY_SIZE(sh_mmcif_resources), |
| 140 | .resource = sh_mmcif_resources, |
| 141 | }; |
| 142 | |
| 143 | /* SDHI0 */ |
| 144 | static struct sh_mobile_sdhi_info sdhi_info = { |
| 145 | .dma_slave_tx = SHDMA_SLAVE_SDHI_TX, |
| 146 | .dma_slave_rx = SHDMA_SLAVE_SDHI_RX, |
| 147 | .tmio_caps = MMC_CAP_SD_HIGHSPEED, |
| 148 | }; |
| 149 | |
| 150 | static struct resource sdhi_resources[] = { |
| 151 | [0] = { |
| 152 | .start = 0xffe50000, |
| 153 | .end = 0xffe501ff, |
| 154 | .flags = IORESOURCE_MEM, |
| 155 | }, |
| 156 | [1] = { |
| 157 | .start = 20, |
| 158 | .flags = IORESOURCE_IRQ, |
| 159 | }, |
| 160 | }; |
| 161 | |
| 162 | static struct platform_device sdhi_device = { |
| 163 | .name = "sh_mobile_sdhi", |
| 164 | .num_resources = ARRAY_SIZE(sdhi_resources), |
| 165 | .resource = sdhi_resources, |
| 166 | .id = 0, |
| 167 | .dev = { |
| 168 | .platform_data = &sdhi_info, |
| 169 | }, |
| 170 | }; |
| 171 | |
Yoshihiro Shimoda | 36239c6 | 2010-07-06 04:32:16 +0000 | [diff] [blame] | 172 | static struct platform_device *sh7757lcr_devices[] __initdata = { |
| 173 | &heartbeat_device, |
| 174 | &sh7757_eth0_device, |
| 175 | &sh7757_eth1_device, |
Yoshihiro Shimoda | 65f63eab | 2011-02-25 07:40:27 +0000 | [diff] [blame^] | 176 | &sh_mmcif_device, |
| 177 | &sdhi_device, |
Yoshihiro Shimoda | 36239c6 | 2010-07-06 04:32:16 +0000 | [diff] [blame] | 178 | }; |
| 179 | |
Yoshihiro Shimoda | ceb7afe | 2011-02-25 07:39:32 +0000 | [diff] [blame] | 180 | static struct flash_platform_data spi_flash_data = { |
| 181 | .name = "m25p80", |
| 182 | .type = "m25px64", |
| 183 | }; |
| 184 | |
| 185 | static struct spi_board_info spi_board_info[] = { |
| 186 | { |
| 187 | .modalias = "m25p80", |
| 188 | .max_speed_hz = 25000000, |
| 189 | .bus_num = 0, |
| 190 | .chip_select = 1, |
| 191 | .platform_data = &spi_flash_data, |
| 192 | }, |
| 193 | }; |
| 194 | |
Yoshihiro Shimoda | 36239c6 | 2010-07-06 04:32:16 +0000 | [diff] [blame] | 195 | static int __init sh7757lcr_devices_setup(void) |
| 196 | { |
| 197 | /* RGMII (PTA) */ |
| 198 | gpio_request(GPIO_FN_ET0_MDC, NULL); |
| 199 | gpio_request(GPIO_FN_ET0_MDIO, NULL); |
| 200 | gpio_request(GPIO_FN_ET1_MDC, NULL); |
| 201 | gpio_request(GPIO_FN_ET1_MDIO, NULL); |
| 202 | |
| 203 | /* ONFI (PTB, PTZ) */ |
| 204 | gpio_request(GPIO_FN_ON_NRE, NULL); |
| 205 | gpio_request(GPIO_FN_ON_NWE, NULL); |
| 206 | gpio_request(GPIO_FN_ON_NWP, NULL); |
| 207 | gpio_request(GPIO_FN_ON_NCE0, NULL); |
| 208 | gpio_request(GPIO_FN_ON_R_B0, NULL); |
| 209 | gpio_request(GPIO_FN_ON_ALE, NULL); |
| 210 | gpio_request(GPIO_FN_ON_CLE, NULL); |
| 211 | |
| 212 | gpio_request(GPIO_FN_ON_DQ7, NULL); |
| 213 | gpio_request(GPIO_FN_ON_DQ6, NULL); |
| 214 | gpio_request(GPIO_FN_ON_DQ5, NULL); |
| 215 | gpio_request(GPIO_FN_ON_DQ4, NULL); |
| 216 | gpio_request(GPIO_FN_ON_DQ3, NULL); |
| 217 | gpio_request(GPIO_FN_ON_DQ2, NULL); |
| 218 | gpio_request(GPIO_FN_ON_DQ1, NULL); |
| 219 | gpio_request(GPIO_FN_ON_DQ0, NULL); |
| 220 | |
| 221 | /* IRQ8 to 0 (PTB, PTC) */ |
| 222 | gpio_request(GPIO_FN_IRQ8, NULL); |
| 223 | gpio_request(GPIO_FN_IRQ7, NULL); |
| 224 | gpio_request(GPIO_FN_IRQ6, NULL); |
| 225 | gpio_request(GPIO_FN_IRQ5, NULL); |
| 226 | gpio_request(GPIO_FN_IRQ4, NULL); |
| 227 | gpio_request(GPIO_FN_IRQ3, NULL); |
| 228 | gpio_request(GPIO_FN_IRQ2, NULL); |
| 229 | gpio_request(GPIO_FN_IRQ1, NULL); |
| 230 | gpio_request(GPIO_FN_IRQ0, NULL); |
| 231 | |
| 232 | /* SPI0 (PTD) */ |
| 233 | gpio_request(GPIO_FN_SP0_MOSI, NULL); |
| 234 | gpio_request(GPIO_FN_SP0_MISO, NULL); |
| 235 | gpio_request(GPIO_FN_SP0_SCK, NULL); |
| 236 | gpio_request(GPIO_FN_SP0_SCK_FB, NULL); |
| 237 | gpio_request(GPIO_FN_SP0_SS0, NULL); |
| 238 | gpio_request(GPIO_FN_SP0_SS1, NULL); |
| 239 | gpio_request(GPIO_FN_SP0_SS2, NULL); |
| 240 | gpio_request(GPIO_FN_SP0_SS3, NULL); |
| 241 | |
| 242 | /* RMII 0/1 (PTE, PTF) */ |
| 243 | gpio_request(GPIO_FN_RMII0_CRS_DV, NULL); |
| 244 | gpio_request(GPIO_FN_RMII0_TXD1, NULL); |
| 245 | gpio_request(GPIO_FN_RMII0_TXD0, NULL); |
| 246 | gpio_request(GPIO_FN_RMII0_TXEN, NULL); |
| 247 | gpio_request(GPIO_FN_RMII0_REFCLK, NULL); |
| 248 | gpio_request(GPIO_FN_RMII0_RXD1, NULL); |
| 249 | gpio_request(GPIO_FN_RMII0_RXD0, NULL); |
| 250 | gpio_request(GPIO_FN_RMII0_RX_ER, NULL); |
| 251 | gpio_request(GPIO_FN_RMII1_CRS_DV, NULL); |
| 252 | gpio_request(GPIO_FN_RMII1_TXD1, NULL); |
| 253 | gpio_request(GPIO_FN_RMII1_TXD0, NULL); |
| 254 | gpio_request(GPIO_FN_RMII1_TXEN, NULL); |
| 255 | gpio_request(GPIO_FN_RMII1_REFCLK, NULL); |
| 256 | gpio_request(GPIO_FN_RMII1_RXD1, NULL); |
| 257 | gpio_request(GPIO_FN_RMII1_RXD0, NULL); |
| 258 | gpio_request(GPIO_FN_RMII1_RX_ER, NULL); |
| 259 | |
| 260 | /* eMMC (PTG) */ |
| 261 | gpio_request(GPIO_FN_MMCCLK, NULL); |
| 262 | gpio_request(GPIO_FN_MMCCMD, NULL); |
| 263 | gpio_request(GPIO_FN_MMCDAT7, NULL); |
| 264 | gpio_request(GPIO_FN_MMCDAT6, NULL); |
| 265 | gpio_request(GPIO_FN_MMCDAT5, NULL); |
| 266 | gpio_request(GPIO_FN_MMCDAT4, NULL); |
| 267 | gpio_request(GPIO_FN_MMCDAT3, NULL); |
| 268 | gpio_request(GPIO_FN_MMCDAT2, NULL); |
| 269 | gpio_request(GPIO_FN_MMCDAT1, NULL); |
| 270 | gpio_request(GPIO_FN_MMCDAT0, NULL); |
| 271 | |
| 272 | /* LPC (PTG, PTH, PTQ, PTU) */ |
| 273 | gpio_request(GPIO_FN_SERIRQ, NULL); |
| 274 | gpio_request(GPIO_FN_LPCPD, NULL); |
| 275 | gpio_request(GPIO_FN_LDRQ, NULL); |
| 276 | gpio_request(GPIO_FN_WP, NULL); |
| 277 | gpio_request(GPIO_FN_FMS0, NULL); |
| 278 | gpio_request(GPIO_FN_LAD3, NULL); |
| 279 | gpio_request(GPIO_FN_LAD2, NULL); |
| 280 | gpio_request(GPIO_FN_LAD1, NULL); |
| 281 | gpio_request(GPIO_FN_LAD0, NULL); |
| 282 | gpio_request(GPIO_FN_LFRAME, NULL); |
| 283 | gpio_request(GPIO_FN_LRESET, NULL); |
| 284 | gpio_request(GPIO_FN_LCLK, NULL); |
| 285 | gpio_request(GPIO_FN_LGPIO7, NULL); |
| 286 | gpio_request(GPIO_FN_LGPIO6, NULL); |
| 287 | gpio_request(GPIO_FN_LGPIO5, NULL); |
| 288 | gpio_request(GPIO_FN_LGPIO4, NULL); |
| 289 | |
| 290 | /* SPI1 (PTH) */ |
| 291 | gpio_request(GPIO_FN_SP1_MOSI, NULL); |
| 292 | gpio_request(GPIO_FN_SP1_MISO, NULL); |
| 293 | gpio_request(GPIO_FN_SP1_SCK, NULL); |
| 294 | gpio_request(GPIO_FN_SP1_SCK_FB, NULL); |
| 295 | gpio_request(GPIO_FN_SP1_SS0, NULL); |
| 296 | gpio_request(GPIO_FN_SP1_SS1, NULL); |
| 297 | |
| 298 | /* SDHI (PTI) */ |
| 299 | gpio_request(GPIO_FN_SD_WP, NULL); |
| 300 | gpio_request(GPIO_FN_SD_CD, NULL); |
| 301 | gpio_request(GPIO_FN_SD_CLK, NULL); |
| 302 | gpio_request(GPIO_FN_SD_CMD, NULL); |
| 303 | gpio_request(GPIO_FN_SD_D3, NULL); |
| 304 | gpio_request(GPIO_FN_SD_D2, NULL); |
| 305 | gpio_request(GPIO_FN_SD_D1, NULL); |
| 306 | gpio_request(GPIO_FN_SD_D0, NULL); |
| 307 | |
| 308 | /* SCIF3/4 (PTJ, PTW) */ |
| 309 | gpio_request(GPIO_FN_RTS3, NULL); |
| 310 | gpio_request(GPIO_FN_CTS3, NULL); |
| 311 | gpio_request(GPIO_FN_TXD3, NULL); |
| 312 | gpio_request(GPIO_FN_RXD3, NULL); |
| 313 | gpio_request(GPIO_FN_RTS4, NULL); |
| 314 | gpio_request(GPIO_FN_RXD4, NULL); |
| 315 | gpio_request(GPIO_FN_TXD4, NULL); |
| 316 | gpio_request(GPIO_FN_CTS4, NULL); |
| 317 | |
| 318 | /* SERMUX (PTK, PTL, PTO, PTV) */ |
| 319 | gpio_request(GPIO_FN_COM2_TXD, NULL); |
| 320 | gpio_request(GPIO_FN_COM2_RXD, NULL); |
| 321 | gpio_request(GPIO_FN_COM2_RTS, NULL); |
| 322 | gpio_request(GPIO_FN_COM2_CTS, NULL); |
| 323 | gpio_request(GPIO_FN_COM2_DTR, NULL); |
| 324 | gpio_request(GPIO_FN_COM2_DSR, NULL); |
| 325 | gpio_request(GPIO_FN_COM2_DCD, NULL); |
| 326 | gpio_request(GPIO_FN_COM2_RI, NULL); |
| 327 | gpio_request(GPIO_FN_RAC_RXD, NULL); |
| 328 | gpio_request(GPIO_FN_RAC_RTS, NULL); |
| 329 | gpio_request(GPIO_FN_RAC_CTS, NULL); |
| 330 | gpio_request(GPIO_FN_RAC_DTR, NULL); |
| 331 | gpio_request(GPIO_FN_RAC_DSR, NULL); |
| 332 | gpio_request(GPIO_FN_RAC_DCD, NULL); |
| 333 | gpio_request(GPIO_FN_RAC_TXD, NULL); |
| 334 | gpio_request(GPIO_FN_COM1_TXD, NULL); |
| 335 | gpio_request(GPIO_FN_COM1_RXD, NULL); |
| 336 | gpio_request(GPIO_FN_COM1_RTS, NULL); |
| 337 | gpio_request(GPIO_FN_COM1_CTS, NULL); |
| 338 | |
| 339 | writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */ |
| 340 | |
| 341 | /* IIC (PTM, PTR, PTS) */ |
| 342 | gpio_request(GPIO_FN_SDA7, NULL); |
| 343 | gpio_request(GPIO_FN_SCL7, NULL); |
| 344 | gpio_request(GPIO_FN_SDA6, NULL); |
| 345 | gpio_request(GPIO_FN_SCL6, NULL); |
| 346 | gpio_request(GPIO_FN_SDA5, NULL); |
| 347 | gpio_request(GPIO_FN_SCL5, NULL); |
| 348 | gpio_request(GPIO_FN_SDA4, NULL); |
| 349 | gpio_request(GPIO_FN_SCL4, NULL); |
| 350 | gpio_request(GPIO_FN_SDA3, NULL); |
| 351 | gpio_request(GPIO_FN_SCL3, NULL); |
| 352 | gpio_request(GPIO_FN_SDA2, NULL); |
| 353 | gpio_request(GPIO_FN_SCL2, NULL); |
| 354 | gpio_request(GPIO_FN_SDA1, NULL); |
| 355 | gpio_request(GPIO_FN_SCL1, NULL); |
| 356 | gpio_request(GPIO_FN_SDA0, NULL); |
| 357 | gpio_request(GPIO_FN_SCL0, NULL); |
| 358 | |
| 359 | /* USB (PTN) */ |
| 360 | gpio_request(GPIO_FN_VBUS_EN, NULL); |
| 361 | gpio_request(GPIO_FN_VBUS_OC, NULL); |
| 362 | |
| 363 | /* SGPIO1/0 (PTN, PTO) */ |
| 364 | gpio_request(GPIO_FN_SGPIO1_CLK, NULL); |
| 365 | gpio_request(GPIO_FN_SGPIO1_LOAD, NULL); |
| 366 | gpio_request(GPIO_FN_SGPIO1_DI, NULL); |
| 367 | gpio_request(GPIO_FN_SGPIO1_DO, NULL); |
| 368 | gpio_request(GPIO_FN_SGPIO0_CLK, NULL); |
| 369 | gpio_request(GPIO_FN_SGPIO0_LOAD, NULL); |
| 370 | gpio_request(GPIO_FN_SGPIO0_DI, NULL); |
| 371 | gpio_request(GPIO_FN_SGPIO0_DO, NULL); |
| 372 | |
| 373 | /* WDT (PTN) */ |
| 374 | gpio_request(GPIO_FN_SUB_CLKIN, NULL); |
| 375 | |
| 376 | /* System (PTT) */ |
| 377 | gpio_request(GPIO_FN_STATUS1, NULL); |
| 378 | gpio_request(GPIO_FN_STATUS0, NULL); |
| 379 | |
| 380 | /* PWMX (PTT) */ |
| 381 | gpio_request(GPIO_FN_PWMX1, NULL); |
| 382 | gpio_request(GPIO_FN_PWMX0, NULL); |
| 383 | |
| 384 | /* R-SPI (PTV) */ |
| 385 | gpio_request(GPIO_FN_R_SPI_MOSI, NULL); |
| 386 | gpio_request(GPIO_FN_R_SPI_MISO, NULL); |
| 387 | gpio_request(GPIO_FN_R_SPI_RSPCK, NULL); |
| 388 | gpio_request(GPIO_FN_R_SPI_SSL0, NULL); |
| 389 | gpio_request(GPIO_FN_R_SPI_SSL1, NULL); |
| 390 | |
| 391 | /* EVC (PTV, PTW) */ |
| 392 | gpio_request(GPIO_FN_EVENT7, NULL); |
| 393 | gpio_request(GPIO_FN_EVENT6, NULL); |
| 394 | gpio_request(GPIO_FN_EVENT5, NULL); |
| 395 | gpio_request(GPIO_FN_EVENT4, NULL); |
| 396 | gpio_request(GPIO_FN_EVENT3, NULL); |
| 397 | gpio_request(GPIO_FN_EVENT2, NULL); |
| 398 | gpio_request(GPIO_FN_EVENT1, NULL); |
| 399 | gpio_request(GPIO_FN_EVENT0, NULL); |
| 400 | |
| 401 | /* LED for heartbeat */ |
| 402 | gpio_request(GPIO_PTU3, NULL); |
| 403 | gpio_direction_output(GPIO_PTU3, 1); |
| 404 | gpio_request(GPIO_PTU2, NULL); |
| 405 | gpio_direction_output(GPIO_PTU2, 1); |
| 406 | gpio_request(GPIO_PTU1, NULL); |
| 407 | gpio_direction_output(GPIO_PTU1, 1); |
| 408 | gpio_request(GPIO_PTU0, NULL); |
| 409 | gpio_direction_output(GPIO_PTU0, 1); |
| 410 | |
| 411 | /* control for MDIO of Gigabit Ethernet */ |
| 412 | gpio_request(GPIO_PTT4, NULL); |
| 413 | gpio_direction_output(GPIO_PTT4, 1); |
| 414 | |
| 415 | /* control for eMMC */ |
| 416 | gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */ |
| 417 | gpio_direction_output(GPIO_PTT7, 0); |
| 418 | gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */ |
| 419 | gpio_direction_output(GPIO_PTT6, 0); |
| 420 | gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ |
| 421 | gpio_direction_output(GPIO_PTT5, 1); |
| 422 | |
Yoshihiro Shimoda | ceb7afe | 2011-02-25 07:39:32 +0000 | [diff] [blame] | 423 | /* register SPI device information */ |
| 424 | spi_register_board_info(spi_board_info, |
| 425 | ARRAY_SIZE(spi_board_info)); |
| 426 | |
Yoshihiro Shimoda | 36239c6 | 2010-07-06 04:32:16 +0000 | [diff] [blame] | 427 | /* General platform */ |
| 428 | return platform_add_devices(sh7757lcr_devices, |
| 429 | ARRAY_SIZE(sh7757lcr_devices)); |
| 430 | } |
| 431 | arch_initcall(sh7757lcr_devices_setup); |
| 432 | |
| 433 | /* Initialize IRQ setting */ |
| 434 | void __init init_sh7757lcr_IRQ(void) |
| 435 | { |
| 436 | plat_irq_setup_pins(IRQ_MODE_IRQ7654); |
| 437 | plat_irq_setup_pins(IRQ_MODE_IRQ3210); |
| 438 | } |
| 439 | |
| 440 | /* Initialize the board */ |
| 441 | static void __init sh7757lcr_setup(char **cmdline_p) |
| 442 | { |
| 443 | printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n"); |
| 444 | } |
| 445 | |
| 446 | static int sh7757lcr_mode_pins(void) |
| 447 | { |
| 448 | int value = 0; |
| 449 | |
| 450 | /* These are the factory default settings of S3 (Low active). |
| 451 | * If you change these dip switches then you will need to |
| 452 | * adjust the values below as well. |
| 453 | */ |
| 454 | value |= MODE_PIN0; /* Clock Mode: 1 */ |
| 455 | |
| 456 | return value; |
| 457 | } |
| 458 | |
| 459 | /* The Machine Vector */ |
| 460 | static struct sh_machine_vector mv_sh7757lcr __initmv = { |
| 461 | .mv_name = "SH7757LCR", |
| 462 | .mv_setup = sh7757lcr_setup, |
| 463 | .mv_init_irq = init_sh7757lcr_IRQ, |
| 464 | .mv_mode_pins = sh7757lcr_mode_pins, |
| 465 | }; |
| 466 | |