| Mauro Carvalho Chehab | ccf988b | 2019-07-26 09:51:16 -0300 | [diff] [blame] | 1 | ================== |
| Vadim Pasternak | 6bec23b | 2016-11-20 16:56:14 +0000 | [diff] [blame] | 2 | Driver i2c-mlxcpld |
| Mauro Carvalho Chehab | ccf988b | 2019-07-26 09:51:16 -0300 | [diff] [blame] | 3 | ================== |
| Vadim Pasternak | 6bec23b | 2016-11-20 16:56:14 +0000 | [diff] [blame] | 4 | |
| 5 | Author: Michael Shych <michaelsh@mellanox.com> |
| 6 | |
| 7 | This is the Mellanox I2C controller logic, implemented in Lattice CPLD |
| 8 | device. |
| Mauro Carvalho Chehab | ccf988b | 2019-07-26 09:51:16 -0300 | [diff] [blame] | 9 | |
| Vadim Pasternak | 6bec23b | 2016-11-20 16:56:14 +0000 | [diff] [blame] | 10 | Device supports: |
| 11 | - Master mode. |
| 12 | - One physical bus. |
| 13 | - Polling mode. |
| 14 | |
| 15 | This controller is equipped within the next Mellanox systems: |
| 16 | "msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", |
| 17 | "msn2740", "msn2100". |
| 18 | |
| 19 | The next transaction types are supported: |
| 20 | - Receive Byte/Block. |
| 21 | - Send Byte/Block. |
| 22 | - Read Byte/Block. |
| 23 | - Write Byte/Block. |
| 24 | |
| 25 | Registers: |
| Mauro Carvalho Chehab | ccf988b | 2019-07-26 09:51:16 -0300 | [diff] [blame] | 26 | |
| 27 | =============== === ======================================================================= |
| Michael Shych | 27aaa8a | 2018-03-27 14:01:26 +0000 | [diff] [blame] | 28 | CPBLTY 0x0 - capability reg. |
| 29 | Bits [6:5] - transaction length. b01 - 72B is supported, |
| 30 | 36B in other case. |
| 31 | Bit 7 - SMBus block read support. |
| Vadim Pasternak | 6bec23b | 2016-11-20 16:56:14 +0000 | [diff] [blame] | 32 | CTRL 0x1 - control reg. |
| 33 | Resets all the registers. |
| 34 | HALF_CYC 0x4 - cycle reg. |
| 35 | Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK |
| 36 | units). |
| 37 | I2C_HOLD 0x5 - hold reg. |
| 38 | OE (output enable) is delayed by value set to this register |
| 39 | (in LPC_CLK units) |
| 40 | CMD 0x6 - command reg. |
| 41 | Bit 0, 0 = write, 1 = read. |
| 42 | Bits [7:1] - the 7bit Address of the I2C device. |
| 43 | It should be written last as it triggers an I2C transaction. |
| 44 | NUM_DATA 0x7 - data size reg. |
| 45 | Number of data bytes to write in read transaction |
| 46 | NUM_ADDR 0x8 - address reg. |
| 47 | Number of address bytes to write in read transaction. |
| 48 | STATUS 0x9 - status reg. |
| 49 | Bit 0 - transaction is completed. |
| 50 | Bit 4 - ACK/NACK. |
| 51 | DATAx 0xa - 0x54 - 68 bytes data buffer regs. |
| 52 | For write transaction address is specified in four first bytes |
| 53 | (DATA1 - DATA4), data starting from DATA4. |
| 54 | For read transactions address is sent in a separate transaction and |
| 55 | specified in the four first bytes (DATA0 - DATA3). Data is read |
| 56 | starting from DATA0. |
| Mauro Carvalho Chehab | ccf988b | 2019-07-26 09:51:16 -0300 | [diff] [blame] | 57 | =============== === ======================================================================= |