blob: e7e020d4372a4cab2bf7b265712a4bd2a3dadde8 [file] [log] [blame]
Russell King96f60e32012-08-15 13:59:49 +01001/*
2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <drm/drmP.h>
Russell King98fb74f2015-06-15 10:17:57 +010010#include <drm/drm_plane_helper.h>
Russell King96f60e32012-08-15 13:59:49 +010011#include "armada_crtc.h"
12#include "armada_drm.h"
13#include "armada_fb.h"
14#include "armada_gem.h"
15#include "armada_hw.h"
16#include <drm/armada_drm.h>
17#include "armada_ioctlP.h"
18
Russell King28a2aeb2015-07-15 18:11:23 +010019struct armada_ovl_plane_properties {
Russell King96f60e32012-08-15 13:59:49 +010020 uint32_t colorkey_yr;
21 uint32_t colorkey_ug;
22 uint32_t colorkey_vb;
23#define K2R(val) (((val) >> 0) & 0xff)
24#define K2G(val) (((val) >> 8) & 0xff)
25#define K2B(val) (((val) >> 16) & 0xff)
26 int16_t brightness;
27 uint16_t contrast;
28 uint16_t saturation;
29 uint32_t colorkey_mode;
30};
31
Russell King28a2aeb2015-07-15 18:11:23 +010032struct armada_ovl_plane {
Russell King561f60b2015-07-15 18:11:24 +010033 struct armada_plane base;
Russell King96f60e32012-08-15 13:59:49 +010034 struct drm_framebuffer *old_fb;
35 uint32_t src_hw;
36 uint32_t dst_hw;
37 uint32_t dst_yx;
38 uint32_t ctrl0;
39 struct {
40 struct armada_vbl_event update;
41 struct armada_regs regs[13];
42 wait_queue_head_t wait;
43 } vbl;
Russell King28a2aeb2015-07-15 18:11:23 +010044 struct armada_ovl_plane_properties prop;
Russell King96f60e32012-08-15 13:59:49 +010045};
Russell King561f60b2015-07-15 18:11:24 +010046#define drm_to_armada_ovl_plane(p) \
47 container_of(p, struct armada_ovl_plane, base.base)
Russell King96f60e32012-08-15 13:59:49 +010048
49
50static void
Russell King28a2aeb2015-07-15 18:11:23 +010051armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
Russell King96f60e32012-08-15 13:59:49 +010052 struct armada_crtc *dcrtc)
53{
54 writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
55 writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
56 writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
57
58 writel_relaxed(prop->brightness << 16 | prop->contrast,
59 dcrtc->base + LCD_SPU_CONTRAST);
60 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
61 writel_relaxed(prop->saturation << 16,
62 dcrtc->base + LCD_SPU_SATURATION);
63 writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
64
65 spin_lock_irq(&dcrtc->irq_lock);
66 armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
67 CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
68 dcrtc->base + LCD_SPU_DMA_CTRL1);
69
70 armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
71 spin_unlock_irq(&dcrtc->irq_lock);
72}
73
Russell Kingfecfdb22015-07-15 18:11:24 +010074static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane,
75 struct drm_framebuffer *fb)
76{
77 struct drm_framebuffer *old_fb;
78
Russell King66377ef2015-07-15 18:11:24 +010079 old_fb = xchg(&dplane->old_fb, fb);
Russell Kingfecfdb22015-07-15 18:11:24 +010080
81 if (old_fb)
Russell King561f60b2015-07-15 18:11:24 +010082 armada_drm_queue_unref_work(dplane->base.base.dev, old_fb);
Russell Kingfecfdb22015-07-15 18:11:24 +010083}
84
Russell King96f60e32012-08-15 13:59:49 +010085/* === Plane support === */
Russell King28a2aeb2015-07-15 18:11:23 +010086static void armada_ovl_plane_vbl(struct armada_crtc *dcrtc, void *data)
Russell King96f60e32012-08-15 13:59:49 +010087{
Russell King28a2aeb2015-07-15 18:11:23 +010088 struct armada_ovl_plane *dplane = data;
Russell King96f60e32012-08-15 13:59:49 +010089
90 armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
Russell Kingfecfdb22015-07-15 18:11:24 +010091 armada_ovl_retire_fb(dplane, NULL);
Russell King070f3f62015-06-15 10:13:29 +010092
93 wake_up(&dplane->vbl.wait);
Russell King96f60e32012-08-15 13:59:49 +010094}
95
Russell King96f60e32012-08-15 13:59:49 +010096static int
Russell King28a2aeb2015-07-15 18:11:23 +010097armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
Russell King96f60e32012-08-15 13:59:49 +010098 struct drm_framebuffer *fb,
99 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
100 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
101{
Russell King28a2aeb2015-07-15 18:11:23 +0100102 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100103 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
Russell King98fb74f2015-06-15 10:17:57 +0100104 struct drm_rect src = {
105 .x1 = src_x,
106 .y1 = src_y,
107 .x2 = src_x + src_w,
108 .y2 = src_y + src_h,
109 };
110 struct drm_rect dest = {
111 .x1 = crtc_x,
112 .y1 = crtc_y,
113 .x2 = crtc_x + crtc_w,
114 .y2 = crtc_y + crtc_h,
115 };
116 const struct drm_rect clip = {
117 .x2 = crtc->mode.hdisplay,
118 .y2 = crtc->mode.vdisplay,
119 };
Russell King96f60e32012-08-15 13:59:49 +0100120 uint32_t val, ctrl0;
121 unsigned idx = 0;
Russell King98fb74f2015-06-15 10:17:57 +0100122 bool visible;
Russell King96f60e32012-08-15 13:59:49 +0100123 int ret;
124
Russell King98fb74f2015-06-15 10:17:57 +0100125 ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
126 0, INT_MAX, true, false, &visible);
127 if (ret)
128 return ret;
129
Russell King96f60e32012-08-15 13:59:49 +0100130 ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
131 CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
132 CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
133
134 /* Does the position/size result in nothing to display? */
Russell King98fb74f2015-06-15 10:17:57 +0100135 if (!visible)
Russell King96f60e32012-08-15 13:59:49 +0100136 ctrl0 &= ~CFG_DMA_ENA;
Russell King96f60e32012-08-15 13:59:49 +0100137
138 if (!dcrtc->plane) {
139 dcrtc->plane = plane;
140 armada_ovl_update_attr(&dplane->prop, dcrtc);
141 }
142
143 /* FIXME: overlay on an interlaced display */
144 /* Just updating the position/size? */
145 if (plane->fb == fb && dplane->ctrl0 == ctrl0) {
Russell King98fb74f2015-06-15 10:17:57 +0100146 val = (drm_rect_height(&src) & 0xffff0000) |
147 drm_rect_width(&src) >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100148 dplane->src_hw = val;
149 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100150
151 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
Russell King96f60e32012-08-15 13:59:49 +0100152 dplane->dst_hw = val;
153 writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100154
155 val = dest.y1 << 16 | dest.x1;
Russell King96f60e32012-08-15 13:59:49 +0100156 dplane->dst_yx = val;
157 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100158
Russell King96f60e32012-08-15 13:59:49 +0100159 return 0;
160 } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) {
161 /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
162 armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
163 dcrtc->base + LCD_SPU_SRAM_PARA1);
164 }
165
Russell King070f3f62015-06-15 10:13:29 +0100166 wait_event_timeout(dplane->vbl.wait,
167 list_empty(&dplane->vbl.update.node),
168 HZ/25);
Russell King96f60e32012-08-15 13:59:49 +0100169
170 if (plane->fb != fb) {
171 struct armada_gem_object *obj = drm_fb_obj(fb);
Russell King73068ce2015-06-15 10:18:02 +0100172 uint32_t addr[3], pixel_format;
173 int i, num_planes, hsub;
Russell King96f60e32012-08-15 13:59:49 +0100174
175 /*
176 * Take a reference on the new framebuffer - we want to
177 * hold on to it while the hardware is displaying it.
178 */
179 drm_framebuffer_reference(fb);
180
Russell Kingfecfdb22015-07-15 18:11:24 +0100181 if (plane->fb)
182 armada_ovl_retire_fb(dplane, plane->fb);
Russell King96f60e32012-08-15 13:59:49 +0100183
Russell King98fb74f2015-06-15 10:17:57 +0100184 src_y = src.y1 >> 16;
185 src_x = src.x1 >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100186
Russell King73068ce2015-06-15 10:18:02 +0100187 pixel_format = fb->pixel_format;
188 hsub = drm_format_horz_chroma_subsampling(pixel_format);
189 num_planes = drm_format_num_planes(pixel_format);
190
191 /*
192 * Annoyingly, shifting a YUYV-format image by one pixel
193 * causes the U/V planes to toggle. Toggle the UV swap.
194 * (Unfortunately, this causes momentary colour flickering.)
195 */
196 if (src_x & (hsub - 1) && num_planes == 1)
197 ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
198
199 for (i = 0; i < num_planes; i++)
200 addr[i] = obj->dev_addr + fb->offsets[i] +
201 src_y * fb->pitches[i] +
202 src_x * drm_format_plane_cpp(pixel_format, i);
203 for (; i < ARRAY_SIZE(addr); i++)
204 addr[i] = 0;
205
206 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
Russell King96f60e32012-08-15 13:59:49 +0100207 LCD_SPU_DMA_START_ADDR_Y0);
Russell King73068ce2015-06-15 10:18:02 +0100208 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
Russell King96f60e32012-08-15 13:59:49 +0100209 LCD_SPU_DMA_START_ADDR_U0);
Russell King73068ce2015-06-15 10:18:02 +0100210 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
Russell King96f60e32012-08-15 13:59:49 +0100211 LCD_SPU_DMA_START_ADDR_V0);
Russell King73068ce2015-06-15 10:18:02 +0100212 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
Russell King96f60e32012-08-15 13:59:49 +0100213 LCD_SPU_DMA_START_ADDR_Y1);
Russell King73068ce2015-06-15 10:18:02 +0100214 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
Russell King96f60e32012-08-15 13:59:49 +0100215 LCD_SPU_DMA_START_ADDR_U1);
Russell King73068ce2015-06-15 10:18:02 +0100216 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
Russell King96f60e32012-08-15 13:59:49 +0100217 LCD_SPU_DMA_START_ADDR_V1);
218
219 val = fb->pitches[0] << 16 | fb->pitches[0];
220 armada_reg_queue_set(dplane->vbl.regs, idx, val,
221 LCD_SPU_DMA_PITCH_YC);
222 val = fb->pitches[1] << 16 | fb->pitches[2];
223 armada_reg_queue_set(dplane->vbl.regs, idx, val,
224 LCD_SPU_DMA_PITCH_UV);
225 }
226
Russell King98fb74f2015-06-15 10:17:57 +0100227 val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100228 if (dplane->src_hw != val) {
229 dplane->src_hw = val;
230 armada_reg_queue_set(dplane->vbl.regs, idx, val,
231 LCD_SPU_DMA_HPXL_VLN);
232 }
Russell King98fb74f2015-06-15 10:17:57 +0100233
234 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
Russell King96f60e32012-08-15 13:59:49 +0100235 if (dplane->dst_hw != val) {
236 dplane->dst_hw = val;
237 armada_reg_queue_set(dplane->vbl.regs, idx, val,
238 LCD_SPU_DZM_HPXL_VLN);
239 }
Russell King98fb74f2015-06-15 10:17:57 +0100240
241 val = dest.y1 << 16 | dest.x1;
Russell King96f60e32012-08-15 13:59:49 +0100242 if (dplane->dst_yx != val) {
243 dplane->dst_yx = val;
244 armada_reg_queue_set(dplane->vbl.regs, idx, val,
245 LCD_SPU_DMA_OVSA_HPXL_VLN);
246 }
Russell King98fb74f2015-06-15 10:17:57 +0100247
Russell King96f60e32012-08-15 13:59:49 +0100248 if (dplane->ctrl0 != ctrl0) {
249 dplane->ctrl0 = ctrl0;
250 armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
251 CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
252 CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
253 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
254 CFG_YUV2RGB) | CFG_DMA_ENA,
255 LCD_SPU_DMA_CTRL0);
256 }
257 if (idx) {
258 armada_reg_queue_end(dplane->vbl.regs, idx);
259 armada_drm_vbl_event_add(dcrtc, &dplane->vbl.update);
260 }
261 return 0;
262}
263
Russell King28a2aeb2015-07-15 18:11:23 +0100264static int armada_ovl_plane_disable(struct drm_plane *plane)
Russell King96f60e32012-08-15 13:59:49 +0100265{
Russell King28a2aeb2015-07-15 18:11:23 +0100266 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100267 struct drm_framebuffer *fb;
268 struct armada_crtc *dcrtc;
269
Russell King561f60b2015-07-15 18:11:24 +0100270 if (!dplane->base.base.crtc)
Russell King96f60e32012-08-15 13:59:49 +0100271 return 0;
272
Russell King561f60b2015-07-15 18:11:24 +0100273 dcrtc = drm_to_armada_crtc(dplane->base.base.crtc);
Russell King96f60e32012-08-15 13:59:49 +0100274 dcrtc->plane = NULL;
275
276 spin_lock_irq(&dcrtc->irq_lock);
277 armada_drm_vbl_event_remove(dcrtc, &dplane->vbl.update);
Russell King96f60e32012-08-15 13:59:49 +0100278 spin_unlock_irq(&dcrtc->irq_lock);
279
Russell King5c8752c2015-07-15 18:11:25 +0100280 dplane->ctrl0 = 0;
281
Russell King58326802015-07-15 18:11:25 +0100282 armada_drm_crtc_plane_disable(dcrtc, plane);
Russell King96f60e32012-08-15 13:59:49 +0100283
Russell King66377ef2015-07-15 18:11:24 +0100284 fb = xchg(&dplane->old_fb, NULL);
Russell King96f60e32012-08-15 13:59:49 +0100285 if (fb)
286 drm_framebuffer_unreference(fb);
287
288 return 0;
289}
290
Russell King28a2aeb2015-07-15 18:11:23 +0100291static void armada_ovl_plane_destroy(struct drm_plane *plane)
Russell King96f60e32012-08-15 13:59:49 +0100292{
Russell King28a2aeb2015-07-15 18:11:23 +0100293 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King41dbb2d2015-06-15 10:13:30 +0100294
295 drm_plane_cleanup(plane);
296
297 kfree(dplane);
Russell King96f60e32012-08-15 13:59:49 +0100298}
299
Russell King28a2aeb2015-07-15 18:11:23 +0100300static int armada_ovl_plane_set_property(struct drm_plane *plane,
Russell King96f60e32012-08-15 13:59:49 +0100301 struct drm_property *property, uint64_t val)
302{
303 struct armada_private *priv = plane->dev->dev_private;
Russell King28a2aeb2015-07-15 18:11:23 +0100304 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100305 bool update_attr = false;
306
307 if (property == priv->colorkey_prop) {
308#define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
309 dplane->prop.colorkey_yr = CCC(K2R(val));
310 dplane->prop.colorkey_ug = CCC(K2G(val));
311 dplane->prop.colorkey_vb = CCC(K2B(val));
312#undef CCC
313 update_attr = true;
314 } else if (property == priv->colorkey_min_prop) {
315 dplane->prop.colorkey_yr &= ~0x00ff0000;
316 dplane->prop.colorkey_yr |= K2R(val) << 16;
317 dplane->prop.colorkey_ug &= ~0x00ff0000;
318 dplane->prop.colorkey_ug |= K2G(val) << 16;
319 dplane->prop.colorkey_vb &= ~0x00ff0000;
320 dplane->prop.colorkey_vb |= K2B(val) << 16;
321 update_attr = true;
322 } else if (property == priv->colorkey_max_prop) {
323 dplane->prop.colorkey_yr &= ~0xff000000;
324 dplane->prop.colorkey_yr |= K2R(val) << 24;
325 dplane->prop.colorkey_ug &= ~0xff000000;
326 dplane->prop.colorkey_ug |= K2G(val) << 24;
327 dplane->prop.colorkey_vb &= ~0xff000000;
328 dplane->prop.colorkey_vb |= K2B(val) << 24;
329 update_attr = true;
330 } else if (property == priv->colorkey_val_prop) {
331 dplane->prop.colorkey_yr &= ~0x0000ff00;
332 dplane->prop.colorkey_yr |= K2R(val) << 8;
333 dplane->prop.colorkey_ug &= ~0x0000ff00;
334 dplane->prop.colorkey_ug |= K2G(val) << 8;
335 dplane->prop.colorkey_vb &= ~0x0000ff00;
336 dplane->prop.colorkey_vb |= K2B(val) << 8;
337 update_attr = true;
338 } else if (property == priv->colorkey_alpha_prop) {
339 dplane->prop.colorkey_yr &= ~0x000000ff;
340 dplane->prop.colorkey_yr |= K2R(val);
341 dplane->prop.colorkey_ug &= ~0x000000ff;
342 dplane->prop.colorkey_ug |= K2G(val);
343 dplane->prop.colorkey_vb &= ~0x000000ff;
344 dplane->prop.colorkey_vb |= K2B(val);
345 update_attr = true;
346 } else if (property == priv->colorkey_mode_prop) {
347 dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
348 dplane->prop.colorkey_mode |= CFG_CKMODE(val);
349 update_attr = true;
350 } else if (property == priv->brightness_prop) {
351 dplane->prop.brightness = val - 256;
352 update_attr = true;
353 } else if (property == priv->contrast_prop) {
354 dplane->prop.contrast = val;
355 update_attr = true;
356 } else if (property == priv->saturation_prop) {
357 dplane->prop.saturation = val;
358 update_attr = true;
359 }
360
Russell King561f60b2015-07-15 18:11:24 +0100361 if (update_attr && dplane->base.base.crtc)
Russell King96f60e32012-08-15 13:59:49 +0100362 armada_ovl_update_attr(&dplane->prop,
Russell King561f60b2015-07-15 18:11:24 +0100363 drm_to_armada_crtc(dplane->base.base.crtc));
Russell King96f60e32012-08-15 13:59:49 +0100364
365 return 0;
366}
367
Russell King28a2aeb2015-07-15 18:11:23 +0100368static const struct drm_plane_funcs armada_ovl_plane_funcs = {
369 .update_plane = armada_ovl_plane_update,
370 .disable_plane = armada_ovl_plane_disable,
371 .destroy = armada_ovl_plane_destroy,
372 .set_property = armada_ovl_plane_set_property,
Russell King96f60e32012-08-15 13:59:49 +0100373};
374
Russell King28a2aeb2015-07-15 18:11:23 +0100375static const uint32_t armada_ovl_formats[] = {
Russell King96f60e32012-08-15 13:59:49 +0100376 DRM_FORMAT_UYVY,
377 DRM_FORMAT_YUYV,
378 DRM_FORMAT_YUV420,
379 DRM_FORMAT_YVU420,
380 DRM_FORMAT_YUV422,
381 DRM_FORMAT_YVU422,
382 DRM_FORMAT_VYUY,
383 DRM_FORMAT_YVYU,
384 DRM_FORMAT_ARGB8888,
385 DRM_FORMAT_ABGR8888,
386 DRM_FORMAT_XRGB8888,
387 DRM_FORMAT_XBGR8888,
388 DRM_FORMAT_RGB888,
389 DRM_FORMAT_BGR888,
390 DRM_FORMAT_ARGB1555,
391 DRM_FORMAT_ABGR1555,
392 DRM_FORMAT_RGB565,
393 DRM_FORMAT_BGR565,
394};
395
396static struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
397 { CKMODE_DISABLE, "disabled" },
398 { CKMODE_Y, "Y component" },
399 { CKMODE_U, "U component" },
400 { CKMODE_V, "V component" },
401 { CKMODE_RGB, "RGB" },
402 { CKMODE_R, "R component" },
403 { CKMODE_G, "G component" },
404 { CKMODE_B, "B component" },
405};
406
407static int armada_overlay_create_properties(struct drm_device *dev)
408{
409 struct armada_private *priv = dev->dev_private;
410
411 if (priv->colorkey_prop)
412 return 0;
413
414 priv->colorkey_prop = drm_property_create_range(dev, 0,
415 "colorkey", 0, 0xffffff);
416 priv->colorkey_min_prop = drm_property_create_range(dev, 0,
417 "colorkey_min", 0, 0xffffff);
418 priv->colorkey_max_prop = drm_property_create_range(dev, 0,
419 "colorkey_max", 0, 0xffffff);
420 priv->colorkey_val_prop = drm_property_create_range(dev, 0,
421 "colorkey_val", 0, 0xffffff);
422 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
423 "colorkey_alpha", 0, 0xffffff);
424 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
425 "colorkey_mode",
426 armada_drm_colorkey_enum_list,
427 ARRAY_SIZE(armada_drm_colorkey_enum_list));
428 priv->brightness_prop = drm_property_create_range(dev, 0,
429 "brightness", 0, 256 + 255);
430 priv->contrast_prop = drm_property_create_range(dev, 0,
431 "contrast", 0, 0x7fff);
432 priv->saturation_prop = drm_property_create_range(dev, 0,
433 "saturation", 0, 0x7fff);
434
435 if (!priv->colorkey_prop)
436 return -ENOMEM;
437
438 return 0;
439}
440
441int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
442{
443 struct armada_private *priv = dev->dev_private;
444 struct drm_mode_object *mobj;
Russell King28a2aeb2015-07-15 18:11:23 +0100445 struct armada_ovl_plane *dplane;
Russell King96f60e32012-08-15 13:59:49 +0100446 int ret;
447
448 ret = armada_overlay_create_properties(dev);
449 if (ret)
450 return ret;
451
452 dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
453 if (!dplane)
454 return -ENOMEM;
455
Russell King96f60e32012-08-15 13:59:49 +0100456 init_waitqueue_head(&dplane->vbl.wait);
Russell King28a2aeb2015-07-15 18:11:23 +0100457 armada_drm_vbl_event_init(&dplane->vbl.update, armada_ovl_plane_vbl,
Russell King96f60e32012-08-15 13:59:49 +0100458 dplane);
459
Russell King561f60b2015-07-15 18:11:24 +0100460 ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
Russell Kingd563c242015-07-15 18:11:24 +0100461 &armada_ovl_plane_funcs,
462 armada_ovl_formats,
463 ARRAY_SIZE(armada_ovl_formats),
464 DRM_PLANE_TYPE_OVERLAY);
Russell King28a2aeb2015-07-15 18:11:23 +0100465 if (ret) {
466 kfree(dplane);
467 return ret;
468 }
Russell King96f60e32012-08-15 13:59:49 +0100469
470 dplane->prop.colorkey_yr = 0xfefefe00;
471 dplane->prop.colorkey_ug = 0x01010100;
472 dplane->prop.colorkey_vb = 0x01010100;
473 dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
474 dplane->prop.brightness = 0;
475 dplane->prop.contrast = 0x4000;
476 dplane->prop.saturation = 0x4000;
477
Russell King561f60b2015-07-15 18:11:24 +0100478 mobj = &dplane->base.base.base;
Russell King96f60e32012-08-15 13:59:49 +0100479 drm_object_attach_property(mobj, priv->colorkey_prop,
480 0x0101fe);
481 drm_object_attach_property(mobj, priv->colorkey_min_prop,
482 0x0101fe);
483 drm_object_attach_property(mobj, priv->colorkey_max_prop,
484 0x0101fe);
485 drm_object_attach_property(mobj, priv->colorkey_val_prop,
486 0x0101fe);
487 drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
488 0x000000);
489 drm_object_attach_property(mobj, priv->colorkey_mode_prop,
490 CKMODE_RGB);
491 drm_object_attach_property(mobj, priv->brightness_prop, 256);
492 drm_object_attach_property(mobj, priv->contrast_prop,
493 dplane->prop.contrast);
494 drm_object_attach_property(mobj, priv->saturation_prop,
495 dplane->prop.saturation);
496
497 return 0;
498}