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Leilk Liu0d850e72015-08-07 15:19:49 +08001Binding for MTK SPI controller
2
3Required properties:
4- compatible: should be one of the following.
Leilk Liu5c5e09f2015-12-31 10:59:03 +08005 - mediatek,mt2701-spi: for mt2701 platforms
Leilk Liu0d850e72015-08-07 15:19:49 +08006 - mediatek,mt6589-spi: for mt6589 platforms
Leilk Liu5c5e09f2015-12-31 10:59:03 +08007 - mediatek,mt8135-spi: for mt8135 platforms
8 - mediatek,mt8173-spi: for mt8173 platforms
Leilk Liu0d850e72015-08-07 15:19:49 +08009
10- #address-cells: should be 1.
11
12- #size-cells: should be 0.
13
14- reg: Address and length of the register set for the device
15
16- interrupts: Should contain spi interrupt
17
18- clocks: phandles to input clocks.
Leilk Liu3d4fe182015-08-31 21:18:58 +080019 The first should be one of the following. It's PLL.
Leilk Liu0d850e72015-08-07 15:19:49 +080020 - <&clk26m>: specify parent clock 26MHZ.
21 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
22 It's the default one.
23 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
24 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
25 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
Leilk Liu3d4fe182015-08-31 21:18:58 +080026 The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
27 The third is <&pericfg CLK_PERI_SPI0>. It's clock gate.
Leilk Liu0d850e72015-08-07 15:19:49 +080028
Leilk Liu3d4fe182015-08-31 21:18:58 +080029- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
30 muxes clock, and "spi-clk" for the clock gate.
Leilk Liu0d850e72015-08-07 15:19:49 +080031
32Optional properties:
leilk.liu@mediatek.com6e6a9cd42015-11-20 10:21:17 +080033-cs-gpios: see spi-bus.txt.
Leilk Liueca3a1e2015-10-26 16:09:41 +080034
Leilk Liu0d850e72015-08-07 15:19:49 +080035- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
leilk.liu@mediatek.comfbdb5d72015-11-20 10:21:16 +080036 controller used. This is an array, the element value should be 0~3,
Leilk Liueca3a1e2015-10-26 16:09:41 +080037 only required for MT8173.
Leilk Liu0d850e72015-08-07 15:19:49 +080038 0: specify GPIO69,70,71,72 for spi pins.
39 1: specify GPIO102,103,104,105 for spi pins.
40 2: specify GPIO128,129,130,131 for spi pins.
41 3: specify GPIO5,6,7,8 for spi pins.
42
43Example:
44
45- SoC Specific Portion:
46spi: spi@1100a000 {
47 compatible = "mediatek,mt8173-spi";
48 #address-cells = <1>;
49 #size-cells = <0>;
50 reg = <0 0x1100a000 0 0x1000>;
51 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
Leilk Liu3d4fe182015-08-31 21:18:58 +080052 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
53 <&topckgen CLK_TOP_SPI_SEL>,
54 <&pericfg CLK_PERI_SPI0>;
55 clock-names = "parent-clk", "sel-clk", "spi-clk";
Leilk Liueca3a1e2015-10-26 16:09:41 +080056 cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
57 mediatek,pad-select = <1>, <0>;
Leilk Liu0d850e72015-08-07 15:19:49 +080058 status = "disabled";
59};