Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 1 | Binding for MTK SPI controller |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible: should be one of the following. |
Leilk Liu | 5c5e09f | 2015-12-31 10:59:03 +0800 | [diff] [blame^] | 5 | - mediatek,mt2701-spi: for mt2701 platforms |
Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 6 | - mediatek,mt6589-spi: for mt6589 platforms |
Leilk Liu | 5c5e09f | 2015-12-31 10:59:03 +0800 | [diff] [blame^] | 7 | - mediatek,mt8135-spi: for mt8135 platforms |
| 8 | - mediatek,mt8173-spi: for mt8173 platforms |
Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 9 | |
| 10 | - #address-cells: should be 1. |
| 11 | |
| 12 | - #size-cells: should be 0. |
| 13 | |
| 14 | - reg: Address and length of the register set for the device |
| 15 | |
| 16 | - interrupts: Should contain spi interrupt |
| 17 | |
| 18 | - clocks: phandles to input clocks. |
Leilk Liu | 3d4fe18 | 2015-08-31 21:18:58 +0800 | [diff] [blame] | 19 | The first should be one of the following. It's PLL. |
Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 20 | - <&clk26m>: specify parent clock 26MHZ. |
| 21 | - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ. |
| 22 | It's the default one. |
| 23 | - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ. |
| 24 | - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. |
| 25 | - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. |
Leilk Liu | 3d4fe18 | 2015-08-31 21:18:58 +0800 | [diff] [blame] | 26 | The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux. |
| 27 | The third is <&pericfg CLK_PERI_SPI0>. It's clock gate. |
Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 28 | |
Leilk Liu | 3d4fe18 | 2015-08-31 21:18:58 +0800 | [diff] [blame] | 29 | - clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the |
| 30 | muxes clock, and "spi-clk" for the clock gate. |
Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 31 | |
| 32 | Optional properties: |
leilk.liu@mediatek.com | 6e6a9cd4 | 2015-11-20 10:21:17 +0800 | [diff] [blame] | 33 | -cs-gpios: see spi-bus.txt. |
Leilk Liu | eca3a1e | 2015-10-26 16:09:41 +0800 | [diff] [blame] | 34 | |
Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 35 | - mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi |
leilk.liu@mediatek.com | fbdb5d7 | 2015-11-20 10:21:16 +0800 | [diff] [blame] | 36 | controller used. This is an array, the element value should be 0~3, |
Leilk Liu | eca3a1e | 2015-10-26 16:09:41 +0800 | [diff] [blame] | 37 | only required for MT8173. |
Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 38 | 0: specify GPIO69,70,71,72 for spi pins. |
| 39 | 1: specify GPIO102,103,104,105 for spi pins. |
| 40 | 2: specify GPIO128,129,130,131 for spi pins. |
| 41 | 3: specify GPIO5,6,7,8 for spi pins. |
| 42 | |
| 43 | Example: |
| 44 | |
| 45 | - SoC Specific Portion: |
| 46 | spi: spi@1100a000 { |
| 47 | compatible = "mediatek,mt8173-spi"; |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <0>; |
| 50 | reg = <0 0x1100a000 0 0x1000>; |
| 51 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; |
Leilk Liu | 3d4fe18 | 2015-08-31 21:18:58 +0800 | [diff] [blame] | 52 | clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, |
| 53 | <&topckgen CLK_TOP_SPI_SEL>, |
| 54 | <&pericfg CLK_PERI_SPI0>; |
| 55 | clock-names = "parent-clk", "sel-clk", "spi-clk"; |
Leilk Liu | eca3a1e | 2015-10-26 16:09:41 +0800 | [diff] [blame] | 56 | cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; |
| 57 | mediatek,pad-select = <1>, <0>; |
Leilk Liu | 0d850e7 | 2015-08-07 15:19:49 +0800 | [diff] [blame] | 58 | status = "disabled"; |
| 59 | }; |