Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 MediaTek Inc. |
| 3 | * Author: Shunli Wang <shunli.wang@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/clk-provider.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | |
| 18 | #include "clk-mtk.h" |
| 19 | #include "clk-gate.h" |
| 20 | |
| 21 | #include <dt-bindings/clock/mt2701-clk.h> |
| 22 | |
| 23 | static const struct mtk_gate_regs eth_cg_regs = { |
| 24 | .sta_ofs = 0x0030, |
| 25 | }; |
| 26 | |
| 27 | #define GATE_ETH(_id, _name, _parent, _shift) { \ |
| 28 | .id = _id, \ |
| 29 | .name = _name, \ |
| 30 | .parent_name = _parent, \ |
| 31 | .regs = ð_cg_regs, \ |
| 32 | .shift = _shift, \ |
| 33 | .ops = &mtk_clk_gate_ops_no_setclr_inv, \ |
| 34 | } |
| 35 | |
| 36 | static const struct mtk_gate eth_clks[] = { |
| 37 | GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), |
| 38 | GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), |
| 39 | GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), |
| 40 | GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8), |
| 41 | GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11), |
| 42 | GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14), |
| 43 | GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17), |
| 44 | GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), |
| 45 | }; |
| 46 | |
| 47 | static const struct of_device_id of_match_clk_mt2701_eth[] = { |
| 48 | { .compatible = "mediatek,mt2701-ethsys", }, |
| 49 | {} |
| 50 | }; |
| 51 | |
| 52 | static int clk_mt2701_eth_probe(struct platform_device *pdev) |
| 53 | { |
| 54 | struct clk_onecell_data *clk_data; |
| 55 | int r; |
| 56 | struct device_node *node = pdev->dev.of_node; |
| 57 | |
| 58 | clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); |
| 59 | |
| 60 | mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), |
| 61 | clk_data); |
| 62 | |
| 63 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 64 | if (r) |
| 65 | dev_err(&pdev->dev, |
| 66 | "could not register clock provider: %s: %d\n", |
| 67 | pdev->name, r); |
| 68 | |
John Crispin | db9c4a1 | 2017-01-23 13:48:26 +0100 | [diff] [blame] | 69 | mtk_register_reset_controller(node, 1, 0x34); |
| 70 | |
Shunli Wang | e986211 | 2016-11-04 15:43:05 +0800 | [diff] [blame] | 71 | return r; |
| 72 | } |
| 73 | |
| 74 | static struct platform_driver clk_mt2701_eth_drv = { |
| 75 | .probe = clk_mt2701_eth_probe, |
| 76 | .driver = { |
| 77 | .name = "clk-mt2701-eth", |
| 78 | .of_match_table = of_match_clk_mt2701_eth, |
| 79 | }, |
| 80 | }; |
| 81 | |
| 82 | builtin_platform_driver(clk_mt2701_eth_drv); |