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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 54479449c801e46ee2b6ba08e2f19cd810f74f94 / . / drivers / clk / rockchip / clk-rk3399.c
blob: 6f3d0a60d6cd283ba42e5f690cf309b888b7078c [file] [log] [blame]
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1/*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <dt-bindings/clock/rk3399-cru.h>
22#include "clk.h"
23
24enum rk3399_plls {
25 lpll, bpll, dpll, cpll, gpll, npll, vpll,
26};
27
28enum rk3399_pmu_plls {
29 ppll,
30};
31
32static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
80 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
Xing Zhengaa2897c2016-04-20 19:06:50 +0800[diff] [blame]95 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]96 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
97 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
98 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
99 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
Xing Zhengaa2897c2016-04-20 19:06:50 +0800[diff] [blame]100 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]101 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
Xing Zhengaa2897c2016-04-20 19:06:50 +0800[diff] [blame]102 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
Xing Zhengefc4204c2016-08-02 15:22:26 +0800[diff] [blame]103 RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]104 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
Xing Zhengaa2897c2016-04-20 19:06:50 +0800[diff] [blame]105 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
Xing Zhengefc4204c2016-08-02 15:22:26 +0800[diff] [blame]106 RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
Xing Zhengaa2897c2016-04-20 19:06:50 +0800[diff] [blame]107 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
108 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]109 { /* sentinel */ },
110};
111
112/* CRU parents */
113PNAME(mux_pll_p) = { "xin24m", "xin32k" };
114
115PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
116 "clk_core_l_bpll_src",
117 "clk_core_l_dpll_src",
118 "clk_core_l_gpll_src" };
119PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
120 "clk_core_b_bpll_src",
121 "clk_core_b_dpll_src",
122 "clk_core_b_gpll_src" };
123PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
124 "gpll_aclk_cci_src",
125 "npll_aclk_cci_src",
126 "vpll_aclk_cci_src" };
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]127PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
128 "gpll_cci_trace" };
129PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
130 "npll_cs"};
131PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
132 "gpll_aclk_perihp_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]133
134PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
135PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
136PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
137PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
138PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]139PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
140 "ppll" };
141PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
142 "xin24m" };
143PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
144 "clk_usbphy_480m" };
145PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
146 "npll", "upll" };
147PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
148 "upll", "xin24m" };
149PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
150 "ppll", "upll", "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]151
152PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]153PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
154 "npll" };
155PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
156 "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]157
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]158PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
159 "dclk_vop0_frac" };
160PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
161 "dclk_vop1_frac" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]162
Xing Zhengfd8bc822016-04-20 19:11:32 +0800[diff] [blame]163PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]164
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]165PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
166PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
167PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
168 "cpll", "gpll" };
169PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
170 "clk_pcie_core_phy" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]171
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]172PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
173 "gpll_aclk_emmc_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]174
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]175PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
176 "gpll_aclk_perilp0_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]177
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]178PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
179 "gpll_fclk_cm0s_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]180
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]181PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
182 "gpll_hclk_perilp1_src" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]183
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]184PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
185PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]186
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]187PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
188 "clk_usbphy1_480m_src" };
189PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
190 "gpll_aclk_gmac_src" };
191PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
192PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
193 "clkin_i2s", "xin12m" };
194PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
195 "clkin_i2s", "xin12m" };
196PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
197 "clkin_i2s", "xin12m" };
198PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
199 "clkin_i2s", "xin12m" };
200PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
201 "clk_i2s2" };
202PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]203
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]204PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
205PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
206PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
207PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]208
209/* PMU CRU parents */
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]210PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
211PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
212PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
213PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
214PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac",
215 "xin24m" };
216PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]217
218static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
219 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
220 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
221 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
222 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
223 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
224 RK3399_PLL_CON(19), 8, 31, 0, NULL),
225 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
226 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
227 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
228 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
229 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
230 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
231 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
232 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
233};
234
235static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
237 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
238};
239
240#define MFLAGS CLK_MUX_HIWORD_MASK
241#define DFLAGS CLK_DIVIDER_HIWORD_MASK
242#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
243#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
244
245static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
246 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
247 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
248
249static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
250 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
251 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
252
253static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
254 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
255 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
256
257static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
258 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
259 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
260
261static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
262 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
263 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
264
265static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
266 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
267 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
268
269static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
270 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
271 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
272
273static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
274 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
275 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
276
277static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
278 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
279 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
280
281static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
282 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
283 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
284
285static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
286 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
287 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
288
289static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
290 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
291 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
292
293static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
294 .core_reg = RK3399_CLKSEL_CON(0),
295 .div_core_shift = 0,
296 .div_core_mask = 0x1f,
297 .mux_core_alt = 3,
298 .mux_core_main = 0,
299 .mux_core_shift = 6,
300 .mux_core_mask = 0x3,
301};
302
303static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
304 .core_reg = RK3399_CLKSEL_CON(2),
305 .div_core_shift = 0,
306 .div_core_mask = 0x1f,
307 .mux_core_alt = 3,
308 .mux_core_main = 1,
309 .mux_core_shift = 6,
310 .mux_core_mask = 0x3,
311};
312
313#define RK3399_DIV_ACLKM_MASK 0x1f
314#define RK3399_DIV_ACLKM_SHIFT 8
315#define RK3399_DIV_ATCLK_MASK 0x1f
316#define RK3399_DIV_ATCLK_SHIFT 0
317#define RK3399_DIV_PCLK_DBG_MASK 0x1f
318#define RK3399_DIV_PCLK_DBG_SHIFT 8
319
320#define RK3399_CLKSEL0(_offs, _aclkm) \
321 { \
322 .reg = RK3399_CLKSEL_CON(0 + _offs), \
323 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
324 RK3399_DIV_ACLKM_SHIFT), \
325 }
326#define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
327 { \
328 .reg = RK3399_CLKSEL_CON(1 + _offs), \
329 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
330 RK3399_DIV_ATCLK_SHIFT) | \
331 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
332 RK3399_DIV_PCLK_DBG_SHIFT), \
333 }
334
335/* cluster_l: aclkm in clksel0, rest in clksel1 */
336#define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
337 { \
338 .prate = _prate##U, \
339 .divs = { \
340 RK3399_CLKSEL0(0, _aclkm), \
341 RK3399_CLKSEL1(0, _atclk, _pdbg), \
342 }, \
343 }
344
345/* cluster_b: aclkm in clksel2, rest in clksel3 */
346#define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
347 { \
348 .prate = _prate##U, \
349 .divs = { \
350 RK3399_CLKSEL0(2, _aclkm), \
351 RK3399_CLKSEL1(2, _atclk, _pdbg), \
352 }, \
353 }
354
355static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
356 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
357 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
358 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
359 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
360 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
361 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
362 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
363 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
364 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
365 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
366 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
367 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
368 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
Xing Zhengaa2897c2016-04-20 19:06:50 +0800[diff] [blame]369 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
370 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]371};
372
373static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
374 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
375 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
376 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
377 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
378 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
379 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
380 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
381 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
382 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
383 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
384 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
385 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
386 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
387 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
388 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
389 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
390 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
391 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
392 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
Xing Zhengaa2897c2016-04-20 19:06:50 +0800[diff] [blame]393 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
394 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]395};
396
397static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
398 /*
399 * CRU Clock-Architecture
400 */
401
402 /* usbphy */
403 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
404 RK3399_CLKGATE_CON(6), 5, GFLAGS),
405 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
406 RK3399_CLKGATE_CON(6), 6, GFLAGS),
407
408 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
409 RK3399_CLKGATE_CON(13), 12, GFLAGS),
410 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
411 RK3399_CLKGATE_CON(13), 12, GFLAGS),
412 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
413 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
414
415 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
416 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
417
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]418 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]419 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
420 RK3399_CLKGATE_CON(6), 4, GFLAGS),
421
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]422 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]423 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
424 RK3399_CLKGATE_CON(12), 0, GFLAGS),
425 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
426 RK3399_CLKGATE_CON(30), 0, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]427 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]428 RK3399_CLKGATE_CON(30), 1, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]429 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]430 RK3399_CLKGATE_CON(30), 2, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]431 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]432 RK3399_CLKGATE_CON(30), 3, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]433 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]434 RK3399_CLKGATE_CON(30), 4, GFLAGS),
435
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]436 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]437 RK3399_CLKGATE_CON(12), 1, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]438 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]439 RK3399_CLKGATE_CON(12), 2, GFLAGS),
440
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]441 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]442 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
443 RK3399_CLKGATE_CON(12), 3, GFLAGS),
444
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]445 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]446 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
447 RK3399_CLKGATE_CON(12), 4, GFLAGS),
448
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]449 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]450 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
451 RK3399_CLKGATE_CON(13), 4, GFLAGS),
452
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]453 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]454 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
455 RK3399_CLKGATE_CON(13), 5, GFLAGS),
456
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]457 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]458 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
459 RK3399_CLKGATE_CON(13), 6, GFLAGS),
460
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]461 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]462 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
463 RK3399_CLKGATE_CON(13), 7, GFLAGS),
464
465 /* little core */
466 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
467 RK3399_CLKGATE_CON(0), 0, GFLAGS),
468 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
469 RK3399_CLKGATE_CON(0), 1, GFLAGS),
470 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
471 RK3399_CLKGATE_CON(0), 2, GFLAGS),
472 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
473 RK3399_CLKGATE_CON(0), 3, GFLAGS),
474
475 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
476 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
477 RK3399_CLKGATE_CON(0), 4, GFLAGS),
478 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
479 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
480 RK3399_CLKGATE_CON(0), 5, GFLAGS),
481 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
482 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
483 RK3399_CLKGATE_CON(0), 6, GFLAGS),
484
485 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
486 RK3399_CLKGATE_CON(14), 12, GFLAGS),
487 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
488 RK3399_CLKGATE_CON(14), 13, GFLAGS),
489
490 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
491 RK3399_CLKGATE_CON(14), 9, GFLAGS),
492 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
493 RK3399_CLKGATE_CON(14), 10, GFLAGS),
494 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
495 RK3399_CLKGATE_CON(14), 11, GFLAGS),
496 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
497 RK3399_CLKGATE_CON(0), 7, GFLAGS),
498
499 /* big core */
500 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
501 RK3399_CLKGATE_CON(1), 0, GFLAGS),
502 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
503 RK3399_CLKGATE_CON(1), 1, GFLAGS),
504 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
505 RK3399_CLKGATE_CON(1), 2, GFLAGS),
506 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
507 RK3399_CLKGATE_CON(1), 3, GFLAGS),
508
509 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
510 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
511 RK3399_CLKGATE_CON(1), 4, GFLAGS),
512 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
513 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
514 RK3399_CLKGATE_CON(1), 5, GFLAGS),
515 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
516 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
517 RK3399_CLKGATE_CON(1), 6, GFLAGS),
518
519 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
520 RK3399_CLKGATE_CON(14), 5, GFLAGS),
521 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
522 RK3399_CLKGATE_CON(14), 6, GFLAGS),
523
524 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
525 RK3399_CLKGATE_CON(14), 1, GFLAGS),
526 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
527 RK3399_CLKGATE_CON(14), 3, GFLAGS),
528 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
529 RK3399_CLKGATE_CON(14), 4, GFLAGS),
530
531 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
532 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
533
534 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
535 RK3399_CLKGATE_CON(14), 2, GFLAGS),
536
537 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
538 RK3399_CLKGATE_CON(1), 7, GFLAGS),
539
540 /* gmac */
541 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
542 RK3399_CLKGATE_CON(6), 9, GFLAGS),
543 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
544 RK3399_CLKGATE_CON(6), 8, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]545 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]546 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
547 RK3399_CLKGATE_CON(6), 10, GFLAGS),
548
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]549 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]550 RK3399_CLKGATE_CON(32), 0, GFLAGS),
551 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
552 RK3399_CLKGATE_CON(32), 1, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]553 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]554 RK3399_CLKGATE_CON(32), 4, GFLAGS),
555
556 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
557 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
558 RK3399_CLKGATE_CON(6), 11, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]559 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]560 RK3399_CLKGATE_CON(32), 2, GFLAGS),
561 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
562 RK3399_CLKGATE_CON(32), 3, GFLAGS),
563
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]564 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]565 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
566 RK3399_CLKGATE_CON(5), 5, GFLAGS),
567
Xing Zheng3f92a052016-04-20 19:06:49 +0800[diff] [blame]568 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]569 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]570 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]571 RK3399_CLKGATE_CON(5), 6, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]572 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]573 RK3399_CLKGATE_CON(5), 7, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]574 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]575 RK3399_CLKGATE_CON(5), 8, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]576 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]577 RK3399_CLKGATE_CON(5), 9, GFLAGS),
578
579 /* spdif */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]580 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]581 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
582 RK3399_CLKGATE_CON(8), 13, GFLAGS),
583 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
584 RK3399_CLKSEL_CON(99), 0,
585 RK3399_CLKGATE_CON(8), 14, GFLAGS,
586 &rk3399_spdif_fracmux),
587 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
588 RK3399_CLKGATE_CON(8), 15, GFLAGS),
589
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]590 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
Xing Zheng37708212016-06-30 10:18:59 +0800[diff] [blame]591 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]592 RK3399_CLKGATE_CON(10), 6, GFLAGS),
593 /* i2s */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]594 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]595 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
596 RK3399_CLKGATE_CON(8), 3, GFLAGS),
597 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
598 RK3399_CLKSEL_CON(96), 0,
599 RK3399_CLKGATE_CON(8), 4, GFLAGS,
600 &rk3399_i2s0_fracmux),
601 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
602 RK3399_CLKGATE_CON(8), 5, GFLAGS),
603
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]604 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]605 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
606 RK3399_CLKGATE_CON(8), 6, GFLAGS),
607 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
608 RK3399_CLKSEL_CON(97), 0,
609 RK3399_CLKGATE_CON(8), 7, GFLAGS,
610 &rk3399_i2s1_fracmux),
611 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
612 RK3399_CLKGATE_CON(8), 8, GFLAGS),
613
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]614 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]615 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
616 RK3399_CLKGATE_CON(8), 9, GFLAGS),
617 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
618 RK3399_CLKSEL_CON(98), 0,
619 RK3399_CLKGATE_CON(8), 10, GFLAGS,
620 &rk3399_i2s2_fracmux),
621 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
622 RK3399_CLKGATE_CON(8), 11, GFLAGS),
623
624 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
625 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
626 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
627 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
628 RK3399_CLKGATE_CON(8), 12, GFLAGS),
629
630 /* uart */
631 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
632 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
633 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
634 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
635 RK3399_CLKGATE_CON(9), 0, GFLAGS),
636 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
637 RK3399_CLKSEL_CON(100), 0,
638 RK3399_CLKGATE_CON(9), 1, GFLAGS,
639 &rk3399_uart0_fracmux),
640
641 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
642 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
643 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
644 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
645 RK3399_CLKGATE_CON(9), 2, GFLAGS),
646 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
647 RK3399_CLKSEL_CON(101), 0,
648 RK3399_CLKGATE_CON(9), 3, GFLAGS,
649 &rk3399_uart1_fracmux),
650
651 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
652 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
653 RK3399_CLKGATE_CON(9), 4, GFLAGS),
654 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
655 RK3399_CLKSEL_CON(102), 0,
656 RK3399_CLKGATE_CON(9), 5, GFLAGS,
657 &rk3399_uart2_fracmux),
658
659 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
660 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
661 RK3399_CLKGATE_CON(9), 6, GFLAGS),
662 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
663 RK3399_CLKSEL_CON(103), 0,
664 RK3399_CLKGATE_CON(9), 7, GFLAGS,
665 &rk3399_uart3_fracmux),
666
667 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
668 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
669 RK3399_CLKGATE_CON(3), 4, GFLAGS),
670
671 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
672 RK3399_CLKGATE_CON(18), 10, GFLAGS),
673 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
674 RK3399_CLKGATE_CON(18), 12, GFLAGS),
675 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
676 RK3399_CLKGATE_CON(18), 15, GFLAGS),
677 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
678 RK3399_CLKGATE_CON(19), 2, GFLAGS),
679
680 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
681 RK3399_CLKGATE_CON(4), 11, GFLAGS),
682 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
683 RK3399_CLKGATE_CON(3), 5, GFLAGS),
684 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
685 RK3399_CLKGATE_CON(3), 6, GFLAGS),
686
687 /* cci */
688 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
689 RK3399_CLKGATE_CON(2), 0, GFLAGS),
690 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
691 RK3399_CLKGATE_CON(2), 1, GFLAGS),
692 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
693 RK3399_CLKGATE_CON(2), 2, GFLAGS),
694 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
695 RK3399_CLKGATE_CON(2), 3, GFLAGS),
696
697 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
698 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
699 RK3399_CLKGATE_CON(2), 4, GFLAGS),
700
701 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
702 RK3399_CLKGATE_CON(15), 0, GFLAGS),
703 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
704 RK3399_CLKGATE_CON(15), 1, GFLAGS),
705 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
706 RK3399_CLKGATE_CON(15), 2, GFLAGS),
707 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
708 RK3399_CLKGATE_CON(15), 3, GFLAGS),
709 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
710 RK3399_CLKGATE_CON(15), 4, GFLAGS),
711 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
712 RK3399_CLKGATE_CON(15), 7, GFLAGS),
713
714 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
715 RK3399_CLKGATE_CON(2), 5, GFLAGS),
716 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
717 RK3399_CLKGATE_CON(2), 6, GFLAGS),
718 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
719 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
720 RK3399_CLKGATE_CON(2), 7, GFLAGS),
721
722 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
723 RK3399_CLKGATE_CON(2), 8, GFLAGS),
724 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
725 RK3399_CLKGATE_CON(2), 9, GFLAGS),
726 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
727 RK3399_CLKGATE_CON(2), 10, GFLAGS),
728 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
729 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
730 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
731 RK3399_CLKGATE_CON(15), 5, GFLAGS),
732 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
733 RK3399_CLKGATE_CON(15), 6, GFLAGS),
734
735 /* vcodec */
736 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
737 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
738 RK3399_CLKGATE_CON(4), 0, GFLAGS),
739 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
740 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
741 RK3399_CLKGATE_CON(4), 1, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]742 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]743 RK3399_CLKGATE_CON(17), 2, GFLAGS),
744 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
745 RK3399_CLKGATE_CON(17), 3, GFLAGS),
746
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]747 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]748 RK3399_CLKGATE_CON(17), 0, GFLAGS),
749 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
750 RK3399_CLKGATE_CON(17), 1, GFLAGS),
751
752 /* vdu */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]753 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]754 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
755 RK3399_CLKGATE_CON(4), 4, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]756 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]757 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
758 RK3399_CLKGATE_CON(4), 5, GFLAGS),
759
760 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
761 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
762 RK3399_CLKGATE_CON(4), 2, GFLAGS),
763 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
764 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
765 RK3399_CLKGATE_CON(4), 3, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]766 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]767 RK3399_CLKGATE_CON(17), 10, GFLAGS),
768 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
769 RK3399_CLKGATE_CON(17), 11, GFLAGS),
770
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]771 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]772 RK3399_CLKGATE_CON(17), 8, GFLAGS),
773 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
774 RK3399_CLKGATE_CON(17), 9, GFLAGS),
775
776 /* iep */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]777 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]778 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
779 RK3399_CLKGATE_CON(4), 6, GFLAGS),
780 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
781 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
782 RK3399_CLKGATE_CON(4), 7, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]783 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]784 RK3399_CLKGATE_CON(16), 2, GFLAGS),
785 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
786 RK3399_CLKGATE_CON(16), 3, GFLAGS),
787
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]788 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]789 RK3399_CLKGATE_CON(16), 0, GFLAGS),
790 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
791 RK3399_CLKGATE_CON(16), 1, GFLAGS),
792
793 /* rga */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]794 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]795 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
796 RK3399_CLKGATE_CON(4), 10, GFLAGS),
797
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]798 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]799 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
800 RK3399_CLKGATE_CON(4), 8, GFLAGS),
801 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
802 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
803 RK3399_CLKGATE_CON(4), 9, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]804 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]805 RK3399_CLKGATE_CON(16), 10, GFLAGS),
806 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
807 RK3399_CLKGATE_CON(16), 11, GFLAGS),
808
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]809 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]810 RK3399_CLKGATE_CON(16), 8, GFLAGS),
811 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
812 RK3399_CLKGATE_CON(16), 9, GFLAGS),
813
814 /* center */
815 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
816 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
817 RK3399_CLKGATE_CON(3), 7, GFLAGS),
818 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
819 RK3399_CLKGATE_CON(19), 0, GFLAGS),
820 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
821 RK3399_CLKGATE_CON(19), 1, GFLAGS),
822
823 /* gpu */
824 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
825 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
826 RK3399_CLKGATE_CON(13), 0, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]827 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]828 RK3399_CLKGATE_CON(30), 8, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]829 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]830 RK3399_CLKGATE_CON(30), 10, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]831 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]832 RK3399_CLKGATE_CON(30), 11, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]833 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]834 RK3399_CLKGATE_CON(13), 1, GFLAGS),
835
836 /* perihp */
Xing Zheng3bd14ae2016-05-13 11:42:17 -0700[diff] [blame]837 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]838 RK3399_CLKGATE_CON(5), 0, GFLAGS),
Xing Zheng3bd14ae2016-05-13 11:42:17 -0700[diff] [blame]839 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]840 RK3399_CLKGATE_CON(5), 1, GFLAGS),
841 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
842 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
843 RK3399_CLKGATE_CON(5), 2, GFLAGS),
844 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
845 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
846 RK3399_CLKGATE_CON(5), 3, GFLAGS),
847 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
848 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
849 RK3399_CLKGATE_CON(5), 4, GFLAGS),
850
Elaine Zhang4f4e0492016-08-02 15:22:49 +0800[diff] [blame]851 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]852 RK3399_CLKGATE_CON(20), 2, GFLAGS),
Elaine Zhang4f4e0492016-08-02 15:22:49 +0800[diff] [blame]853 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]854 RK3399_CLKGATE_CON(20), 10, GFLAGS),
855 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
856 RK3399_CLKGATE_CON(20), 12, GFLAGS),
857
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]858 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]859 RK3399_CLKGATE_CON(20), 5, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]860 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]861 RK3399_CLKGATE_CON(20), 6, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]862 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]863 RK3399_CLKGATE_CON(20), 7, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]864 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]865 RK3399_CLKGATE_CON(20), 8, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]866 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]867 RK3399_CLKGATE_CON(20), 9, GFLAGS),
868 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
869 RK3399_CLKGATE_CON(20), 13, GFLAGS),
870 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
871 RK3399_CLKGATE_CON(20), 15, GFLAGS),
872
873 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
874 RK3399_CLKGATE_CON(20), 4, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]875 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]876 RK3399_CLKGATE_CON(20), 11, GFLAGS),
877 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
878 RK3399_CLKGATE_CON(20), 14, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]879 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]880 RK3399_CLKGATE_CON(31), 8, GFLAGS),
881
882 /* sdio & sdmmc */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]883 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]884 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
885 RK3399_CLKGATE_CON(12), 13, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]886 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]887 RK3399_CLKGATE_CON(33), 8, GFLAGS),
888 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
889 RK3399_CLKGATE_CON(33), 9, GFLAGS),
890
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]891 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]892 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
893 RK3399_CLKGATE_CON(6), 0, GFLAGS),
894
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]895 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]896 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
897 RK3399_CLKGATE_CON(6), 1, GFLAGS),
898
Douglas Anderson84752e82016-05-04 16:36:25 -0700[diff] [blame]899 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
900 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]901
902 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
903 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
904
905 /* pcie */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]906 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]907 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
908 RK3399_CLKGATE_CON(6), 2, GFLAGS),
909
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]910 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]911 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
912 RK3399_CLKGATE_CON(12), 6, GFLAGS),
913 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
914 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
915
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]916 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]917 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
918 RK3399_CLKGATE_CON(6), 3, GFLAGS),
919 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
920 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
921
922 /* emmc */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]923 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]924 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
925 RK3399_CLKGATE_CON(6), 14, GFLAGS),
926
927 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
928 RK3399_CLKGATE_CON(6), 12, GFLAGS),
929 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
930 RK3399_CLKGATE_CON(6), 13, GFLAGS),
931 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
932 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
933 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
934 RK3399_CLKGATE_CON(32), 8, GFLAGS),
935 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
936 RK3399_CLKGATE_CON(32), 9, GFLAGS),
937 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
938 RK3399_CLKGATE_CON(32), 10, GFLAGS),
939
940 /* perilp0 */
941 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
942 RK3399_CLKGATE_CON(7), 1, GFLAGS),
943 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
944 RK3399_CLKGATE_CON(7), 0, GFLAGS),
945 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
946 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
947 RK3399_CLKGATE_CON(7), 2, GFLAGS),
948 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
949 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
950 RK3399_CLKGATE_CON(7), 3, GFLAGS),
951 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
952 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
953 RK3399_CLKGATE_CON(7), 4, GFLAGS),
954
955 /* aclk_perilp0 gates */
956 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
957 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
958 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
959 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
960 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
961 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
962 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
963 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
964 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
965 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
966 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]967 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]968
969 /* hclk_perilp0 gates */
970 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]971 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
972 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
973 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
974 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]975 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
976
977 /* pclk_perilp0 gates */
978 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
979
980 /* crypto */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]981 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]982 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
983 RK3399_CLKGATE_CON(7), 7, GFLAGS),
984
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]985 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]986 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
987 RK3399_CLKGATE_CON(7), 8, GFLAGS),
988
989 /* cm0s_perilp */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]990 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]991 RK3399_CLKGATE_CON(7), 6, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]992 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]993 RK3399_CLKGATE_CON(7), 5, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]994 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]995 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
996 RK3399_CLKGATE_CON(7), 9, GFLAGS),
997
998 /* fclk_cm0s gates */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]999 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
1000 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
1001 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
1002 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1003 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1004
1005 /* perilp1 */
1006 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
1007 RK3399_CLKGATE_CON(8), 1, GFLAGS),
1008 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
1009 RK3399_CLKGATE_CON(8), 0, GFLAGS),
1010 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1011 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1012 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1013 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1014 RK3399_CLKGATE_CON(8), 2, GFLAGS),
1015
1016 /* hclk_perilp1 gates */
1017 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1018 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1019 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1020 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1021 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1022 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1023 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1024 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1025 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1026
1027 /* pclk_perilp1 gates */
1028 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1029 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1030 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1031 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1032 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1033 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1034 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1035 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1036 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1037 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1038 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1039 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1040 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1041 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1042 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1043 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1044 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1045 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1046 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1047 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1048 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1049
1050 /* saradc */
1051 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1052 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1053 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1054
1055 /* tsadc */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1056 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1057 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1058 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1059
1060 /* cif_testout */
1061 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1062 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1063 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1064 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1065 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1066
1067 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1068 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1069 COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
1070 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1071 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1072
1073 /* vio */
1074 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1075 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1076 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1077 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1078 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1079 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1080
1081 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1082 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1083
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1084 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1085 RK3399_CLKGATE_CON(29), 1, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1086 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1087 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1088 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1089 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1090
1091 /* hdcp */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1092 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1093 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1094 RK3399_CLKGATE_CON(11), 12, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1095 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1096 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1097 RK3399_CLKGATE_CON(11), 3, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1098 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1099 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1100 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1101
1102 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1103 RK3399_CLKGATE_CON(29), 4, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1104 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1105 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1106
1107 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1108 RK3399_CLKGATE_CON(29), 5, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1109 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1110 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1111
1112 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1113 RK3399_CLKGATE_CON(29), 3, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1114 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1115 RK3399_CLKGATE_CON(29), 6, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1116 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1117 RK3399_CLKGATE_CON(29), 7, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1118 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1119 RK3399_CLKGATE_CON(29), 8, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1120 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1121 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1122
1123 /* edp */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1124 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1125 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1126 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1127
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1128 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1129 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1130 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1131 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1132 RK3399_CLKGATE_CON(32), 12, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1133 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1134 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1135
1136 /* hdmi */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1137 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1138 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1139
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1140 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1141 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1142 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1143
1144 /* vop0 */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1145 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1146 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1147 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1148 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1149 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1150 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1151
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1152 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1153 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1154 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1155 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1156
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1157 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1158 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1159 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1160 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1161
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1162 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1163 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1164 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1165
1166 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1167 RK3399_CLKSEL_CON(106), 0,
1168 &rk3399_dclk_vop0_fracmux),
1169
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1170 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1171 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1172 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1173
1174 /* vop1 */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1175 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1176 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1177 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1178 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1179 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1180 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1181
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1182 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1183 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1184 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1185 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1186
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1187 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1188 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1189 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1190 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1191
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1192 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1193 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1194 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1195
1196 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1197 RK3399_CLKSEL_CON(107), 0,
1198 &rk3399_dclk_vop1_fracmux),
1199
1200 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1201 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1202 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1203
1204 /* isp */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1205 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1206 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1207 RK3399_CLKGATE_CON(12), 8, GFLAGS),
Xing Zheng3f92a052016-04-20 19:06:49 +0800[diff] [blame]1208 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1209 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1210 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1211
1212 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1213 RK3399_CLKGATE_CON(27), 1, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1214 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1215 RK3399_CLKGATE_CON(27), 5, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1216 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1217 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1218
1219 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1220 RK3399_CLKGATE_CON(27), 0, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1221 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1222 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1223
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1224 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1225 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1226 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1227
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1228 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1229 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1230 RK3399_CLKGATE_CON(12), 10, GFLAGS),
Xing Zheng3f92a052016-04-20 19:06:49 +0800[diff] [blame]1231 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1232 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1233 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1234
1235 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1236 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1237
1238 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1239 RK3399_CLKGATE_CON(27), 2, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1240 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1241 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1242
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1243 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1244 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1245 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1246
1247 /*
1248 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1249 * so we ignore the mux and make clocks nodes as following,
1250 *
1251 * pclkin_cifinv --|-------\
1252 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1253 * pclkin_cif --|-------/
1254 */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1255 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1256 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1257
1258 /* cif */
Xing Zhengfd8bc822016-04-20 19:11:32 +0800[diff] [blame]1259 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1260 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1261 RK3399_CLKGATE_CON(10), 7, GFLAGS),
Xing Zhengfd8bc822016-04-20 19:11:32 +0800[diff] [blame]1262
1263 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1264 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1265
1266 /* gic */
1267 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1268 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1269 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1270
1271 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1272 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1273 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1274 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1275 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1276 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1277
1278 /* alive */
1279 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1280 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1281 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1282
1283 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1284 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1285 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1286 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1287 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1288
1289 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1290 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1291 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1292 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1293 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1294 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1295 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1296 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1297 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1298
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1299 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1300 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1301
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1302 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1303 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1304 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1305 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1306
1307 /* testout */
1308 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1309 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1310 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1311 RK3399_CLKSEL_CON(105), 0,
1312 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1313
1314 DIV(0, "clk_test_24m", "xin24m", 0,
1315 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1316
1317 /* spi */
1318 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1319 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1320 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1321
1322 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1323 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1324 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1325
1326 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1327 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1328 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1329
1330 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1331 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1332 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1333
1334 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1335 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1336 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1337
1338 /* i2c */
1339 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1340 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1341 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1342
1343 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1344 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1345 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1346
1347 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1348 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1349 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1350
1351 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1352 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1353 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1354
1355 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1356 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1357 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1358
1359 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1360 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1361 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1362
1363 /* timer */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1364 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1365 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1366 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1367 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1368 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1369 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1370 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1371 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1372 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1373 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1374 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1375 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1376
1377 /* clk_test */
1378 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1379 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1380 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1381 RK3368_CLKGATE_CON(13), 11, GFLAGS),
1382};
1383
1384static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1385 /*
1386 * PMU CRU Clock-Architecture
1387 */
1388
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1389 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1390 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1391
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1392 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1393 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1394
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1395 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1396 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1397 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1398
1399 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1400 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1401 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1402
1403 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1404 RK3399_PMU_CLKSEL_CON(7), 0,
1405 &rk3399_pmuclk_wifi_fracmux),
1406
1407 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1408 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1409
1410 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1411 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1412 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1413
1414 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1415 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
Xing Zhengf3d40912016-04-20 19:12:10 +0800[diff] [blame]1416 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1417
1418 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1419 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
Xing Zhengf3d40912016-04-20 19:12:10 +0800[diff] [blame]1420 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1421
1422 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1423 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1424 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1425 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1426
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1427 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1428 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1429 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1430
1431 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1432 RK3399_PMU_CLKSEL_CON(6), 0,
1433 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1434 &rk3399_uart4_pmu_fracmux),
1435
1436 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1437 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1438
1439 /* pmu clock gates */
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1440 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1441 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1442
1443 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1444
1445 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1446 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1447 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1448 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1449 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1450 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1451 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1452 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1453 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1454 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1455 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1456 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1457 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1458 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1459 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1460 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1461
Xing Zheng50961e82016-04-20 19:06:51 +0800[diff] [blame]1462 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1463 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1464 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1465 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1466 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1467};
1468
1469static const char *const rk3399_cru_critical_clocks[] __initconst = {
1470 "aclk_cci_pre",
Brian Norris176df692016-05-13 11:42:16 -0700[diff] [blame]1471 "aclk_gic",
1472 "aclk_gic_noc",
Chris Zhong54479442016-08-09 11:02:33 -0700[diff] [blame^]1473 "aclk_hdcp_noc",
1474 "hclk_hdcp_noc",
1475 "pclk_hdcp_noc",
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1476 "pclk_perilp0",
1477 "pclk_perilp0",
1478 "hclk_perilp0",
1479 "hclk_perilp0_noc",
1480 "pclk_perilp1",
1481 "pclk_perilp1_noc",
1482 "pclk_perihp",
1483 "pclk_perihp_noc",
1484 "hclk_perihp",
1485 "aclk_perihp",
1486 "aclk_perihp_noc",
1487 "aclk_perilp0",
1488 "aclk_perilp0_noc",
1489 "hclk_perilp1",
1490 "hclk_perilp1_noc",
1491 "aclk_dmac0_perilp",
1492 "gpll_hclk_perilp1_src",
1493 "gpll_aclk_perilp0_src",
1494 "gpll_aclk_perihp_src",
Chris Zhong54479442016-08-09 11:02:33 -0700[diff] [blame^]1495 "aclk_vio_noc",
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1496};
1497
1498static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1499 "ppll",
1500 "pclk_pmu_src",
1501 "fclk_cm0s_src_pmu",
1502 "clk_timer_src_pmu",
1503};
1504
1505static void __init rk3399_clk_init(struct device_node *np)
1506{
1507 struct rockchip_clk_provider *ctx;
1508 void __iomem *reg_base;
Xing Zheng26e0ee12016-05-25 16:51:56 +0800[diff] [blame]1509 struct clk *clk;
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1510
1511 reg_base = of_iomap(np, 0);
1512 if (!reg_base) {
1513 pr_err("%s: could not map cru region\n", __func__);
1514 return;
1515 }
1516
1517 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1518 if (IS_ERR(ctx)) {
1519 pr_err("%s: rockchip clk init failed\n", __func__);
Shawn Lin62d0e71d2016-06-03 08:54:18 +0800[diff] [blame]1520 iounmap(reg_base);
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1521 return;
1522 }
1523
Xing Zheng26e0ee12016-05-25 16:51:56 +0800[diff] [blame]1524 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1525 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
1526 if (IS_ERR(clk))
1527 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1528 __func__, PTR_ERR(clk));
1529 else
1530 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
1531
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1532 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1533 ARRAY_SIZE(rk3399_pll_clks), -1);
1534
1535 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1536 ARRAY_SIZE(rk3399_clk_branches));
1537
1538 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1539 ARRAY_SIZE(rk3399_cru_critical_clocks));
1540
1541 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1542 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1543 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1544 ARRAY_SIZE(rk3399_cpuclkl_rates));
1545
1546 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1547 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1548 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1549 ARRAY_SIZE(rk3399_cpuclkb_rates));
1550
1551 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1552 ROCKCHIP_SOFTRST_HIWORD_MASK);
1553
1554 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1555
1556 rockchip_clk_of_add_provider(np, ctx);
1557}
1558CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1559
1560static void __init rk3399_pmu_clk_init(struct device_node *np)
1561{
1562 struct rockchip_clk_provider *ctx;
1563 void __iomem *reg_base;
1564
1565 reg_base = of_iomap(np, 0);
1566 if (!reg_base) {
1567 pr_err("%s: could not map cru pmu region\n", __func__);
1568 return;
1569 }
1570
1571 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1572 if (IS_ERR(ctx)) {
1573 pr_err("%s: rockchip pmu clk init failed\n", __func__);
Shawn Lin62d0e71d2016-06-03 08:54:18 +0800[diff] [blame]1574 iounmap(reg_base);
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1575 return;
1576 }
1577
1578 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1579 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1580
1581 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1582 ARRAY_SIZE(rk3399_clk_pmu_branches));
1583
1584 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
Heiko Stuebner995d3fd2016-04-19 21:07:01 +0200[diff] [blame]1585 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
Xing Zheng11551002016-03-28 17:51:37 +0800[diff] [blame]1586
1587 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1588 ROCKCHIP_SOFTRST_HIWORD_MASK);
1589
1590 rockchip_clk_of_add_provider(np, ctx);
1591}
1592CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);