blob: 4ebb2e215bac7ccbbbb59a857794de542ac348df [file] [log] [blame]
Qiao Zhou70c6cce2012-07-09 14:37:32 +08001/*
2 * Base driver for Marvell 88PM800
3 *
4 * Copyright (C) 2012 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
6 * Joseph(Yossi) Hanin <yhanin@marvell.com>
7 * Qiao Zhou <zhouqiao@marvell.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
Chao Xie52705342013-06-14 01:21:50 -040025#include <linux/err.h>
Qiao Zhou70c6cce2012-07-09 14:37:32 +080026#include <linux/i2c.h>
27#include <linux/mfd/core.h>
28#include <linux/mfd/88pm80x.h>
29#include <linux/slab.h>
30
31#define PM800_CHIP_ID (0x00)
32
33/* Interrupt Registers */
34#define PM800_INT_STATUS1 (0x05)
35#define PM800_ONKEY_INT_STS1 (1 << 0)
36#define PM800_EXTON_INT_STS1 (1 << 1)
37#define PM800_CHG_INT_STS1 (1 << 2)
38#define PM800_BAT_INT_STS1 (1 << 3)
39#define PM800_RTC_INT_STS1 (1 << 4)
40#define PM800_CLASSD_OC_INT_STS1 (1 << 5)
41
42#define PM800_INT_STATUS2 (0x06)
43#define PM800_VBAT_INT_STS2 (1 << 0)
44#define PM800_VSYS_INT_STS2 (1 << 1)
45#define PM800_VCHG_INT_STS2 (1 << 2)
46#define PM800_TINT_INT_STS2 (1 << 3)
47#define PM800_GPADC0_INT_STS2 (1 << 4)
48#define PM800_TBAT_INT_STS2 (1 << 5)
49#define PM800_GPADC2_INT_STS2 (1 << 6)
50#define PM800_GPADC3_INT_STS2 (1 << 7)
51
52#define PM800_INT_STATUS3 (0x07)
53
54#define PM800_INT_STATUS4 (0x08)
55#define PM800_GPIO0_INT_STS4 (1 << 0)
56#define PM800_GPIO1_INT_STS4 (1 << 1)
57#define PM800_GPIO2_INT_STS4 (1 << 2)
58#define PM800_GPIO3_INT_STS4 (1 << 3)
59#define PM800_GPIO4_INT_STS4 (1 << 4)
60
61#define PM800_INT_ENA_1 (0x09)
62#define PM800_ONKEY_INT_ENA1 (1 << 0)
63#define PM800_EXTON_INT_ENA1 (1 << 1)
64#define PM800_CHG_INT_ENA1 (1 << 2)
65#define PM800_BAT_INT_ENA1 (1 << 3)
66#define PM800_RTC_INT_ENA1 (1 << 4)
67#define PM800_CLASSD_OC_INT_ENA1 (1 << 5)
68
69#define PM800_INT_ENA_2 (0x0A)
70#define PM800_VBAT_INT_ENA2 (1 << 0)
71#define PM800_VSYS_INT_ENA2 (1 << 1)
72#define PM800_VCHG_INT_ENA2 (1 << 2)
73#define PM800_TINT_INT_ENA2 (1 << 3)
74
75#define PM800_INT_ENA_3 (0x0B)
76#define PM800_GPADC0_INT_ENA3 (1 << 0)
77#define PM800_GPADC1_INT_ENA3 (1 << 1)
78#define PM800_GPADC2_INT_ENA3 (1 << 2)
79#define PM800_GPADC3_INT_ENA3 (1 << 3)
80#define PM800_GPADC4_INT_ENA3 (1 << 4)
81
82#define PM800_INT_ENA_4 (0x0C)
83#define PM800_GPIO0_INT_ENA4 (1 << 0)
84#define PM800_GPIO1_INT_ENA4 (1 << 1)
85#define PM800_GPIO2_INT_ENA4 (1 << 2)
86#define PM800_GPIO3_INT_ENA4 (1 << 3)
87#define PM800_GPIO4_INT_ENA4 (1 << 4)
88
89/* number of INT_ENA & INT_STATUS regs */
90#define PM800_INT_REG_NUM (4)
91
92/* Interrupt Number in 88PM800 */
93enum {
94 PM800_IRQ_ONKEY, /*EN1b0 *//*0 */
95 PM800_IRQ_EXTON, /*EN1b1 */
96 PM800_IRQ_CHG, /*EN1b2 */
97 PM800_IRQ_BAT, /*EN1b3 */
98 PM800_IRQ_RTC, /*EN1b4 */
99 PM800_IRQ_CLASSD, /*EN1b5 *//*5 */
100 PM800_IRQ_VBAT, /*EN2b0 */
101 PM800_IRQ_VSYS, /*EN2b1 */
102 PM800_IRQ_VCHG, /*EN2b2 */
103 PM800_IRQ_TINT, /*EN2b3 */
104 PM800_IRQ_GPADC0, /*EN3b0 *//*10 */
105 PM800_IRQ_GPADC1, /*EN3b1 */
106 PM800_IRQ_GPADC2, /*EN3b2 */
107 PM800_IRQ_GPADC3, /*EN3b3 */
108 PM800_IRQ_GPADC4, /*EN3b4 */
109 PM800_IRQ_GPIO0, /*EN4b0 *//*15 */
110 PM800_IRQ_GPIO1, /*EN4b1 */
111 PM800_IRQ_GPIO2, /*EN4b2 */
112 PM800_IRQ_GPIO3, /*EN4b3 */
113 PM800_IRQ_GPIO4, /*EN4b4 *//*19 */
114 PM800_MAX_IRQ,
115};
116
117enum {
118 /* Procida */
119 PM800_CHIP_A0 = 0x60,
120 PM800_CHIP_A1 = 0x61,
121 PM800_CHIP_B0 = 0x62,
122 PM800_CHIP_C0 = 0x63,
123 PM800_CHIP_END = PM800_CHIP_C0,
124
125 /* Make sure to update this to the last stepping */
126 PM8XXX_CHIP_END = PM800_CHIP_END
127};
128
129static const struct i2c_device_id pm80x_id_table[] = {
130 {"88PM800", CHIP_PM800},
Samuel Ortiz31b3ffb2012-07-09 15:11:46 +0200131 {} /* NULL terminated */
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800132};
133MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
134
135static struct resource rtc_resources[] = {
136 {
137 .name = "88pm80x-rtc",
138 .start = PM800_IRQ_RTC,
139 .end = PM800_IRQ_RTC,
140 .flags = IORESOURCE_IRQ,
141 },
142};
143
144static struct mfd_cell rtc_devs[] = {
145 {
146 .name = "88pm80x-rtc",
147 .num_resources = ARRAY_SIZE(rtc_resources),
148 .resources = &rtc_resources[0],
149 .id = -1,
150 },
151};
152
153static struct resource onkey_resources[] = {
154 {
155 .name = "88pm80x-onkey",
156 .start = PM800_IRQ_ONKEY,
157 .end = PM800_IRQ_ONKEY,
158 .flags = IORESOURCE_IRQ,
159 },
160};
161
162static struct mfd_cell onkey_devs[] = {
163 {
164 .name = "88pm80x-onkey",
165 .num_resources = 1,
166 .resources = &onkey_resources[0],
167 .id = -1,
168 },
169};
170
171static const struct regmap_irq pm800_irqs[] = {
172 /* INT0 */
173 [PM800_IRQ_ONKEY] = {
174 .mask = PM800_ONKEY_INT_ENA1,
175 },
176 [PM800_IRQ_EXTON] = {
177 .mask = PM800_EXTON_INT_ENA1,
178 },
179 [PM800_IRQ_CHG] = {
180 .mask = PM800_CHG_INT_ENA1,
181 },
182 [PM800_IRQ_BAT] = {
183 .mask = PM800_BAT_INT_ENA1,
184 },
185 [PM800_IRQ_RTC] = {
186 .mask = PM800_RTC_INT_ENA1,
187 },
188 [PM800_IRQ_CLASSD] = {
189 .mask = PM800_CLASSD_OC_INT_ENA1,
190 },
191 /* INT1 */
192 [PM800_IRQ_VBAT] = {
193 .reg_offset = 1,
194 .mask = PM800_VBAT_INT_ENA2,
195 },
196 [PM800_IRQ_VSYS] = {
197 .reg_offset = 1,
198 .mask = PM800_VSYS_INT_ENA2,
199 },
200 [PM800_IRQ_VCHG] = {
201 .reg_offset = 1,
202 .mask = PM800_VCHG_INT_ENA2,
203 },
204 [PM800_IRQ_TINT] = {
205 .reg_offset = 1,
206 .mask = PM800_TINT_INT_ENA2,
207 },
208 /* INT2 */
209 [PM800_IRQ_GPADC0] = {
210 .reg_offset = 2,
211 .mask = PM800_GPADC0_INT_ENA3,
212 },
213 [PM800_IRQ_GPADC1] = {
214 .reg_offset = 2,
215 .mask = PM800_GPADC1_INT_ENA3,
216 },
217 [PM800_IRQ_GPADC2] = {
218 .reg_offset = 2,
219 .mask = PM800_GPADC2_INT_ENA3,
220 },
221 [PM800_IRQ_GPADC3] = {
222 .reg_offset = 2,
223 .mask = PM800_GPADC3_INT_ENA3,
224 },
225 [PM800_IRQ_GPADC4] = {
226 .reg_offset = 2,
227 .mask = PM800_GPADC4_INT_ENA3,
228 },
229 /* INT3 */
230 [PM800_IRQ_GPIO0] = {
231 .reg_offset = 3,
232 .mask = PM800_GPIO0_INT_ENA4,
233 },
234 [PM800_IRQ_GPIO1] = {
235 .reg_offset = 3,
236 .mask = PM800_GPIO1_INT_ENA4,
237 },
238 [PM800_IRQ_GPIO2] = {
239 .reg_offset = 3,
240 .mask = PM800_GPIO2_INT_ENA4,
241 },
242 [PM800_IRQ_GPIO3] = {
243 .reg_offset = 3,
244 .mask = PM800_GPIO3_INT_ENA4,
245 },
246 [PM800_IRQ_GPIO4] = {
247 .reg_offset = 3,
248 .mask = PM800_GPIO4_INT_ENA4,
249 },
250};
251
Bill Pembertonf791be42012-11-19 13:23:04 -0500252static int device_gpadc_init(struct pm80x_chip *chip,
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800253 struct pm80x_platform_data *pdata)
254{
255 struct pm80x_subchip *subchip = chip->subchip;
256 struct regmap *map = subchip->regmap_gpadc;
257 int data = 0, mask = 0, ret = 0;
258
259 if (!map) {
260 dev_warn(chip->dev,
261 "Warning: gpadc regmap is not available!\n");
262 return -EINVAL;
263 }
264 /*
265 * initialize GPADC without activating it turn on GPADC
266 * measurments
267 */
268 ret = regmap_update_bits(map,
269 PM800_GPADC_MISC_CONFIG2,
270 PM800_GPADC_MISC_GPFSM_EN,
271 PM800_GPADC_MISC_GPFSM_EN);
272 if (ret < 0)
273 goto out;
274 /*
275 * This function configures the ADC as requires for
276 * CP implementation.CP does not "own" the ADC configuration
277 * registers and relies on AP.
278 * Reason: enable automatic ADC measurements needed
279 * for CP to get VBAT and RF temperature readings.
280 */
281 ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
282 PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
283 if (ret < 0)
284 goto out;
285 ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
286 (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
287 (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
288 if (ret < 0)
289 goto out;
290
291 /*
292 * the defult of PM800 is GPADC operates at 100Ks/s rate
293 * and Number of GPADC slots with active current bias prior
294 * to GPADC sampling = 1 slot for all GPADCs set for
295 * Temprature mesurmants
296 */
297 mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
298 PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
299
300 if (pdata && (pdata->batt_det == 0))
301 data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
302 PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
303 else
304 data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
305 PM800_GPADC_GP_BIAS_EN3);
306
307 ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
308 if (ret < 0)
309 goto out;
310
311 dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
312 return 0;
313
314out:
315 dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
316 return ret;
317}
318
Bill Pembertonf791be42012-11-19 13:23:04 -0500319static int device_irq_init_800(struct pm80x_chip *chip)
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800320{
321 struct regmap *map = chip->regmap;
Yi Zhang1ef56772013-06-14 01:21:48 -0400322 unsigned long flags = IRQF_ONESHOT;
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800323 int data, mask, ret = -EINVAL;
324
325 if (!map || !chip->irq) {
326 dev_err(chip->dev, "incorrect parameters\n");
327 return -EINVAL;
328 }
329
330 /*
331 * irq_mode defines the way of clearing interrupt. it's read-clear by
332 * default.
333 */
334 mask =
335 PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
336 PM800_WAKEUP2_INT_MASK;
337
338 data = PM800_WAKEUP2_INT_CLEAR;
339 ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
340
341 if (ret < 0)
342 goto out;
343
344 ret =
345 regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
346 chip->regmap_irq_chip, &chip->irq_data);
347
348out:
349 return ret;
350}
351
352static void device_irq_exit_800(struct pm80x_chip *chip)
353{
354 regmap_del_irq_chip(chip->irq, chip->irq_data);
355}
356
357static struct regmap_irq_chip pm800_irq_chip = {
358 .name = "88pm800",
359 .irqs = pm800_irqs,
360 .num_irqs = ARRAY_SIZE(pm800_irqs),
361
362 .num_regs = 4,
363 .status_base = PM800_INT_STATUS1,
364 .mask_base = PM800_INT_ENA_1,
365 .ack_base = PM800_INT_STATUS1,
Chao Xiecb5c5802013-06-14 01:21:47 -0400366 .mask_invert = 1,
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800367};
368
369static int pm800_pages_init(struct pm80x_chip *chip)
370{
371 struct pm80x_subchip *subchip;
372 struct i2c_client *client = chip->client;
373
Chao Xie52705342013-06-14 01:21:50 -0400374 int ret = 0;
375
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800376 subchip = chip->subchip;
Chao Xie52705342013-06-14 01:21:50 -0400377 if (!subchip || !subchip->power_page_addr || !subchip->gpadc_page_addr)
378 return -ENODEV;
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800379
Chao Xie52705342013-06-14 01:21:50 -0400380 /* PM800 block power page */
381 subchip->power_page = i2c_new_dummy(client->adapter,
382 subchip->power_page_addr);
383 if (subchip->power_page == NULL) {
384 ret = -ENODEV;
385 goto out;
386 }
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800387
Chao Xie52705342013-06-14 01:21:50 -0400388 subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
389 &pm80x_regmap_config);
390 if (IS_ERR(subchip->regmap_power)) {
391 ret = PTR_ERR(subchip->regmap_power);
392 dev_err(chip->dev,
393 "Failed to allocate regmap_power: %d\n", ret);
394 goto out;
395 }
396
397 i2c_set_clientdata(subchip->power_page, chip);
398
399 /* PM800 block GPADC */
400 subchip->gpadc_page = i2c_new_dummy(client->adapter,
401 subchip->gpadc_page_addr);
402 if (subchip->gpadc_page == NULL) {
403 ret = -ENODEV;
404 goto out;
405 }
406
407 subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
408 &pm80x_regmap_config);
409 if (IS_ERR(subchip->regmap_gpadc)) {
410 ret = PTR_ERR(subchip->regmap_gpadc);
411 dev_err(chip->dev,
412 "Failed to allocate regmap_gpadc: %d\n", ret);
413 goto out;
414 }
415 i2c_set_clientdata(subchip->gpadc_page, chip);
416
417out:
418 return ret;
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800419}
420
421static void pm800_pages_exit(struct pm80x_chip *chip)
422{
423 struct pm80x_subchip *subchip;
424
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800425 subchip = chip->subchip;
Chao Xie52705342013-06-14 01:21:50 -0400426
427 if (subchip && subchip->power_page)
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800428 i2c_unregister_device(subchip->power_page);
Chao Xie52705342013-06-14 01:21:50 -0400429
430 if (subchip && subchip->gpadc_page)
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800431 i2c_unregister_device(subchip->gpadc_page);
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800432}
433
Bill Pembertonf791be42012-11-19 13:23:04 -0500434static int device_800_init(struct pm80x_chip *chip,
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800435 struct pm80x_platform_data *pdata)
436{
437 int ret, pmic_id;
Axel Lin46b65a82012-07-11 09:27:54 +0800438 unsigned int val;
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800439
Axel Lin46b65a82012-07-11 09:27:54 +0800440 ret = regmap_read(chip->regmap, PM800_CHIP_ID, &val);
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800441 if (ret < 0) {
442 dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
443 goto out;
444 }
445
Axel Lin46b65a82012-07-11 09:27:54 +0800446 pmic_id = val & PM80X_VERSION_MASK;
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800447
448 if ((pmic_id >= PM800_CHIP_A0) && (pmic_id <= PM800_CHIP_END)) {
Axel Lin46b65a82012-07-11 09:27:54 +0800449 chip->version = val;
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800450 dev_info(chip->dev,
Axel Lin46b65a82012-07-11 09:27:54 +0800451 "88PM80x:Marvell 88PM800 (ID:0x%x) detected\n", val);
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800452 } else {
453 dev_err(chip->dev,
Axel Lin46b65a82012-07-11 09:27:54 +0800454 "Failed to detect Marvell 88PM800:ChipID[0x%x]\n", val);
455 ret = -EINVAL;
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800456 goto out;
457 }
458
459 /*
460 * alarm wake up bit will be clear in device_irq_init(),
461 * read before that
462 */
Axel Lin46b65a82012-07-11 09:27:54 +0800463 ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800464 if (ret < 0) {
465 dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
466 goto out;
467 }
Axel Lin46b65a82012-07-11 09:27:54 +0800468 if (val & PM800_ALARM_WAKEUP) {
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800469 if (pdata && pdata->rtc)
470 pdata->rtc->rtc_wakeup = 1;
471 }
472
473 ret = device_gpadc_init(chip, pdata);
474 if (ret < 0) {
475 dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
476 goto out;
477 }
478
479 chip->regmap_irq_chip = &pm800_irq_chip;
480
481 ret = device_irq_init_800(chip);
482 if (ret < 0) {
483 dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
484 goto out;
485 }
486
487 ret =
488 mfd_add_devices(chip->dev, 0, &onkey_devs[0],
Mark Brown0848c942012-09-11 15:16:36 +0800489 ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
490 NULL);
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800491 if (ret < 0) {
492 dev_err(chip->dev, "Failed to add onkey subdev\n");
493 goto out_dev;
494 } else
495 dev_info(chip->dev, "[%s]:Added mfd onkey_devs\n", __func__);
496
497 if (pdata && pdata->rtc) {
498 rtc_devs[0].platform_data = pdata->rtc;
499 rtc_devs[0].pdata_size = sizeof(struct pm80x_rtc_pdata);
500 ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
Mark Brown0848c942012-09-11 15:16:36 +0800501 ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800502 if (ret < 0) {
503 dev_err(chip->dev, "Failed to add rtc subdev\n");
504 goto out_dev;
505 } else
506 dev_info(chip->dev,
507 "[%s]:Added mfd rtc_devs\n", __func__);
508 }
509
510 return 0;
511out_dev:
512 mfd_remove_devices(chip->dev);
513 device_irq_exit_800(chip);
514out:
515 return ret;
516}
517
Bill Pembertonf791be42012-11-19 13:23:04 -0500518static int pm800_probe(struct i2c_client *client,
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800519 const struct i2c_device_id *id)
520{
521 int ret = 0;
522 struct pm80x_chip *chip;
523 struct pm80x_platform_data *pdata = client->dev.platform_data;
524 struct pm80x_subchip *subchip;
525
526 ret = pm80x_init(client, id);
527 if (ret) {
528 dev_err(&client->dev, "pm800_init fail\n");
529 goto out_init;
530 }
531
532 chip = i2c_get_clientdata(client);
533
534 /* init subchip for PM800 */
535 subchip =
536 devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
537 GFP_KERNEL);
538 if (!subchip) {
539 ret = -ENOMEM;
540 goto err_subchip_alloc;
541 }
542
Chao Xiec750d8e2013-06-14 01:21:49 -0400543 /* pm800 has 2 addtional pages to support power and gpadc. */
544 subchip->power_page_addr = client->addr + 1;
545 subchip->gpadc_page_addr = client->addr + 2;
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800546 chip->subchip = subchip;
547
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800548 ret = pm800_pages_init(chip);
549 if (ret) {
550 dev_err(&client->dev, "pm800_pages_init failed!\n");
551 goto err_page_init;
552 }
553
Yi Zhang618fa572013-06-14 01:21:45 -0400554 ret = device_800_init(chip, pdata);
555 if (ret) {
556 dev_err(chip->dev, "%s id 0x%x failed!\n", __func__, chip->id);
557 goto err_device_init;
558 }
559
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800560 if (pdata->plat_config)
561 pdata->plat_config(chip, pdata);
562
Yi Zhang618fa572013-06-14 01:21:45 -0400563 return 0;
564
565err_device_init:
566 pm800_pages_exit(chip);
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800567err_page_init:
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800568err_subchip_alloc:
Yi Zhang306df792013-01-22 10:43:45 +0800569 pm80x_deinit();
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800570out_init:
571 return ret;
572}
573
Bill Pemberton4740f732012-11-19 13:26:01 -0500574static int pm800_remove(struct i2c_client *client)
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800575{
576 struct pm80x_chip *chip = i2c_get_clientdata(client);
577
578 mfd_remove_devices(chip->dev);
579 device_irq_exit_800(chip);
580
581 pm800_pages_exit(chip);
Yi Zhang306df792013-01-22 10:43:45 +0800582 pm80x_deinit();
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800583
584 return 0;
585}
586
587static struct i2c_driver pm800_driver = {
588 .driver = {
Chao Xie46223a12013-06-14 01:21:46 -0400589 .name = "88PM800",
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800590 .owner = THIS_MODULE,
591 .pm = &pm80x_pm_ops,
592 },
593 .probe = pm800_probe,
Bill Pemberton84449212012-11-19 13:20:24 -0500594 .remove = pm800_remove,
Qiao Zhou70c6cce2012-07-09 14:37:32 +0800595 .id_table = pm80x_id_table,
596};
597
598static int __init pm800_i2c_init(void)
599{
600 return i2c_add_driver(&pm800_driver);
601}
602subsys_initcall(pm800_i2c_init);
603
604static void __exit pm800_i2c_exit(void)
605{
606 i2c_del_driver(&pm800_driver);
607}
608module_exit(pm800_i2c_exit);
609
610MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
611MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
612MODULE_LICENSE("GPL");