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Alan Tull6a8c3be2015-10-07 16:36:28 +01001#
2# FPGA framework configuration
3#
4
Vincent Legoll50fa0282017-06-14 10:36:26 -05005menuconfig FPGA
Alan Tull6a8c3be2015-10-07 16:36:28 +01006 tristate "FPGA Configuration Framework"
7 help
8 Say Y here if you want support for configuring FPGAs from the
9 kernel. The FPGA framework adds a FPGA manager class and FPGA
10 manager drivers.
11
Alan Tullfab62662015-10-07 16:36:29 +010012if FPGA
13
Alan Tull0fa20cd2016-11-01 14:14:29 -050014config FPGA_REGION
15 tristate "FPGA Region"
16 depends on OF && FPGA_BRIDGE
17 help
18 FPGA Regions allow loading FPGA images under control of
19 the Device Tree.
20
Joel Holdsworth21f8ba22017-02-27 16:14:26 -060021config FPGA_MGR_ICE40_SPI
22 tristate "Lattice iCE40 SPI"
23 depends on OF && SPI
24 help
25 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
26
Alan Tullfab62662015-10-07 16:36:29 +010027config FPGA_MGR_SOCFPGA
28 tristate "Altera SOCFPGA FPGA Manager"
Jason Gunthorpea0e1b612016-11-21 22:26:42 +000029 depends on ARCH_SOCFPGA || COMPILE_TEST
Alan Tullfab62662015-10-07 16:36:29 +010030 help
31 FPGA manager driver support for Altera SOCFPGA.
32
Alan Tullacbb910a2016-11-01 14:14:32 -050033config FPGA_MGR_SOCFPGA_A10
34 tristate "Altera SoCFPGA Arria10"
Jason Gunthorpea0e1b612016-11-21 22:26:42 +000035 depends on ARCH_SOCFPGA || COMPILE_TEST
36 select REGMAP_MMIO
Alan Tullacbb910a2016-11-01 14:14:32 -050037 help
38 FPGA manager driver support for Altera Arria10 SoCFPGA.
39
Florian Fainelli4348f7e2017-02-27 16:14:22 -060040config FPGA_MGR_TS73XX
41 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
42 depends on ARCH_EP93XX && MACH_TS72XX
43 help
44 FPGA manager driver support for the Altera Cyclone II FPGA
45 present on the TS-73xx SBC boards.
46
Anatolij Gustschin061c97d2017-03-23 19:34:26 -050047config FPGA_MGR_XILINX_SPI
48 tristate "Xilinx Configuration over Slave Serial (SPI)"
49 depends on SPI
50 help
51 FPGA manager driver support for Xilinx FPGA configuration
52 over slave serial interface.
53
Moritz Fischer37784702015-10-16 15:42:30 -070054config FPGA_MGR_ZYNQ_FPGA
55 tristate "Xilinx Zynq FPGA"
Jean Delvare54e9b0992016-09-08 09:38:05 -050056 depends on ARCH_ZYNQ || COMPILE_TEST
Sudip Mukherjee1c8cb402016-08-03 13:45:46 -070057 depends on HAS_DMA
Moritz Fischer37784702015-10-16 15:42:30 -070058 help
59 FPGA manager driver support for Xilinx Zynq FPGAs.
60
Alan Tull21aeda92016-11-01 14:14:28 -050061config FPGA_BRIDGE
62 tristate "FPGA Bridge Framework"
63 depends on OF
64 help
65 Say Y here if you want to support bridges connected between host
66 processors and FPGAs or between FPGAs.
67
Alan Tulle5f8efa2016-11-01 14:14:30 -050068config SOCFPGA_FPGA_BRIDGE
69 tristate "Altera SoCFPGA FPGA Bridges"
70 depends on ARCH_SOCFPGA && FPGA_BRIDGE
71 help
72 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
73 devices.
74
Alan Tullca24a642016-11-01 14:14:31 -050075config ALTERA_FREEZE_BRIDGE
76 tristate "Altera FPGA Freeze Bridge"
77 depends on ARCH_SOCFPGA && FPGA_BRIDGE
78 help
79 Say Y to enable drivers for Altera FPGA Freeze bridges. A
80 freeze bridge is a bridge that exists in the FPGA fabric to
81 isolate one region of the FPGA from the busses while that
82 region is being reprogrammed.
83
Matthew Gerlachd201cc12017-03-23 19:34:28 -050084config ALTERA_PR_IP_CORE
85 tristate "Altera Partial Reconfiguration IP Core"
86 help
87 Core driver support for Altera Partial Reconfiguration IP component
88
Matthew Gerlach5b73cb52017-03-23 19:34:30 -050089config ALTERA_PR_IP_CORE_PLAT
90 tristate "Platform support of Altera Partial Reconfiguration IP Core"
91 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
92 help
93 Platform driver support for Altera Partial Reconfiguration IP
94 component
95
Moritz Fischer7e961c12017-03-24 10:33:21 -050096config XILINX_PR_DECOUPLER
97 tristate "Xilinx LogiCORE PR Decoupler"
98 depends on FPGA_BRIDGE
99 depends on HAS_IOMEM
100 help
101 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
102 The PR Decoupler exists in the FPGA fabric to isolate one
103 region of the FPGA from the busses while that region is
104 being reprogrammed during partial reconfig.
105
Alan Tullfab62662015-10-07 16:36:29 +0100106endif # FPGA