Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Intel Low Power Subsystem PWM controller driver |
| 3 | * |
| 4 | * Copyright (C) 2014, Intel Corporation |
| 5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
| 6 | * Author: Chew Kean Ho <kean.ho.chew@intel.com> |
| 7 | * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> |
| 8 | * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 9 | * Author: Alan Cox <alan@linux.intel.com> |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
Thierry Reding | e0c86a3 | 2014-08-23 00:22:45 +0200 | [diff] [blame] | 16 | #include <linux/io.h> |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 19 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 20 | #include "pwm-lpss.h" |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 21 | |
| 22 | #define PWM 0x00000000 |
| 23 | #define PWM_ENABLE BIT(31) |
| 24 | #define PWM_SW_UPDATE BIT(30) |
| 25 | #define PWM_BASE_UNIT_SHIFT 8 |
| 26 | #define PWM_BASE_UNIT_MASK 0x00ffff00 |
| 27 | #define PWM_ON_TIME_DIV_MASK 0x000000ff |
| 28 | #define PWM_DIVISION_CORRECTION 0x2 |
| 29 | #define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION) |
| 30 | #define NSECS_PER_SEC 1000000000UL |
| 31 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 32 | /* Size of each PWM register space if multiple */ |
| 33 | #define PWM_SIZE 0x400 |
| 34 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 35 | struct pwm_lpss_chip { |
| 36 | struct pwm_chip chip; |
| 37 | void __iomem *regs; |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 38 | unsigned long clk_rate; |
| 39 | }; |
| 40 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 41 | /* BayTrail */ |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 42 | const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 43 | .clk_rate = 25000000, |
| 44 | .npwm = 1, |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 45 | }; |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 46 | EXPORT_SYMBOL_GPL(pwm_lpss_byt_info); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 47 | |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 48 | /* Braswell */ |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 49 | const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 50 | .clk_rate = 19200000, |
| 51 | .npwm = 1, |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 52 | }; |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 53 | EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info); |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 54 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 55 | static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) |
| 56 | { |
| 57 | return container_of(chip, struct pwm_lpss_chip, chip); |
| 58 | } |
| 59 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 60 | static inline u32 pwm_lpss_read(const struct pwm_device *pwm) |
| 61 | { |
| 62 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); |
| 63 | |
| 64 | return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); |
| 65 | } |
| 66 | |
| 67 | static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) |
| 68 | { |
| 69 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); |
| 70 | |
| 71 | writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); |
| 72 | } |
| 73 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 74 | static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 75 | int duty_ns, int period_ns) |
| 76 | { |
| 77 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
| 78 | u8 on_time_div; |
| 79 | unsigned long c; |
| 80 | unsigned long long base_unit, freq = NSECS_PER_SEC; |
| 81 | u32 ctrl; |
| 82 | |
| 83 | do_div(freq, period_ns); |
| 84 | |
| 85 | /* The equation is: base_unit = ((freq / c) * 65536) + correction */ |
| 86 | base_unit = freq * 65536; |
| 87 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 88 | c = lpwm->clk_rate; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 89 | if (!c) |
| 90 | return -EINVAL; |
| 91 | |
| 92 | do_div(base_unit, c); |
| 93 | base_unit += PWM_DIVISION_CORRECTION; |
| 94 | if (base_unit > PWM_LIMIT) |
| 95 | return -EINVAL; |
| 96 | |
| 97 | if (duty_ns <= 0) |
| 98 | duty_ns = 1; |
| 99 | on_time_div = 255 - (255 * duty_ns / period_ns); |
| 100 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 101 | ctrl = pwm_lpss_read(pwm); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 102 | ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK); |
| 103 | ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT; |
| 104 | ctrl |= on_time_div; |
| 105 | /* request PWM to update on next cycle */ |
| 106 | ctrl |= PWM_SW_UPDATE; |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 107 | pwm_lpss_write(pwm, ctrl); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 113 | { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 114 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 115 | return 0; |
| 116 | } |
| 117 | |
| 118 | static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 119 | { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 120 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | static const struct pwm_ops pwm_lpss_ops = { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 124 | .free = pwm_lpss_disable, |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 125 | .config = pwm_lpss_config, |
| 126 | .enable = pwm_lpss_enable, |
| 127 | .disable = pwm_lpss_disable, |
| 128 | .owner = THIS_MODULE, |
| 129 | }; |
| 130 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 131 | struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, |
| 132 | const struct pwm_lpss_boardinfo *info) |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 133 | { |
| 134 | struct pwm_lpss_chip *lpwm; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 135 | int ret; |
| 136 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 137 | lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 138 | if (!lpwm) |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 139 | return ERR_PTR(-ENOMEM); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 140 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 141 | lpwm->regs = devm_ioremap_resource(dev, r); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 142 | if (IS_ERR(lpwm->regs)) |
Thierry Reding | 89c0339 | 2014-05-07 10:27:57 +0200 | [diff] [blame] | 143 | return ERR_CAST(lpwm->regs); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 144 | |
Heikki Krogerus | 65accd8 | 2014-05-09 11:35:21 +0300 | [diff] [blame] | 145 | lpwm->clk_rate = info->clk_rate; |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 146 | lpwm->chip.dev = dev; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 147 | lpwm->chip.ops = &pwm_lpss_ops; |
| 148 | lpwm->chip.base = -1; |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame^] | 149 | lpwm->chip.npwm = info->npwm; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 150 | |
| 151 | ret = pwmchip_add(&lpwm->chip); |
| 152 | if (ret) { |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 153 | dev_err(dev, "failed to add PWM chip: %d\n", ret); |
| 154 | return ERR_PTR(ret); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 155 | } |
| 156 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 157 | return lpwm; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 158 | } |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 159 | EXPORT_SYMBOL_GPL(pwm_lpss_probe); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 160 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 161 | int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 162 | { |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 163 | return pwmchip_remove(&lpwm->chip); |
| 164 | } |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 165 | EXPORT_SYMBOL_GPL(pwm_lpss_remove); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 166 | |
| 167 | MODULE_DESCRIPTION("PWM driver for Intel LPSS"); |
| 168 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); |
| 169 | MODULE_LICENSE("GPL v2"); |