| Naga Sureshkumar Relli | d2920ef | 2019-04-01 13:28:32 +0530 | [diff] [blame] | 1 | Xilinx Zynq QSPI controller Device Tree Bindings |
| 2 | ------------------------------------------------------------------- |
| 3 | |
| 4 | Required properties: |
| 5 | - compatible : Should be "xlnx,zynq-qspi-1.0". |
| 6 | - reg : Physical base address and size of QSPI registers map. |
| 7 | - interrupts : Property with a value describing the interrupt |
| 8 | number. |
| 9 | - clock-names : List of input clock names - "ref_clk", "pclk" |
| 10 | (See clock bindings for details). |
| 11 | - clocks : Clock phandles (see clock bindings for details). |
| 12 | |
| 13 | Optional properties: |
| 14 | - num-cs : Number of chip selects used. |
| 15 | |
| 16 | Example: |
| 17 | qspi: spi@e000d000 { |
| 18 | compatible = "xlnx,zynq-qspi-1.0"; |
| 19 | reg = <0xe000d000 0x1000>; |
| 20 | interrupt-parent = <&intc>; |
| 21 | interrupts = <0 19 4>; |
| 22 | clock-names = "ref_clk", "pclk"; |
| 23 | clocks = <&clkc 10>, <&clkc 43>; |
| 24 | num-cs = <1>; |
| 25 | }; |