blob: 1fb10733305ab668bd9ccf9f4f9bf2da18861f5a [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Russell Kingd73e60b2008-10-31 13:08:02 +00002/*
3 * linux/arch/arm/mm/copypage-v4wt.S
4 *
5 * Copyright (C) 1995-1999 Russell King
6 *
Russell Kingd73e60b2008-10-31 13:08:02 +00007 * This is for CPUs with a writethrough cache and 'flush ID cache' is
8 * the only supported cache operation.
9 */
10#include <linux/init.h>
Russell King063b0a42008-10-31 15:08:35 +000011#include <linux/highmem.h>
Russell Kingd73e60b2008-10-31 13:08:02 +000012
13/*
Russell King063b0a42008-10-31 15:08:35 +000014 * ARMv4 optimised copy_user_highpage
Russell Kingd73e60b2008-10-31 13:08:02 +000015 *
16 * Since we have writethrough caches, we don't have to worry about
17 * dirty data in the cache. However, we do have to ensure that
18 * subsequent reads are up to date.
19 */
Nicolas Pitreb99afae2018-11-07 17:49:00 +010020static void v4wt_copy_user_page(void *kto, const void *kfrom)
Russell Kingd73e60b2008-10-31 13:08:02 +000021{
Nicolas Pitreb99afae2018-11-07 17:49:00 +010022 int tmp;
23
24 asm volatile ("\
Stefan Agnerb7e8c932019-02-18 00:58:29 +010025 .syntax unified\n\
Nicolas Pitreb99afae2018-11-07 17:49:00 +010026 ldmia %1!, {r3, r4, ip, lr} @ 4\n\
271: stmia %0!, {r3, r4, ip, lr} @ 4\n\
28 ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\
29 stmia %0!, {r3, r4, ip, lr} @ 4\n\
30 ldmia %1!, {r3, r4, ip, lr} @ 4\n\
31 stmia %0!, {r3, r4, ip, lr} @ 4\n\
32 ldmia %1!, {r3, r4, ip, lr} @ 4\n\
33 subs %2, %2, #1 @ 1\n\
34 stmia %0!, {r3, r4, ip, lr} @ 4\n\
Stefan Agnerb7e8c932019-02-18 00:58:29 +010035 ldmiane %1!, {r3, r4, ip, lr} @ 4\n\
Russell Kingd73e60b2008-10-31 13:08:02 +000036 bne 1b @ 1\n\
Nicolas Pitreb99afae2018-11-07 17:49:00 +010037 mcr p15, 0, %2, c7, c7, 0 @ flush ID cache"
38 : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
39 : "2" (PAGE_SIZE / 64)
40 : "r3", "r4", "ip", "lr");
Russell Kingd73e60b2008-10-31 13:08:02 +000041}
42
Russell King063b0a42008-10-31 15:08:35 +000043void v4wt_copy_user_highpage(struct page *to, struct page *from,
Russell Kingf00a75c2009-10-05 15:17:45 +010044 unsigned long vaddr, struct vm_area_struct *vma)
Russell King063b0a42008-10-31 15:08:35 +000045{
46 void *kto, *kfrom;
47
Cong Wang5472e862011-11-25 23:14:15 +080048 kto = kmap_atomic(to);
49 kfrom = kmap_atomic(from);
Russell King063b0a42008-10-31 15:08:35 +000050 v4wt_copy_user_page(kto, kfrom);
Cong Wang5472e862011-11-25 23:14:15 +080051 kunmap_atomic(kfrom);
52 kunmap_atomic(kto);
Russell King063b0a42008-10-31 15:08:35 +000053}
54
Russell Kingd73e60b2008-10-31 13:08:02 +000055/*
56 * ARMv4 optimised clear_user_page
57 *
58 * Same story as above.
59 */
Russell King303c6442008-10-31 16:32:19 +000060void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
Russell Kingd73e60b2008-10-31 13:08:02 +000061{
Cong Wang5472e862011-11-25 23:14:15 +080062 void *ptr, *kaddr = kmap_atomic(page);
Nicolas Pitre43ae2862008-11-04 02:42:27 -050063 asm volatile("\
64 mov r1, %2 @ 1\n\
Russell Kingd73e60b2008-10-31 13:08:02 +000065 mov r2, #0 @ 1\n\
66 mov r3, #0 @ 1\n\
67 mov ip, #0 @ 1\n\
68 mov lr, #0 @ 1\n\
Russell King303c6442008-10-31 16:32:19 +0000691: stmia %0!, {r2, r3, ip, lr} @ 4\n\
70 stmia %0!, {r2, r3, ip, lr} @ 4\n\
71 stmia %0!, {r2, r3, ip, lr} @ 4\n\
72 stmia %0!, {r2, r3, ip, lr} @ 4\n\
Russell Kingd73e60b2008-10-31 13:08:02 +000073 subs r1, r1, #1 @ 1\n\
74 bne 1b @ 1\n\
Russell King303c6442008-10-31 16:32:19 +000075 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache"
Nicolas Pitre43ae2862008-11-04 02:42:27 -050076 : "=r" (ptr)
77 : "0" (kaddr), "I" (PAGE_SIZE / 64)
Russell King303c6442008-10-31 16:32:19 +000078 : "r1", "r2", "r3", "ip", "lr");
Cong Wang5472e862011-11-25 23:14:15 +080079 kunmap_atomic(kaddr);
Russell Kingd73e60b2008-10-31 13:08:02 +000080}
81
82struct cpu_user_fns v4wt_user_fns __initdata = {
Russell King303c6442008-10-31 16:32:19 +000083 .cpu_clear_user_highpage = v4wt_clear_user_highpage,
Russell King063b0a42008-10-31 15:08:35 +000084 .cpu_copy_user_highpage = v4wt_copy_user_highpage,
Russell Kingd73e60b2008-10-31 13:08:02 +000085};