Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 2 | /* |
| 3 | * linux/arch/arm/mm/copypage-v4wt.S |
| 4 | * |
| 5 | * Copyright (C) 1995-1999 Russell King |
| 6 | * |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 7 | * This is for CPUs with a writethrough cache and 'flush ID cache' is |
| 8 | * the only supported cache operation. |
| 9 | */ |
| 10 | #include <linux/init.h> |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 11 | #include <linux/highmem.h> |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 12 | |
| 13 | /* |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 14 | * ARMv4 optimised copy_user_highpage |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 15 | * |
| 16 | * Since we have writethrough caches, we don't have to worry about |
| 17 | * dirty data in the cache. However, we do have to ensure that |
| 18 | * subsequent reads are up to date. |
| 19 | */ |
Nicolas Pitre | b99afae | 2018-11-07 17:49:00 +0100 | [diff] [blame] | 20 | static void v4wt_copy_user_page(void *kto, const void *kfrom) |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 21 | { |
Nicolas Pitre | b99afae | 2018-11-07 17:49:00 +0100 | [diff] [blame] | 22 | int tmp; |
| 23 | |
| 24 | asm volatile ("\ |
Stefan Agner | b7e8c93 | 2019-02-18 00:58:29 +0100 | [diff] [blame] | 25 | .syntax unified\n\ |
Nicolas Pitre | b99afae | 2018-11-07 17:49:00 +0100 | [diff] [blame] | 26 | ldmia %1!, {r3, r4, ip, lr} @ 4\n\ |
| 27 | 1: stmia %0!, {r3, r4, ip, lr} @ 4\n\ |
| 28 | ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\ |
| 29 | stmia %0!, {r3, r4, ip, lr} @ 4\n\ |
| 30 | ldmia %1!, {r3, r4, ip, lr} @ 4\n\ |
| 31 | stmia %0!, {r3, r4, ip, lr} @ 4\n\ |
| 32 | ldmia %1!, {r3, r4, ip, lr} @ 4\n\ |
| 33 | subs %2, %2, #1 @ 1\n\ |
| 34 | stmia %0!, {r3, r4, ip, lr} @ 4\n\ |
Stefan Agner | b7e8c93 | 2019-02-18 00:58:29 +0100 | [diff] [blame] | 35 | ldmiane %1!, {r3, r4, ip, lr} @ 4\n\ |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 36 | bne 1b @ 1\n\ |
Nicolas Pitre | b99afae | 2018-11-07 17:49:00 +0100 | [diff] [blame] | 37 | mcr p15, 0, %2, c7, c7, 0 @ flush ID cache" |
| 38 | : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp) |
| 39 | : "2" (PAGE_SIZE / 64) |
| 40 | : "r3", "r4", "ip", "lr"); |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 41 | } |
| 42 | |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 43 | void v4wt_copy_user_highpage(struct page *to, struct page *from, |
Russell King | f00a75c | 2009-10-05 15:17:45 +0100 | [diff] [blame] | 44 | unsigned long vaddr, struct vm_area_struct *vma) |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 45 | { |
| 46 | void *kto, *kfrom; |
| 47 | |
Cong Wang | 5472e86 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 48 | kto = kmap_atomic(to); |
| 49 | kfrom = kmap_atomic(from); |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 50 | v4wt_copy_user_page(kto, kfrom); |
Cong Wang | 5472e86 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 51 | kunmap_atomic(kfrom); |
| 52 | kunmap_atomic(kto); |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 53 | } |
| 54 | |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 55 | /* |
| 56 | * ARMv4 optimised clear_user_page |
| 57 | * |
| 58 | * Same story as above. |
| 59 | */ |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 60 | void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr) |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 61 | { |
Cong Wang | 5472e86 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 62 | void *ptr, *kaddr = kmap_atomic(page); |
Nicolas Pitre | 43ae286 | 2008-11-04 02:42:27 -0500 | [diff] [blame] | 63 | asm volatile("\ |
| 64 | mov r1, %2 @ 1\n\ |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 65 | mov r2, #0 @ 1\n\ |
| 66 | mov r3, #0 @ 1\n\ |
| 67 | mov ip, #0 @ 1\n\ |
| 68 | mov lr, #0 @ 1\n\ |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 69 | 1: stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
| 70 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
| 71 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
| 72 | stmia %0!, {r2, r3, ip, lr} @ 4\n\ |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 73 | subs r1, r1, #1 @ 1\n\ |
| 74 | bne 1b @ 1\n\ |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 75 | mcr p15, 0, r2, c7, c7, 0 @ flush ID cache" |
Nicolas Pitre | 43ae286 | 2008-11-04 02:42:27 -0500 | [diff] [blame] | 76 | : "=r" (ptr) |
| 77 | : "0" (kaddr), "I" (PAGE_SIZE / 64) |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 78 | : "r1", "r2", "r3", "ip", "lr"); |
Cong Wang | 5472e86 | 2011-11-25 23:14:15 +0800 | [diff] [blame] | 79 | kunmap_atomic(kaddr); |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | struct cpu_user_fns v4wt_user_fns __initdata = { |
Russell King | 303c644 | 2008-10-31 16:32:19 +0000 | [diff] [blame] | 83 | .cpu_clear_user_highpage = v4wt_clear_user_highpage, |
Russell King | 063b0a4 | 2008-10-31 15:08:35 +0000 | [diff] [blame] | 84 | .cpu_copy_user_highpage = v4wt_copy_user_highpage, |
Russell King | d73e60b | 2008-10-31 13:08:02 +0000 | [diff] [blame] | 85 | }; |