| Andy Fleming | 8080d54 | 2006-02-10 17:01:06 -0600 | [diff] [blame] | 1 | /* |
| 2 | * FSL SoC setup code |
| 3 | * |
| 4 | * Maintained by Kumar Gala (see MAINTAINERS for contact information) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/config.h> |
| 13 | #include <linux/stddef.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/pci.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/irq.h> |
| 20 | #include <linux/module.h> |
| 21 | |
| 22 | #include <asm/system.h> |
| 23 | #include <asm/atomic.h> |
| 24 | #include <asm/io.h> |
| 25 | #include <asm/pci-bridge.h> |
| 26 | #include <asm/prom.h> |
| 27 | #include <sysdev/fsl_soc.h> |
| 28 | |
| 29 | #undef DEBUG |
| 30 | |
| 31 | #ifdef DEBUG |
| 32 | #define DBG(x...) printk(x) |
| 33 | #else |
| 34 | #define DBG(x...) |
| 35 | #endif |
| 36 | |
| 37 | int mpc85xx_pci2_busno = 0; |
| 38 | |
| 39 | #ifdef CONFIG_PCI |
| 40 | int __init add_bridge(struct device_node *dev) |
| 41 | { |
| 42 | int len; |
| 43 | struct pci_controller *hose; |
| 44 | struct resource rsrc; |
| 45 | int *bus_range; |
| 46 | int primary = 1, has_address = 0; |
| 47 | phys_addr_t immr = get_immrbase(); |
| 48 | |
| 49 | DBG("Adding PCI host bridge %s\n", dev->full_name); |
| 50 | |
| 51 | /* Fetch host bridge registers address */ |
| 52 | has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); |
| 53 | |
| 54 | /* Get bus range if any */ |
| 55 | bus_range = (int *) get_property(dev, "bus-range", &len); |
| 56 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
| 57 | printk(KERN_WARNING "Can't get bus-range for %s, assume" |
| 58 | " bus 0\n", dev->full_name); |
| 59 | } |
| 60 | |
| 61 | hose = pcibios_alloc_controller(); |
| 62 | if (!hose) |
| 63 | return -ENOMEM; |
| 64 | hose->arch_data = dev; |
| 65 | hose->set_cfg_type = 1; |
| 66 | |
| 67 | hose->first_busno = bus_range ? bus_range[0] : 0; |
| 68 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
| 69 | |
| 70 | /* PCI 1 */ |
| 71 | if ((rsrc.start & 0xfffff) == 0x8000) { |
| 72 | setup_indirect_pci(hose, immr + 0x8000, immr + 0x8004); |
| 73 | } |
| 74 | /* PCI 2 */ |
| 75 | if ((rsrc.start & 0xfffff) == 0x9000) { |
| 76 | setup_indirect_pci(hose, immr + 0x9000, immr + 0x9004); |
| 77 | primary = 0; |
| 78 | hose->bus_offset = hose->first_busno; |
| 79 | mpc85xx_pci2_busno = hose->first_busno; |
| 80 | } |
| 81 | |
| 82 | printk(KERN_INFO "Found MPC85xx PCI host bridge at 0x%08lx. " |
| 83 | "Firmware bus number: %d->%d\n", |
| 84 | rsrc.start, hose->first_busno, hose->last_busno); |
| 85 | |
| 86 | DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
| 87 | hose, hose->cfg_addr, hose->cfg_data); |
| 88 | |
| 89 | /* Interpret the "ranges" property */ |
| 90 | /* This also maps the I/O region and sets isa_io/mem_base */ |
| 91 | pci_process_bridge_OF_ranges(hose, dev, primary); |
| 92 | |
| 93 | return 0; |
| 94 | } |
| 95 | |
| 96 | #endif |