| Thomas Gleixner | e62d949 | 2019-05-20 19:07:58 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Hans-Christian Egtvedt | eafe570 | 2007-07-23 16:01:38 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Driver for the AT73C213 16-bit stereo DAC on Atmel ATSTK1000 |
| 4 | * |
| 5 | * Copyright (C) 2006 - 2007 Atmel Corporation |
| Hans-Christian Egtvedt | eafe570 | 2007-07-23 16:01:38 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _SND_AT73C213_H |
| 9 | #define _SND_AT73C213_H |
| 10 | |
| 11 | /* DAC control register */ |
| 12 | #define DAC_CTRL 0x00 |
| 13 | #define DAC_CTRL_ONPADRV 7 |
| 14 | #define DAC_CTRL_ONAUXIN 6 |
| 15 | #define DAC_CTRL_ONDACR 5 |
| 16 | #define DAC_CTRL_ONDACL 4 |
| 17 | #define DAC_CTRL_ONLNOR 3 |
| 18 | #define DAC_CTRL_ONLNOL 2 |
| 19 | #define DAC_CTRL_ONLNIR 1 |
| 20 | #define DAC_CTRL_ONLNIL 0 |
| 21 | |
| 22 | /* DAC left line in gain register */ |
| 23 | #define DAC_LLIG 0x01 |
| 24 | #define DAC_LLIG_LLIG 0 |
| 25 | |
| 26 | /* DAC right line in gain register */ |
| 27 | #define DAC_RLIG 0x02 |
| 28 | #define DAC_RLIG_RLIG 0 |
| 29 | |
| 30 | /* DAC Left Master Playback Gain Register */ |
| 31 | #define DAC_LMPG 0x03 |
| 32 | #define DAC_LMPG_LMPG 0 |
| 33 | |
| 34 | /* DAC Right Master Playback Gain Register */ |
| 35 | #define DAC_RMPG 0x04 |
| 36 | #define DAC_RMPG_RMPG 0 |
| 37 | |
| 38 | /* DAC Left Line Out Gain Register */ |
| 39 | #define DAC_LLOG 0x05 |
| 40 | #define DAC_LLOG_LLOG 0 |
| 41 | |
| 42 | /* DAC Right Line Out Gain Register */ |
| 43 | #define DAC_RLOG 0x06 |
| 44 | #define DAC_RLOG_RLOG 0 |
| 45 | |
| 46 | /* DAC Output Level Control Register */ |
| 47 | #define DAC_OLC 0x07 |
| 48 | #define DAC_OLC_RSHORT 7 |
| 49 | #define DAC_OLC_ROLC 4 |
| 50 | #define DAC_OLC_LSHORT 3 |
| 51 | #define DAC_OLC_LOLC 0 |
| 52 | |
| 53 | /* DAC Mixer Control Register */ |
| 54 | #define DAC_MC 0x08 |
| 55 | #define DAC_MC_INVR 5 |
| 56 | #define DAC_MC_INVL 4 |
| 57 | #define DAC_MC_RMSMIN2 3 |
| 58 | #define DAC_MC_RMSMIN1 2 |
| 59 | #define DAC_MC_LMSMIN2 1 |
| 60 | #define DAC_MC_LMSMIN1 0 |
| 61 | |
| 62 | /* DAC Clock and Sampling Frequency Control Register */ |
| 63 | #define DAC_CSFC 0x09 |
| 64 | #define DAC_CSFC_OVRSEL 4 |
| 65 | |
| 66 | /* DAC Miscellaneous Register */ |
| 67 | #define DAC_MISC 0x0A |
| 68 | #define DAC_MISC_VCMCAPSEL 7 |
| 69 | #define DAC_MISC_DINTSEL 4 |
| 70 | #define DAC_MISC_DITHEN 3 |
| 71 | #define DAC_MISC_DEEMPEN 2 |
| 72 | #define DAC_MISC_NBITS 0 |
| 73 | |
| 74 | /* DAC Precharge Control Register */ |
| 75 | #define DAC_PRECH 0x0C |
| 76 | #define DAC_PRECH_PRCHGPDRV 7 |
| 77 | #define DAC_PRECH_PRCHGAUX1 6 |
| 78 | #define DAC_PRECH_PRCHGLNOR 5 |
| 79 | #define DAC_PRECH_PRCHGLNOL 4 |
| 80 | #define DAC_PRECH_PRCHGLNIR 3 |
| 81 | #define DAC_PRECH_PRCHGLNIL 2 |
| 82 | #define DAC_PRECH_PRCHG 1 |
| 83 | #define DAC_PRECH_ONMSTR 0 |
| 84 | |
| 85 | /* DAC Auxiliary Input Gain Control Register */ |
| 86 | #define DAC_AUXG 0x0D |
| 87 | #define DAC_AUXG_AUXG 0 |
| 88 | |
| 89 | /* DAC Reset Register */ |
| 90 | #define DAC_RST 0x10 |
| 91 | #define DAC_RST_RESMASK 2 |
| 92 | #define DAC_RST_RESFILZ 1 |
| 93 | #define DAC_RST_RSTZ 0 |
| 94 | |
| 95 | /* Power Amplifier Control Register */ |
| 96 | #define PA_CTRL 0x11 |
| 97 | #define PA_CTRL_APAON 6 |
| 98 | #define PA_CTRL_APAPRECH 5 |
| 99 | #define PA_CTRL_APALP 4 |
| 100 | #define PA_CTRL_APAGAIN 0 |
| 101 | |
| 102 | #endif /* _SND_AT73C213_H */ |