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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 45f035748b2aa29840fec6ba01cd8e44c63034c2 / . / arch / arm / boot / dts / tegra20-plutux.dts
blob: 429e4605fbdb4597da194f88487d0241225d59ce [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Thierry Redinga3ee1292012-09-20 17:06:07 +0200[diff] [blame]2/dts-v1/;
3
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]4#include "tegra20-tamonten.dtsi"
Thierry Redinga3ee1292012-09-20 17:06:07 +0200[diff] [blame]5
6/ {
7 model = "Avionic Design Plutux board";
8 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
9
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]10 host1x@50000000 {
11 hdmi@54280000 {
Thierry Reding358f8892012-11-16 16:56:51 +0100[diff] [blame]12 status = "okay";
13 };
14 };
15
Thierry Redinga3ee1292012-09-20 17:06:07 +0200[diff] [blame]16 i2c@7000c000 {
17 wm8903: wm8903@1a {
18 compatible = "wlf,wm8903";
19 reg = <0x1a>;
20 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]21 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Thierry Redinga3ee1292012-09-20 17:06:07 +0200[diff] [blame]22
23 gpio-controller;
24 #gpio-cells = <2>;
25
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
28 gpio-cfg = <0xffffffff
29 0xffffffff
30 0
31 0xffffffff
32 0xffffffff>;
33 };
34 };
35
36 sound {
37 compatible = "ad,tegra-audio-plutux",
38 "nvidia,tegra-audio-wm8903";
39 nvidia,model = "Avionic Design Plutux";
40
41 nvidia,audio-routing =
42 "Headphone Jack", "HPOUTR",
43 "Headphone Jack", "HPOUTL",
44 "Int Spk", "ROP",
45 "Int Spk", "RON",
46 "Int Spk", "LOP",
47 "Int Spk", "LON",
48 "Mic Jack", "MICBIAS",
49 "IN1L", "Mic Jack";
50
51 nvidia,i2s-controller = <&tegra_i2s1>;
52 nvidia,audio-codec = <&wm8903>;
53
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]54 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
55 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]56
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300[diff] [blame]57 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
59 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]60 clock-names = "pll_a", "pll_a_out0", "mclk";
Thierry Redinga3ee1292012-09-20 17:06:07 +0200[diff] [blame]61 };
Alban Bedel23e63342014-06-19 15:25:49 +0200[diff] [blame]62
63 regulators {
64 vcc_24v_reg: regulator@100 {
65 compatible = "regulator-fixed";
66 reg = <100>;
67 regulator-name = "vcc_24v";
68 regulator-min-microvolt = <24000000>;
69 regulator-max-microvolt = <24000000>;
70 regulator-always-on;
71 };
72
73 vdd_5v0_reg: regulator@101 {
74 compatible = "regulator-fixed";
75 reg = <101>;
76 regulator-name = "vdd_5v0";
77 vin-supply = <&vcc_24v_reg>;
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 regulator-always-on;
81 };
82
83 vdd_3v3_reg: regulator@102 {
84 compatible = "regulator-fixed";
85 reg = <102>;
86 regulator-name = "vdd_3v3";
87 vin-supply = <&vcc_24v_reg>;
88 regulator-min-microvolt = <3300000>;
89 regulator-max-microvolt = <3300000>;
90 regulator-always-on;
91 };
92
93 vdd_1v8_reg: regulator@103 {
94 compatible = "regulator-fixed";
95 reg = <103>;
96 regulator-name = "vdd_1v8";
97 vin-supply = <&vdd_3v3_reg>;
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <1800000>;
100 regulator-always-on;
101 };
102 };
Thierry Redinga3ee1292012-09-20 17:06:07 +0200[diff] [blame]103};