| Pierre-Yves MORDRET | 18d5989 | 2017-09-28 17:36:40 +0200 | [diff] [blame] | 1 | * STMicroelectronics STM32 MDMA controller |
| 2 | |
| 3 | The STM32 MDMA is a general-purpose direct memory access controller capable of |
| 4 | supporting 64 independent DMA channels with 256 HW requests. |
| 5 | |
| 6 | Required properties: |
| 7 | - compatible: Should be "st,stm32h7-mdma" |
| 8 | - reg: Should contain MDMA registers location and length. This should include |
| 9 | all of the per-channel registers. |
| 10 | - interrupts: Should contain the MDMA interrupt. |
| 11 | - clocks: Should contain the input clock of the DMA instance. |
| 12 | - resets: Reference to a reset controller asserting the DMA controller. |
| 13 | - #dma-cells : Must be <5>. See DMA client paragraph for more details. |
| 14 | |
| 15 | Optional properties: |
| 16 | - dma-channels: Number of DMA channels supported by the controller. |
| 17 | - dma-requests: Number of DMA request signals supported by the controller. |
| 18 | - st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via |
| 19 | AHB bus. |
| 20 | |
| 21 | Example: |
| 22 | |
| 23 | mdma1: dma@52000000 { |
| 24 | compatible = "st,stm32h7-mdma"; |
| 25 | reg = <0x52000000 0x1000>; |
| 26 | interrupts = <122>; |
| 27 | clocks = <&timer_clk>; |
| 28 | resets = <&rcc 992>; |
| 29 | #dma-cells = <5>; |
| 30 | dma-channels = <16>; |
| 31 | dma-requests = <32>; |
| 32 | st,ahb-addr-masks = <0x20000000>, <0x00000000>; |
| 33 | }; |
| 34 | |
| 35 | * DMA client |
| 36 | |
| 37 | DMA clients connected to the STM32 MDMA controller must use the format |
| 38 | described in the dma.txt file, using a five-cell specifier for each channel: |
| 39 | a phandle to the MDMA controller plus the following five integer cells: |
| 40 | |
| 41 | 1. The request line number |
| 42 | 2. The priority level |
| 43 | 0x00: Low |
| 44 | 0x01: Medium |
| 45 | 0x10: High |
| 46 | 0x11: Very high |
| 47 | 3. A 32bit mask specifying the DMA channel configuration |
| 48 | -bit 0-1: Source increment mode |
| 49 | 0x00: Source address pointer is fixed |
| 50 | 0x10: Source address pointer is incremented after each data transfer |
| 51 | 0x11: Source address pointer is decremented after each data transfer |
| 52 | -bit 2-3: Destination increment mode |
| 53 | 0x00: Destination address pointer is fixed |
| 54 | 0x10: Destination address pointer is incremented after each data |
| 55 | transfer |
| 56 | 0x11: Destination address pointer is decremented after each data |
| 57 | transfer |
| 58 | -bit 8-9: Source increment offset size |
| 59 | 0x00: byte (8bit) |
| 60 | 0x01: half-word (16bit) |
| 61 | 0x10: word (32bit) |
| 62 | 0x11: double-word (64bit) |
| 63 | -bit 10-11: Destination increment offset size |
| 64 | 0x00: byte (8bit) |
| 65 | 0x01: half-word (16bit) |
| 66 | 0x10: word (32bit) |
| 67 | 0x11: double-word (64bit) |
| 68 | -bit 25-18: The number of bytes to be transferred in a single transfer |
| 69 | (min = 1 byte, max = 128 bytes) |
| 70 | -bit 29:28: Trigger Mode |
| 71 | 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes) |
| 72 | 0x01: Each MDMA request triggers a block transfer (max 64K bytes) |
| 73 | 0x10: Each MDMA request triggers a repeated block transfer |
| 74 | 0x11: Each MDMA request triggers a linked list transfer |
| 75 | 4. A 32bit value specifying the register to be used to acknowledge the request |
| 76 | if no HW ack signal is used by the MDMA client |
| 77 | 5. A 32bit mask specifying the value to be written to acknowledge the request |
| 78 | if no HW ack signal is used by the MDMA client |
| 79 | |
| 80 | Example: |
| 81 | |
| 82 | i2c4: i2c@5c002000 { |
| 83 | compatible = "st,stm32f7-i2c"; |
| 84 | reg = <0x5c002000 0x400>; |
| 85 | interrupts = <95>, |
| 86 | <96>; |
| 87 | clocks = <&timer_clk>; |
| 88 | #address-cells = <1>; |
| 89 | #size-cells = <0>; |
| 90 | dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, |
| 91 | <&mdma1 37 0x0 0x40002 0x0 0x0>; |
| 92 | dma-names = "rx", "tx"; |
| 93 | status = "disabled"; |
| 94 | }; |