| Chen-Yu Tsai | 783ab76 | 2017-01-28 20:22:36 +0800 | [diff] [blame] | 1 | Allwinner A80 Display Engine Clock Control Binding |
| 2 | -------------------------------------------------- |
| 3 | |
| 4 | Required properties : |
| 5 | - compatible: must contain one of the following compatibles: |
| 6 | - "allwinner,sun9i-a80-de-clks" |
| 7 | |
| 8 | - reg: Must contain the registers base address and length |
| 9 | - clocks: phandle to the clocks feeding the display engine subsystem. |
| 10 | Three are needed: |
| 11 | - "mod": the display engine module clock |
| 12 | - "dram": the DRAM bus clock for the system |
| 13 | - "bus": the bus clock for the whole display engine subsystem |
| 14 | - clock-names: Must contain the clock names described just above |
| 15 | - resets: phandle to the reset control for the display engine subsystem. |
| 16 | - #clock-cells : must contain 1 |
| 17 | - #reset-cells : must contain 1 |
| 18 | |
| 19 | Example: |
| 20 | de_clocks: clock@3000000 { |
| 21 | compatible = "allwinner,sun9i-a80-de-clks"; |
| 22 | reg = <0x03000000 0x30>; |
| 23 | clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; |
| 24 | clock-names = "mod", "dram", "bus"; |
| 25 | resets = <&ccu RST_BUS_DE>; |
| 26 | #clock-cells = <1>; |
| 27 | #reset-cells = <1>; |
| 28 | }; |